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Merge remote branch 'upstream/gallium-0.1' into gallium-0.1
[mesa.git] / src / gallium / drivers / nv30 / nv30_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_util.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/util/tgsi_parse.h"
8 #include "tgsi/util/tgsi_util.h"
9
10 #include "nv30_context.h"
11
12 #define SWZ_X 0
13 #define SWZ_Y 1
14 #define SWZ_Z 2
15 #define SWZ_W 3
16 #define MASK_X 1
17 #define MASK_Y 2
18 #define MASK_Z 4
19 #define MASK_W 8
20 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
21 #define DEF_SCALE NV30_FP_OP_DST_SCALE_1X
22 #define DEF_CTEST NV30_FP_OP_COND_TR
23 #include "nv30_shader.h"
24
25 #define swz(s,x,y,z,w) nv30_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
26 #define neg(s) nv30_sr_neg((s))
27 #define abs(s) nv30_sr_abs((s))
28 #define scale(s,v) nv30_sr_scale((s), NV30_FP_OP_DST_SCALE_##v)
29
30 #define MAX_CONSTS 128
31 #define MAX_IMM 32
32 struct nv30_fpc {
33 struct nv30_fragment_program *fp;
34
35 uint attrib_map[PIPE_MAX_SHADER_INPUTS];
36
37 int high_temp;
38 int temp_temp_count;
39 int num_regs;
40
41 uint depth_id;
42 uint colour_id;
43
44 unsigned inst_offset;
45
46 struct {
47 int pipe;
48 float vals[4];
49 } consts[MAX_CONSTS];
50 int nr_consts;
51
52 struct nv30_sreg imm[MAX_IMM];
53 unsigned nr_imm;
54 };
55
56 static INLINE struct nv30_sreg
57 temp(struct nv30_fpc *fpc)
58 {
59 int idx;
60
61 idx = fpc->temp_temp_count++;
62 idx += fpc->high_temp + 1;
63 return nv30_sr(NV30SR_TEMP, idx);
64 }
65
66 static INLINE struct nv30_sreg
67 constant(struct nv30_fpc *fpc, int pipe, float vals[4])
68 {
69 int idx;
70
71 if (fpc->nr_consts == MAX_CONSTS)
72 assert(0);
73 idx = fpc->nr_consts++;
74
75 fpc->consts[idx].pipe = pipe;
76 if (pipe == -1)
77 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
78 return nv30_sr(NV30SR_CONST, idx);
79 }
80
81 #define arith(cc,s,o,d,m,s0,s1,s2) \
82 nv30_fp_arith((cc), (s), NV30_FP_OP_OPCODE_##o, \
83 (d), (m), (s0), (s1), (s2))
84 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
85 nv30_fp_tex((cc), (s), NV30_FP_OP_OPCODE_##o, (u), \
86 (d), (m), (s0), none, none)
87
88 static void
89 grow_insns(struct nv30_fpc *fpc, int size)
90 {
91 struct nv30_fragment_program *fp = fpc->fp;
92
93 fp->insn_len += size;
94 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
95 }
96
97 static void
98 emit_src(struct nv30_fpc *fpc, int pos, struct nv30_sreg src)
99 {
100 struct nv30_fragment_program *fp = fpc->fp;
101 uint32_t *hw = &fp->insn[fpc->inst_offset];
102 uint32_t sr = 0;
103
104 switch (src.type) {
105 case NV30SR_INPUT:
106 sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT);
107 hw[0] |= (src.index << NV30_FP_OP_INPUT_SRC_SHIFT);
108 break;
109 case NV30SR_OUTPUT:
110 sr |= NV30_FP_REG_SRC_HALF;
111 /* fall-through */
112 case NV30SR_TEMP:
113 sr |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT);
114 sr |= (src.index << NV30_FP_REG_SRC_SHIFT);
115 break;
116 case NV30SR_CONST:
117 grow_insns(fpc, 4);
118 hw = &fp->insn[fpc->inst_offset];
119 if (fpc->consts[src.index].pipe >= 0) {
120 struct nv30_fragment_program_data *fpd;
121
122 fp->consts = realloc(fp->consts, ++fp->nr_consts *
123 sizeof(*fpd));
124 fpd = &fp->consts[fp->nr_consts - 1];
125 fpd->offset = fpc->inst_offset + 4;
126 fpd->index = fpc->consts[src.index].pipe;
127 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
128 } else {
129 memcpy(&fp->insn[fpc->inst_offset + 4],
130 fpc->consts[src.index].vals,
131 sizeof(uint32_t) * 4);
132 }
133
134 sr |= (NV30_FP_REG_TYPE_CONST << NV30_FP_REG_TYPE_SHIFT);
135 break;
136 case NV30SR_NONE:
137 sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT);
138 break;
139 default:
140 assert(0);
141 }
142
143 if (src.negate)
144 sr |= NV30_FP_REG_NEGATE;
145
146 if (src.abs)
147 hw[1] |= (1 << (29 + pos));
148
149 sr |= ((src.swz[0] << NV30_FP_REG_SWZ_X_SHIFT) |
150 (src.swz[1] << NV30_FP_REG_SWZ_Y_SHIFT) |
151 (src.swz[2] << NV30_FP_REG_SWZ_Z_SHIFT) |
152 (src.swz[3] << NV30_FP_REG_SWZ_W_SHIFT));
153
154 hw[pos + 1] |= sr;
155 }
156
157 static void
158 emit_dst(struct nv30_fpc *fpc, struct nv30_sreg dst)
159 {
160 struct nv30_fragment_program *fp = fpc->fp;
161 uint32_t *hw = &fp->insn[fpc->inst_offset];
162
163 switch (dst.type) {
164 case NV30SR_TEMP:
165 if (fpc->num_regs < (dst.index + 1))
166 fpc->num_regs = dst.index + 1;
167 break;
168 case NV30SR_OUTPUT:
169 if (dst.index == 1) {
170 fp->fp_control |= 0xe;
171 } else {
172 hw[0] |= NV30_FP_OP_OUT_REG_HALF;
173 }
174 break;
175 case NV30SR_NONE:
176 hw[0] |= (1 << 30);
177 break;
178 default:
179 assert(0);
180 }
181
182 hw[0] |= (dst.index << NV30_FP_OP_OUT_REG_SHIFT);
183 }
184
185 static void
186 nv30_fp_arith(struct nv30_fpc *fpc, int sat, int op,
187 struct nv30_sreg dst, int mask,
188 struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2)
189 {
190 struct nv30_fragment_program *fp = fpc->fp;
191 uint32_t *hw;
192
193 fpc->inst_offset = fp->insn_len;
194 grow_insns(fpc, 4);
195 hw = &fp->insn[fpc->inst_offset];
196 memset(hw, 0, sizeof(uint32_t) * 4);
197
198 if (op == NV30_FP_OP_OPCODE_KIL)
199 fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
200 hw[0] |= (op << NV30_FP_OP_OPCODE_SHIFT);
201 hw[0] |= (mask << NV30_FP_OP_OUTMASK_SHIFT);
202 hw[2] |= (dst.dst_scale << NV30_FP_OP_DST_SCALE_SHIFT);
203
204 if (sat)
205 hw[0] |= NV30_FP_OP_OUT_SAT;
206
207 if (dst.cc_update)
208 hw[0] |= NV30_FP_OP_COND_WRITE_ENABLE;
209 hw[1] |= (dst.cc_test << NV30_FP_OP_COND_SHIFT);
210 hw[1] |= ((dst.cc_swz[0] << NV30_FP_OP_COND_SWZ_X_SHIFT) |
211 (dst.cc_swz[1] << NV30_FP_OP_COND_SWZ_Y_SHIFT) |
212 (dst.cc_swz[2] << NV30_FP_OP_COND_SWZ_Z_SHIFT) |
213 (dst.cc_swz[3] << NV30_FP_OP_COND_SWZ_W_SHIFT));
214
215 emit_dst(fpc, dst);
216 emit_src(fpc, 0, s0);
217 emit_src(fpc, 1, s1);
218 emit_src(fpc, 2, s2);
219 }
220
221 static void
222 nv30_fp_tex(struct nv30_fpc *fpc, int sat, int op, int unit,
223 struct nv30_sreg dst, int mask,
224 struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2)
225 {
226 struct nv30_fragment_program *fp = fpc->fp;
227
228 nv30_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
229
230 fp->insn[fpc->inst_offset] |= (unit << NV30_FP_OP_TEX_UNIT_SHIFT);
231 fp->samplers |= (1 << unit);
232 }
233
234 static INLINE struct nv30_sreg
235 tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc)
236 {
237 struct nv30_sreg src;
238
239 switch (fsrc->SrcRegister.File) {
240 case TGSI_FILE_INPUT:
241 src = nv30_sr(NV30SR_INPUT,
242 fpc->attrib_map[fsrc->SrcRegister.Index]);
243 break;
244 case TGSI_FILE_CONSTANT:
245 src = constant(fpc, fsrc->SrcRegister.Index, NULL);
246 break;
247 case TGSI_FILE_IMMEDIATE:
248 assert(fsrc->SrcRegister.Index < fpc->nr_imm);
249 src = fpc->imm[fsrc->SrcRegister.Index];
250 break;
251 case TGSI_FILE_TEMPORARY:
252 src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index + 1);
253 if (fpc->high_temp < src.index)
254 fpc->high_temp = src.index;
255 break;
256 /* This is clearly insane, but gallium hands us shaders like this.
257 * Luckily fragprog results are just temp regs..
258 */
259 case TGSI_FILE_OUTPUT:
260 if (fsrc->SrcRegister.Index == fpc->colour_id)
261 return nv30_sr(NV30SR_OUTPUT, 0);
262 else
263 return nv30_sr(NV30SR_OUTPUT, 1);
264 break;
265 default:
266 NOUVEAU_ERR("bad src file\n");
267 break;
268 }
269
270 src.abs = fsrc->SrcRegisterExtMod.Absolute;
271 src.negate = fsrc->SrcRegister.Negate;
272 src.swz[0] = fsrc->SrcRegister.SwizzleX;
273 src.swz[1] = fsrc->SrcRegister.SwizzleY;
274 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
275 src.swz[3] = fsrc->SrcRegister.SwizzleW;
276 return src;
277 }
278
279 static INLINE struct nv30_sreg
280 tgsi_dst(struct nv30_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
281 int idx;
282
283 switch (fdst->DstRegister.File) {
284 case TGSI_FILE_OUTPUT:
285 if (fdst->DstRegister.Index == fpc->colour_id)
286 return nv30_sr(NV30SR_OUTPUT, 0);
287 else
288 return nv30_sr(NV30SR_OUTPUT, 1);
289 break;
290 case TGSI_FILE_TEMPORARY:
291 idx = fdst->DstRegister.Index + 1;
292 if (fpc->high_temp < idx)
293 fpc->high_temp = idx;
294 return nv30_sr(NV30SR_TEMP, idx);
295 case TGSI_FILE_NULL:
296 return nv30_sr(NV30SR_NONE, 0);
297 default:
298 NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
299 return nv30_sr(NV30SR_NONE, 0);
300 }
301 }
302
303 static INLINE int
304 tgsi_mask(uint tgsi)
305 {
306 int mask = 0;
307
308 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
309 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
310 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
311 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
312 return mask;
313 }
314
315 static boolean
316 src_native_swz(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc,
317 struct nv30_sreg *src)
318 {
319 const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0);
320 struct nv30_sreg tgsi = tgsi_src(fpc, fsrc);
321 uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
322 uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
323 fsrc->SrcRegisterExtSwz.NegateY,
324 fsrc->SrcRegisterExtSwz.NegateZ,
325 fsrc->SrcRegisterExtSwz.NegateW };
326 uint c;
327
328 for (c = 0; c < 4; c++) {
329 switch (tgsi_util_get_full_src_register_extswizzle(fsrc, c)) {
330 case TGSI_EXTSWIZZLE_X:
331 case TGSI_EXTSWIZZLE_Y:
332 case TGSI_EXTSWIZZLE_Z:
333 case TGSI_EXTSWIZZLE_W:
334 mask |= (1 << c);
335 break;
336 case TGSI_EXTSWIZZLE_ZERO:
337 zero_mask |= (1 << c);
338 tgsi.swz[c] = SWZ_X;
339 break;
340 case TGSI_EXTSWIZZLE_ONE:
341 one_mask |= (1 << c);
342 tgsi.swz[c] = SWZ_X;
343 break;
344 default:
345 assert(0);
346 }
347
348 if (!tgsi.negate && neg[c])
349 neg_mask |= (1 << c);
350 }
351
352 if (mask == MASK_ALL && !neg_mask)
353 return TRUE;
354
355 *src = temp(fpc);
356
357 if (mask)
358 arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
359
360 if (zero_mask)
361 arith(fpc, 0, SFL, *src, zero_mask, *src, none, none);
362
363 if (one_mask)
364 arith(fpc, 0, STR, *src, one_mask, *src, none, none);
365
366 if (neg_mask) {
367 struct nv30_sreg one = temp(fpc);
368 arith(fpc, 0, STR, one, neg_mask, one, none, none);
369 arith(fpc, 0, MUL, *src, neg_mask, *src, neg(one), none);
370 }
371
372 return FALSE;
373 }
374
375 static boolean
376 nv30_fragprog_parse_instruction(struct nv30_fpc *fpc,
377 const struct tgsi_full_instruction *finst)
378 {
379 const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0);
380 struct nv30_sreg src[3], dst, tmp;
381 int mask, sat, unit = 0;
382 int ai = -1, ci = -1;
383 int i;
384
385 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
386 return TRUE;
387
388 fpc->temp_temp_count = 0;
389 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
390 const struct tgsi_full_src_register *fsrc;
391
392 fsrc = &finst->FullSrcRegisters[i];
393 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
394 src[i] = tgsi_src(fpc, fsrc);
395 }
396 }
397
398 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
399 const struct tgsi_full_src_register *fsrc;
400
401 fsrc = &finst->FullSrcRegisters[i];
402
403 switch (fsrc->SrcRegister.File) {
404 case TGSI_FILE_INPUT:
405 case TGSI_FILE_CONSTANT:
406 case TGSI_FILE_TEMPORARY:
407 if (!src_native_swz(fpc, fsrc, &src[i]))
408 continue;
409 break;
410 default:
411 break;
412 }
413
414 switch (fsrc->SrcRegister.File) {
415 case TGSI_FILE_INPUT:
416 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
417 ai = fsrc->SrcRegister.Index;
418 src[i] = tgsi_src(fpc, fsrc);
419 } else {
420 NOUVEAU_MSG("extra src attr %d\n",
421 fsrc->SrcRegister.Index);
422 src[i] = temp(fpc);
423 arith(fpc, 0, MOV, src[i], MASK_ALL,
424 tgsi_src(fpc, fsrc), none, none);
425 }
426 break;
427 case TGSI_FILE_CONSTANT:
428 case TGSI_FILE_IMMEDIATE:
429 if (ci == -1 || ci == fsrc->SrcRegister.Index) {
430 ci = fsrc->SrcRegister.Index;
431 src[i] = tgsi_src(fpc, fsrc);
432 } else {
433 src[i] = temp(fpc);
434 arith(fpc, 0, MOV, src[i], MASK_ALL,
435 tgsi_src(fpc, fsrc), none, none);
436 }
437 break;
438 case TGSI_FILE_TEMPORARY:
439 /* handled above */
440 break;
441 case TGSI_FILE_SAMPLER:
442 unit = fsrc->SrcRegister.Index;
443 break;
444 case TGSI_FILE_OUTPUT:
445 break;
446 default:
447 NOUVEAU_ERR("bad src file\n");
448 return FALSE;
449 }
450 }
451
452 dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
453 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
454 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
455
456 switch (finst->Instruction.Opcode) {
457 case TGSI_OPCODE_ABS:
458 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
459 break;
460 case TGSI_OPCODE_ADD:
461 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
462 break;
463 case TGSI_OPCODE_CMP:
464 tmp = temp(fpc);
465 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
466 tmp.cc_update = 1;
467 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
468 dst.cc_test = NV30_VP_INST_COND_LT;
469 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
470 break;
471 case TGSI_OPCODE_COS:
472 arith(fpc, sat, COS, dst, mask, src[0], none, none);
473 break;
474 case TGSI_OPCODE_DP3:
475 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
476 break;
477 case TGSI_OPCODE_DP4:
478 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
479 break;
480 case TGSI_OPCODE_DPH:
481 tmp = temp(fpc);
482 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
483 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
484 swz(src[1], W, W, W, W), none);
485 break;
486 case TGSI_OPCODE_DST:
487 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
488 break;
489 case TGSI_OPCODE_EX2:
490 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
491 break;
492 case TGSI_OPCODE_FLR:
493 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
494 break;
495 case TGSI_OPCODE_FRC:
496 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
497 break;
498 case TGSI_OPCODE_KIL:
499 arith(fpc, 0, KIL, none, 0, none, none, none);
500 break;
501 case TGSI_OPCODE_KILP:
502 dst = nv30_sr(NV30SR_NONE, 0);
503 dst.cc_update = 1;
504 arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none);
505 dst.cc_update = 0; dst.cc_test = NV30_FP_OP_COND_LT;
506 arith(fpc, 0, KIL, dst, 0, none, none, none);
507 break;
508 case TGSI_OPCODE_LG2:
509 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
510 break;
511 // case TGSI_OPCODE_LIT:
512 case TGSI_OPCODE_LRP:
513 tmp = temp(fpc);
514 arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
515 arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
516 break;
517 case TGSI_OPCODE_MAD:
518 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
519 break;
520 case TGSI_OPCODE_MAX:
521 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
522 break;
523 case TGSI_OPCODE_MIN:
524 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
525 break;
526 case TGSI_OPCODE_MOV:
527 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
528 break;
529 case TGSI_OPCODE_MUL:
530 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
531 break;
532 case TGSI_OPCODE_POW:
533 tmp = temp(fpc);
534 arith(fpc, 0, LG2, tmp, MASK_X,
535 swz(src[0], X, X, X, X), none, none);
536 arith(fpc, 0, MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
537 swz(src[1], X, X, X, X), none);
538 arith(fpc, sat, EX2, dst, mask,
539 swz(tmp, X, X, X, X), none, none);
540 break;
541 case TGSI_OPCODE_RCP:
542 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
543 break;
544 case TGSI_OPCODE_RET:
545 assert(0);
546 break;
547 case TGSI_OPCODE_RFL:
548 tmp = temp(fpc);
549 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[0], none);
550 arith(fpc, 0, DP3, tmp, MASK_Y, src[0], src[1], none);
551 arith(fpc, 0, DIV, scale(tmp, 2X), MASK_Z,
552 swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
553 arith(fpc, sat, MAD, dst, mask,
554 swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
555 break;
556 case TGSI_OPCODE_RSQ:
557 tmp = temp(fpc);
558 arith(fpc, 0, LG2, scale(tmp, INV_2X), MASK_X,
559 abs(swz(src[0], X, X, X, X)), none, none);
560 arith(fpc, sat, EX2, dst, mask,
561 neg(swz(tmp, X, X, X, X)), none, none);
562 break;
563 case TGSI_OPCODE_SCS:
564 if (mask & MASK_X) {
565 arith(fpc, sat, COS, dst, MASK_X,
566 swz(src[0], X, X, X, X), none, none);
567 }
568 if (mask & MASK_Y) {
569 arith(fpc, sat, SIN, dst, MASK_Y,
570 swz(src[0], X, X, X, X), none, none);
571 }
572 break;
573 case TGSI_OPCODE_SIN:
574 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
575 break;
576 case TGSI_OPCODE_SGE:
577 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
578 break;
579 case TGSI_OPCODE_SLT:
580 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
581 break;
582 case TGSI_OPCODE_SUB:
583 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
584 break;
585 case TGSI_OPCODE_TEX:
586 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
587 break;
588 case TGSI_OPCODE_TXB:
589 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
590 break;
591 case TGSI_OPCODE_TXP:
592 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
593 break;
594 case TGSI_OPCODE_XPD:
595 tmp = temp(fpc);
596 arith(fpc, 0, MUL, tmp, mask,
597 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
598 arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
599 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
600 neg(tmp));
601 break;
602 default:
603 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
604 return FALSE;
605 }
606
607 return TRUE;
608 }
609
610 static boolean
611 nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc,
612 const struct tgsi_full_declaration *fdec)
613 {
614 int hw;
615
616 switch (fdec->Semantic.SemanticName) {
617 case TGSI_SEMANTIC_POSITION:
618 hw = NV30_FP_OP_INPUT_SRC_POSITION;
619 break;
620 case TGSI_SEMANTIC_COLOR:
621 if (fdec->Semantic.SemanticIndex == 0) {
622 hw = NV30_FP_OP_INPUT_SRC_COL0;
623 } else
624 if (fdec->Semantic.SemanticIndex == 1) {
625 hw = NV30_FP_OP_INPUT_SRC_COL1;
626 } else {
627 NOUVEAU_ERR("bad colour semantic index\n");
628 return FALSE;
629 }
630 break;
631 case TGSI_SEMANTIC_FOG:
632 hw = NV30_FP_OP_INPUT_SRC_FOGC;
633 break;
634 case TGSI_SEMANTIC_GENERIC:
635 if (fdec->Semantic.SemanticIndex <= 7) {
636 hw = NV30_FP_OP_INPUT_SRC_TC(fdec->Semantic.
637 SemanticIndex);
638 } else {
639 NOUVEAU_ERR("bad generic semantic index\n");
640 return FALSE;
641 }
642 break;
643 default:
644 NOUVEAU_ERR("bad input semantic\n");
645 return FALSE;
646 }
647
648 fpc->attrib_map[fdec->DeclarationRange.First] = hw;
649 return TRUE;
650 }
651
652 static boolean
653 nv30_fragprog_parse_decl_output(struct nv30_fpc *fpc,
654 const struct tgsi_full_declaration *fdec)
655 {
656 switch (fdec->Semantic.SemanticName) {
657 case TGSI_SEMANTIC_POSITION:
658 fpc->depth_id = fdec->DeclarationRange.First;
659 break;
660 case TGSI_SEMANTIC_COLOR:
661 fpc->colour_id = fdec->DeclarationRange.First;
662 break;
663 default:
664 NOUVEAU_ERR("bad output semantic\n");
665 return FALSE;
666 }
667
668 return TRUE;
669 }
670
671 void
672 nv30_fragprog_translate(struct nv30_context *nv30,
673 struct nv30_fragment_program *fp)
674 {
675 struct tgsi_parse_context parse;
676 struct nv30_fpc *fpc = NULL;
677
678 fpc = CALLOC(1, sizeof(struct nv30_fpc));
679 if (!fpc)
680 return;
681 fpc->fp = fp;
682 fpc->high_temp = -1;
683 fpc->num_regs = 2;
684
685 tgsi_parse_init(&parse, fp->pipe.tokens);
686
687 while (!tgsi_parse_end_of_tokens(&parse)) {
688 tgsi_parse_token(&parse);
689
690 switch (parse.FullToken.Token.Type) {
691 case TGSI_TOKEN_TYPE_DECLARATION:
692 {
693 const struct tgsi_full_declaration *fdec;
694 fdec = &parse.FullToken.FullDeclaration;
695 switch (fdec->Declaration.File) {
696 case TGSI_FILE_INPUT:
697 if (!nv30_fragprog_parse_decl_attrib(fpc, fdec))
698 goto out_err;
699 break;
700 case TGSI_FILE_OUTPUT:
701 if (!nv30_fragprog_parse_decl_output(fpc, fdec))
702 goto out_err;
703 break;
704 default:
705 break;
706 }
707 }
708 break;
709 case TGSI_TOKEN_TYPE_IMMEDIATE:
710 {
711 struct tgsi_full_immediate *imm;
712 float vals[4];
713 int i;
714
715 imm = &parse.FullToken.FullImmediate;
716 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
717 assert(fpc->nr_imm < MAX_IMM);
718
719 for (i = 0; i < 4; i++)
720 vals[i] = imm->u.ImmediateFloat32[i].Float;
721 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
722 }
723 break;
724 case TGSI_TOKEN_TYPE_INSTRUCTION:
725 {
726 const struct tgsi_full_instruction *finst;
727
728 finst = &parse.FullToken.FullInstruction;
729 if (!nv30_fragprog_parse_instruction(fpc, finst))
730 goto out_err;
731 }
732 break;
733 default:
734 break;
735 }
736 }
737
738 fp->fp_control |= (fpc->num_regs-1)/2;
739 fp->fp_reg_control = (1<<16)|0x4;
740
741 /* Terminate final instruction */
742 fp->insn[fpc->inst_offset] |= 0x00000001;
743
744 /* Append NOP + END instruction, may or may not be necessary. */
745 fpc->inst_offset = fp->insn_len;
746 grow_insns(fpc, 4);
747 fp->insn[fpc->inst_offset + 0] = 0x00000001;
748 fp->insn[fpc->inst_offset + 1] = 0x00000000;
749 fp->insn[fpc->inst_offset + 2] = 0x00000000;
750 fp->insn[fpc->inst_offset + 3] = 0x00000000;
751
752 fp->translated = TRUE;
753 fp->on_hw = FALSE;
754 out_err:
755 tgsi_parse_free(&parse);
756 FREE(fpc);
757 }
758
759 void
760 nv30_fragprog_bind(struct nv30_context *nv30, struct nv30_fragment_program *fp)
761 {
762 struct pipe_winsys *ws = nv30->pipe.winsys;
763 int i;
764
765 if (!fp->translated) {
766 nv30_fragprog_translate(nv30, fp);
767 if (!fp->translated)
768 assert(0);
769 }
770
771 if (fp->nr_consts) {
772 float *map = ws->buffer_map(ws, nv30->fragprog.constant_buf,
773 PIPE_BUFFER_USAGE_CPU_READ);
774 for (i = 0; i < fp->nr_consts; i++) {
775 struct nv30_fragment_program_data *fpd = &fp->consts[i];
776 uint32_t *p = &fp->insn[fpd->offset];
777 uint32_t *cb = (uint32_t *)&map[fpd->index * 4];
778
779 if (!memcmp(p, cb, 4 * sizeof(float)))
780 continue;
781 memcpy(p, cb, 4 * sizeof(float));
782 fp->on_hw = 0;
783 }
784 ws->buffer_unmap(ws, nv30->fragprog.constant_buf);
785 }
786
787 if (!fp->on_hw) {
788 const uint32_t le = 1;
789 uint32_t *map;
790
791 if (!fp->buffer)
792 fp->buffer = ws->buffer_create(ws, 0x100, 0,
793 fp->insn_len * 4);
794 map = ws->buffer_map(ws, fp->buffer,
795 PIPE_BUFFER_USAGE_CPU_WRITE);
796
797 #if 0
798 for (i = 0; i < fp->insn_len; i++) {
799 NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]);
800 }
801 #endif
802
803 if ((*(const uint8_t *)&le)) {
804 for (i = 0; i < fp->insn_len; i++) {
805 map[i] = fp->insn[i];
806 }
807 } else {
808 /* Weird swapping for big-endian chips */
809 for (i = 0; i < fp->insn_len; i++) {
810 map[i] = ((fp->insn[i] & 0xffff) << 16) |
811 ((fp->insn[i] >> 16) & 0xffff);
812 }
813 }
814
815 ws->buffer_unmap(ws, fp->buffer);
816 fp->on_hw = TRUE;
817 }
818
819 BEGIN_RING(rankine, NV34TCL_FP_CONTROL, 1);
820 OUT_RING (fp->fp_control);
821 BEGIN_RING(rankine, NV34TCL_FP_REG_CONTROL, 1);
822 OUT_RING (fp->fp_reg_control);
823
824 nv30->fragprog.active = fp;
825 }
826
827 void
828 nv30_fragprog_destroy(struct nv30_context *nv30,
829 struct nv30_fragment_program *fp)
830 {
831 if (fp->insn_len)
832 FREE(fp->insn);
833 }
834