src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format_s3tc.h"
  27
  28 #include "nouveau/nv_object.xml.h"
  29 #include "nouveau/nv_m2mf.xml.h"
  30 #include "nv30-40_3d.xml.h"
  31 #include "nv01_2d.xml.h"
  32
  33 #include "nouveau/nouveau_fence.h"
  34 #include "nv30_screen.h"
  35 #include "nv30_context.h"
  36 #include "nv30_resource.h"
  37 #include "nv30_format.h"
  38
  39 #define RANKINE_0397_CHIPSET 0x00000003
  40 #define RANKINE_0497_CHIPSET 0x000001e0
  41 #define RANKINE_0697_CHIPSET 0x00000010
  42 #define CURIE_4097_CHIPSET   0x00000baf
  43 #define CURIE_4497_CHIPSET   0x00005450
  44 #define CURIE_4497_CHIPSET6X 0x00000088
  45
  46 static int
  47 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  48 {
  49    struct nv30_screen *screen = nv30_screen(pscreen);
  50    struct nouveau_object *eng3d = screen->eng3d;
  51
  52    switch (param) {
  53    /* non-boolean capabilities */
  54    case PIPE_CAP_MAX_RENDER_TARGETS:
  55       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  56    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57       return 13;
  58    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59       return 10;
  60    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  63       return 16;
  64    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  65       return 120;
  66    /* supported capabilities */
  67    case PIPE_CAP_TWO_SIDED_STENCIL:
  68    case PIPE_CAP_ANISOTROPIC_FILTER:
  69    case PIPE_CAP_POINT_SPRITE:
  70    case PIPE_CAP_SCALED_RESOLVE:
  71    case PIPE_CAP_OCCLUSION_QUERY:
  72    case PIPE_CAP_TIMER_QUERY:
  73    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  74    case PIPE_CAP_TEXTURE_SWIZZLE:
  75    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  76    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  77    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81    case PIPE_CAP_USER_VERTEX_BUFFERS:
  82       return 1;
  83    /* nv4x capabilities */
  84    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  85    case PIPE_CAP_NPOT_TEXTURES:
  86    case PIPE_CAP_CONDITIONAL_RENDER:
  87    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  88    case PIPE_CAP_PRIMITIVE_RESTART:
  89       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  90    /* unsupported */
  91    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  92    case PIPE_CAP_SM3:
  93    case PIPE_CAP_INDEP_BLEND_ENABLE:
  94    case PIPE_CAP_INDEP_BLEND_FUNC:
  95    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  96    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  97    case PIPE_CAP_TGSI_INSTANCEID:
  98    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
  99    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 100    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 101    case PIPE_CAP_MIN_TEXEL_OFFSET:
 102    case PIPE_CAP_MAX_TEXEL_OFFSET:
 103    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 104    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 105    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 106    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 107    case PIPE_CAP_TEXTURE_BARRIER:
 108    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 110    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 111    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 112    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 113       return 0;
 114    default:
 115       debug_printf("unknown param %d\n", param);
 116       return 0;
 117    }
 118 }
 119
 120 static float
 121 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 122 {
 123    struct nv30_screen *screen = nv30_screen(pscreen);
 124    struct nouveau_object *eng3d = screen->eng3d;
 125
 126    switch (param) {
 127    case PIPE_CAPF_MAX_LINE_WIDTH:
 128    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 129       return 10.0;
 130    case PIPE_CAPF_MAX_POINT_WIDTH:
 131    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 132       return 64.0;
 133    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 134       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 135    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 136       return 15.0;
 137    default:
 138       debug_printf("unknown paramf %d\n", param);
 139       return 0;
 140    }
 141 }
 142
 143 static int
 144 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 145                              enum pipe_shader_cap param)
 146 {
 147    struct nv30_screen *screen = nv30_screen(pscreen);
 148    struct nouveau_object *eng3d = screen->eng3d;
 149
 150    switch (shader) {
 151    case PIPE_SHADER_VERTEX:
 152       switch (param) {
 153       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 154       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 155          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 156       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 157       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 158          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 159       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 160          return 0;
 161       case PIPE_SHADER_CAP_MAX_INPUTS:
 162          return 16;
 163       case PIPE_SHADER_CAP_MAX_CONSTS:
 164          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 165       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 166          return 1;
 167       case PIPE_SHADER_CAP_MAX_TEMPS:
 168          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 169       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 170          return 0;
 171       case PIPE_SHADER_CAP_MAX_ADDRS:
 172          return 2;
 173       case PIPE_SHADER_CAP_MAX_PREDS:
 174       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 175       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 176       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 177       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 178       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 179       case PIPE_SHADER_CAP_SUBROUTINES:
 180       case PIPE_SHADER_CAP_INTEGERS:
 181          return 0;
 182       default:
 183          debug_printf("unknown vertex shader param %d\n", param);
 184          return 0;
 185       }
 186       break;
 187    case PIPE_SHADER_FRAGMENT:
 188       switch (param) {
 189       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 190       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 191       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 192       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 193          return 4096;
 194       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 195          return 0;
 196       case PIPE_SHADER_CAP_MAX_INPUTS:
 197          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 198       case PIPE_SHADER_CAP_MAX_CONSTS:
 199          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 200       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 201          return 1;
 202       case PIPE_SHADER_CAP_MAX_TEMPS:
 203          return 32;
 204       case PIPE_SHADER_CAP_MAX_ADDRS:
 205          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 206       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 207          return 16;
 208       case PIPE_SHADER_CAP_MAX_PREDS:
 209       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 210       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 211       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 212       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 213       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 214       case PIPE_SHADER_CAP_SUBROUTINES:
 215          return 0;
 216       default:
 217          debug_printf("unknown fragment shader param %d\n", param);
 218          return 0;
 219       }
 220       break;
 221    default:
 222       return 0;
 223    }
 224 }
 225
 226 static boolean
 227 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 228                                 enum pipe_format format,
 229                                 enum pipe_texture_target target,
 230                                 unsigned sample_count,
 231                                 unsigned bindings)
 232 {
 233    if (!(0x00000017 & (1 << sample_count)))
 234       return FALSE;
 235
 236    if (!util_format_s3tc_enabled) {
 237       switch (format) {
 238       case PIPE_FORMAT_DXT1_RGB:
 239       case PIPE_FORMAT_DXT1_RGBA:
 240       case PIPE_FORMAT_DXT3_RGBA:
 241       case PIPE_FORMAT_DXT5_RGBA:
 242          return FALSE;
 243       default:
 244          break;
 245       }
 246    }
 247
 248    /* transfers & shared are always supported */
 249    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 250                  PIPE_BIND_TRANSFER_WRITE |
 251                  PIPE_BIND_SHARED);
 252
 253    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 254 }
 255
 256 static void
 257 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 258 {
 259    struct nv30_screen *screen = nv30_screen(pscreen);
 260    struct nouveau_pushbuf *push = screen->base.pushbuf;
 261
 262    *sequence = ++screen->base.fence.sequence;
 263
 264    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 265    PUSH_DATA (push, 0);
 266    PUSH_DATA (push, *sequence);
 267 }
 268
 269 static uint32_t
 270 nv30_screen_fence_update(struct pipe_screen *pscreen)
 271 {
 272    struct nv30_screen *screen = nv30_screen(pscreen);
 273    struct nv04_notify *fence = screen->fence->data;
 274    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 275 }
 276
 277 static void
 278 nv30_screen_destroy(struct pipe_screen *pscreen)
 279 {
 280    struct nv30_screen *screen = nv30_screen(pscreen);
 281
 282    if (screen->base.fence.current &&
 283        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 284       nouveau_fence_wait(screen->base.fence.current);
 285       nouveau_fence_ref (NULL, &screen->base.fence.current);
 286    }
 287
 288    nouveau_object_del(&screen->query);
 289    nouveau_object_del(&screen->fence);
 290    nouveau_object_del(&screen->ntfy);
 291
 292    nouveau_object_del(&screen->sifm);
 293    nouveau_object_del(&screen->swzsurf);
 294    nouveau_object_del(&screen->surf2d);
 295    nouveau_object_del(&screen->m2mf);
 296    nouveau_object_del(&screen->eng3d);
 297    nouveau_object_del(&screen->null);
 298
 299    nouveau_screen_fini(&screen->base);
 300    FREE(screen);
 301 }
 302
 303 #define FAIL_SCREEN_INIT(str, err)                    \
 304    do {                                               \
 305       NOUVEAU_ERR(str, err);                          \
 306       nv30_screen_destroy(pscreen);                   \
 307       return NULL;                                    \
 308    } while(0)
 309
 310 struct pipe_screen *
 311 nv30_screen_create(struct nouveau_device *dev)
 312 {
 313    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 314    struct pipe_screen *pscreen;
 315    struct nouveau_pushbuf *push;
 316    struct nv04_fifo *fifo;
 317    unsigned oclass = 0;
 318    int ret, i;
 319
 320    if (!screen)
 321       return NULL;
 322
 323    switch (dev->chipset & 0xf0) {
 324    case 0x30:
 325       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 326          oclass = NV30_3D_CLASS;
 327       else
 328       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 329          oclass = NV34_3D_CLASS;
 330       else
 331       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 332          oclass = NV35_3D_CLASS;
 333       break;
 334    case 0x40:
 335       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 336          oclass = NV40_3D_CLASS;
 337       else
 338       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 339          oclass = NV44_3D_CLASS;
 340       break;
 341    case 0x60:
 342       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 343          oclass = NV44_3D_CLASS;
 344       break;
 345    default:
 346       break;
 347    }
 348
 349    if (!oclass) {
 350       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 351       return NULL;
 352    }
 353
 354    pscreen = &screen->base.base;
 355    pscreen->destroy = nv30_screen_destroy;
 356    pscreen->get_param = nv30_screen_get_param;
 357    pscreen->get_paramf = nv30_screen_get_paramf;
 358    pscreen->get_shader_param = nv30_screen_get_shader_param;
 359    pscreen->context_create = nv30_context_create;
 360    pscreen->is_format_supported = nv30_screen_is_format_supported;
 361    nv30_resource_screen_init(pscreen);
 362
 363    screen->base.fence.emit = nv30_screen_fence_emit;
 364    screen->base.fence.update = nv30_screen_fence_update;
 365    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 366    if (oclass != NV40_3D_CLASS)
 367       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 368
 369    ret = nouveau_screen_init(&screen->base, dev);
 370    if (ret)
 371       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 372
 373    fifo = screen->base.channel->data;
 374    push = screen->base.pushbuf;
 375    push->rsvd_kick = 16;
 376
 377    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 378                             NULL, 0, &screen->null);
 379    if (ret)
 380       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 381
 382    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 383     * this means that the address pointed at by the DMA object must
 384     * be 4KiB aligned, which means this object needs to be the first
 385     * one allocated on the channel.
 386     */
 387    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 388                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 389                             .length = 32 }, sizeof(struct nv04_notify),
 390                             &screen->fence);
 391    if (ret)
 392       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 393
 394    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 395    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 396                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 397                             .length = 32 }, sizeof(struct nv04_notify),
 398                             &screen->ntfy);
 399    if (ret)
 400       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 401
 402    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 403     * the remainder of the "notifier block" assigned by the kernel for
 404     * use as query objects
 405     */
 406    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 407                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 408                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 409                             &screen->query);
 410    if (ret)
 411       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 412
 413    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 414    if (ret)
 415       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 416
 417    LIST_INITHEAD(&screen->queries);
 418
 419    /* Vertex program resources (code/data), currently 6 of the constant
 420     * slots are reserved to implement user clipping planes
 421     */
 422    if (oclass < NV40_3D_CLASS) {
 423       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 424       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 425    } else {
 426       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 427       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 428    }
 429
 430    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 431    if (ret == 0)
 432       nouveau_bo_map(screen->notify, 0, screen->base.client);
 433    if (ret)
 434       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 435
 436    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 437                             NULL, 0, &screen->eng3d);
 438    if (ret)
 439       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 440
 441    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 442    PUSH_DATA (push, screen->eng3d->handle);
 443    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 444    PUSH_DATA (push, screen->ntfy->handle);
 445    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 446    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 447    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 448    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 449    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 450    PUSH_DATA (push, fifo->vram);     /* ZETA */
 451    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 452    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 453    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 454    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 455    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 456    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 457    BEGIN_NV04(push, NV30_3D(VIEWPORT_CLIP_MODE), 1);
 458    PUSH_DATA (push, 0);
 459    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 460       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 461       PUSH_DATA (push, 0x00100000);
 462       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 463       PUSH_DATA (push, 3);
 464
 465       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 466       PUSH_DATA (push, 0);
 467       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 468       PUSH_DATA (push, fui(0.0));
 469       PUSH_DATA (push, fui(0.0));
 470       PUSH_DATA (push, fui(1.0));
 471       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 472       for (i = 0; i < 16; i++)
 473          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 474
 475       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 476       PUSH_DATA (push, 0);
 477    } else {
 478       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 479       PUSH_DATA (push, fifo->vram);
 480       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 481
 482       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 483       PUSH_DATA (push, 0x00000004);
 484
 485       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 486       PUSH_DATA (push, 0x00000010);
 487       PUSH_DATA (push, 0x01000100);
 488       PUSH_DATA (push, 0xff800006);
 489
 490       /* vtxprog output routing */
 491       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 492       PUSH_DATA (push, 0x06144321);
 493       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 494       PUSH_DATA (push, 0xedcba987);
 495       PUSH_DATA (push, 0x0000006f);
 496       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 497       PUSH_DATA (push, 0x00171615);
 498       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 499       PUSH_DATA (push, 0x001b1a19);
 500
 501       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 502       PUSH_DATA (push, 0x0020ffff);
 503       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 504       PUSH_DATA (push, 0x01d300d4);
 505
 506       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 507       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 508    }
 509
 510    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 511                             NULL, 0, &screen->m2mf);
 512    if (ret)
 513       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 514
 515    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 516    PUSH_DATA (push, screen->m2mf->handle);
 517    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 518    PUSH_DATA (push, screen->ntfy->handle);
 519
 520    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 521                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 522    if (ret)
 523       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 524
 525    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 526    PUSH_DATA (push, screen->surf2d->handle);
 527    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 528    PUSH_DATA (push, screen->ntfy->handle);
 529
 530    if (dev->chipset < 0x40)
 531       oclass = NV30_SURFACE_SWZ_CLASS;
 532    else
 533       oclass = NV40_SURFACE_SWZ_CLASS;
 534
 535    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 536                             NULL, 0, &screen->swzsurf);
 537    if (ret)
 538       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 539
 540    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 541    PUSH_DATA (push, screen->swzsurf->handle);
 542    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 543    PUSH_DATA (push, screen->ntfy->handle);
 544
 545    if (dev->chipset < 0x40)
 546       oclass = NV30_SIFM_CLASS;
 547    else
 548       oclass = NV40_SIFM_CLASS;
 549
 550    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 551                             NULL, 0, &screen->sifm);
 552    if (ret)
 553       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 554
 555    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 556    PUSH_DATA (push, screen->sifm->handle);
 557    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 558    PUSH_DATA (push, screen->ntfy->handle);
 559    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 560    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 561
 562    nouveau_pushbuf_kick(push, push->channel);
 563
 564    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 565    return pscreen;
 566 }