src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nouveau/nv_m2mf.xml.h"
  31 #include "nv30-40_3d.xml.h"
  32 #include "nv01_2d.xml.h"
  33
  34 #include "nouveau/nouveau_fence.h"
  35 #include "nv30_screen.h"
  36 #include "nv30_context.h"
  37 #include "nv30_resource.h"
  38 #include "nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64       return 16;
  65    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  66       return 120;
  67    /* supported capabilities */
  68    case PIPE_CAP_TWO_SIDED_STENCIL:
  69    case PIPE_CAP_ANISOTROPIC_FILTER:
  70    case PIPE_CAP_POINT_SPRITE:
  71    case PIPE_CAP_SCALED_RESOLVE:
  72    case PIPE_CAP_OCCLUSION_QUERY:
  73    case PIPE_CAP_TIMER_QUERY:
  74    case PIPE_CAP_QUERY_TIMESTAMP:
  75    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  76    case PIPE_CAP_TEXTURE_SWIZZLE:
  77    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  78    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  79    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  80    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  81    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  82    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  83    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  84    case PIPE_CAP_USER_INDEX_BUFFERS:
  85       return 1;
  86    case PIPE_CAP_USER_VERTEX_BUFFERS:
  87       return 0;
  88    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  89       return 16;
  90    /* nv4x capabilities */
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_CONDITIONAL_RENDER:
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_PRIMITIVE_RESTART:
  96       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  97    /* unsupported */
  98    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  99    case PIPE_CAP_SM3:
 100    case PIPE_CAP_INDEP_BLEND_ENABLE:
 101    case PIPE_CAP_INDEP_BLEND_FUNC:
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 104    case PIPE_CAP_TGSI_INSTANCEID:
 105    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 106    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 107    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 108    case PIPE_CAP_MIN_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 112    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 113    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 114    case PIPE_CAP_TEXTURE_BARRIER:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 118    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 119    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 120    case PIPE_CAP_START_INSTANCE:
 121    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 122       return 0;
 123    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 124    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 125    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 126       return 1;
 127    default:
 128       debug_printf("unknown param %d\n", param);
 129       return 0;
 130    }
 131 }
 132
 133 static float
 134 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 135 {
 136    struct nv30_screen *screen = nv30_screen(pscreen);
 137    struct nouveau_object *eng3d = screen->eng3d;
 138
 139    switch (param) {
 140    case PIPE_CAPF_MAX_LINE_WIDTH:
 141    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 142       return 10.0;
 143    case PIPE_CAPF_MAX_POINT_WIDTH:
 144    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 145       return 64.0;
 146    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 147       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 148    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 149       return 15.0;
 150    default:
 151       debug_printf("unknown paramf %d\n", param);
 152       return 0;
 153    }
 154 }
 155
 156 static int
 157 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 158                              enum pipe_shader_cap param)
 159 {
 160    struct nv30_screen *screen = nv30_screen(pscreen);
 161    struct nouveau_object *eng3d = screen->eng3d;
 162
 163    switch (shader) {
 164    case PIPE_SHADER_VERTEX:
 165       switch (param) {
 166       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 167       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 168          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 169       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 170       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 171          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 172       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 173          return 0;
 174       case PIPE_SHADER_CAP_MAX_INPUTS:
 175          return 16;
 176       case PIPE_SHADER_CAP_MAX_CONSTS:
 177          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 178       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 179          return 1;
 180       case PIPE_SHADER_CAP_MAX_TEMPS:
 181          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 182       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 183          return 0;
 184       case PIPE_SHADER_CAP_MAX_ADDRS:
 185          return 2;
 186       case PIPE_SHADER_CAP_MAX_PREDS:
 187       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 188       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 189       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 190       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 191       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 192       case PIPE_SHADER_CAP_SUBROUTINES:
 193       case PIPE_SHADER_CAP_INTEGERS:
 194          return 0;
 195       default:
 196          debug_printf("unknown vertex shader param %d\n", param);
 197          return 0;
 198       }
 199       break;
 200    case PIPE_SHADER_FRAGMENT:
 201       switch (param) {
 202       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 203       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 204       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 205       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 206          return 4096;
 207       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 208          return 0;
 209       case PIPE_SHADER_CAP_MAX_INPUTS:
 210          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 211       case PIPE_SHADER_CAP_MAX_CONSTS:
 212          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 213       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 214          return 1;
 215       case PIPE_SHADER_CAP_MAX_TEMPS:
 216          return 32;
 217       case PIPE_SHADER_CAP_MAX_ADDRS:
 218          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 219       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 220          return 16;
 221       case PIPE_SHADER_CAP_MAX_PREDS:
 222       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 223       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 224       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 225       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 226       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 227       case PIPE_SHADER_CAP_SUBROUTINES:
 228          return 0;
 229       default:
 230          debug_printf("unknown fragment shader param %d\n", param);
 231          return 0;
 232       }
 233       break;
 234    default:
 235       return 0;
 236    }
 237 }
 238
 239 static boolean
 240 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 241                                 enum pipe_format format,
 242                                 enum pipe_texture_target target,
 243                                 unsigned sample_count,
 244                                 unsigned bindings)
 245 {
 246    if (!(0x00000017 & (1 << sample_count)))
 247       return FALSE;
 248
 249    if (!util_format_is_supported(format, bindings)) {
 250       return FALSE;
 251    }
 252
 253    /* transfers & shared are always supported */
 254    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 255                  PIPE_BIND_TRANSFER_WRITE |
 256                  PIPE_BIND_SHARED);
 257
 258    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 259 }
 260
 261 static void
 262 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 263 {
 264    struct nv30_screen *screen = nv30_screen(pscreen);
 265    struct nouveau_pushbuf *push = screen->base.pushbuf;
 266
 267    *sequence = ++screen->base.fence.sequence;
 268
 269    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 270    PUSH_DATA (push, 0);
 271    PUSH_DATA (push, *sequence);
 272 }
 273
 274 static uint32_t
 275 nv30_screen_fence_update(struct pipe_screen *pscreen)
 276 {
 277    struct nv30_screen *screen = nv30_screen(pscreen);
 278    struct nv04_notify *fence = screen->fence->data;
 279    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 280 }
 281
 282 static void
 283 nv30_screen_destroy(struct pipe_screen *pscreen)
 284 {
 285    struct nv30_screen *screen = nv30_screen(pscreen);
 286
 287    if (screen->base.fence.current &&
 288        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 289       nouveau_fence_wait(screen->base.fence.current);
 290       nouveau_fence_ref (NULL, &screen->base.fence.current);
 291    }
 292
 293    nouveau_object_del(&screen->query);
 294    nouveau_object_del(&screen->fence);
 295    nouveau_object_del(&screen->ntfy);
 296
 297    nouveau_object_del(&screen->sifm);
 298    nouveau_object_del(&screen->swzsurf);
 299    nouveau_object_del(&screen->surf2d);
 300    nouveau_object_del(&screen->m2mf);
 301    nouveau_object_del(&screen->eng3d);
 302    nouveau_object_del(&screen->null);
 303
 304    nouveau_screen_fini(&screen->base);
 305    FREE(screen);
 306 }
 307
 308 #define FAIL_SCREEN_INIT(str, err)                    \
 309    do {                                               \
 310       NOUVEAU_ERR(str, err);                          \
 311       nv30_screen_destroy(pscreen);                   \
 312       return NULL;                                    \
 313    } while(0)
 314
 315 struct pipe_screen *
 316 nv30_screen_create(struct nouveau_device *dev)
 317 {
 318    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 319    struct pipe_screen *pscreen;
 320    struct nouveau_pushbuf *push;
 321    struct nv04_fifo *fifo;
 322    unsigned oclass = 0;
 323    int ret, i;
 324
 325    if (!screen)
 326       return NULL;
 327
 328    switch (dev->chipset & 0xf0) {
 329    case 0x30:
 330       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 331          oclass = NV30_3D_CLASS;
 332       else
 333       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 334          oclass = NV34_3D_CLASS;
 335       else
 336       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 337          oclass = NV35_3D_CLASS;
 338       break;
 339    case 0x40:
 340       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 341          oclass = NV40_3D_CLASS;
 342       else
 343       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 344          oclass = NV44_3D_CLASS;
 345       break;
 346    case 0x60:
 347       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 348          oclass = NV44_3D_CLASS;
 349       break;
 350    default:
 351       break;
 352    }
 353
 354    if (!oclass) {
 355       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 356       return NULL;
 357    }
 358
 359    pscreen = &screen->base.base;
 360    pscreen->destroy = nv30_screen_destroy;
 361    pscreen->get_param = nv30_screen_get_param;
 362    pscreen->get_paramf = nv30_screen_get_paramf;
 363    pscreen->get_shader_param = nv30_screen_get_shader_param;
 364    pscreen->context_create = nv30_context_create;
 365    pscreen->is_format_supported = nv30_screen_is_format_supported;
 366    nv30_resource_screen_init(pscreen);
 367
 368    screen->base.fence.emit = nv30_screen_fence_emit;
 369    screen->base.fence.update = nv30_screen_fence_update;
 370
 371    ret = nouveau_screen_init(&screen->base, dev);
 372    if (ret)
 373       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 374
 375    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 376    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 377    if (oclass == NV40_3D_CLASS) {
 378       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 379       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 380    }
 381
 382    fifo = screen->base.channel->data;
 383    push = screen->base.pushbuf;
 384    push->rsvd_kick = 16;
 385
 386    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 387                             NULL, 0, &screen->null);
 388    if (ret)
 389       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 390
 391    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 392     * this means that the address pointed at by the DMA object must
 393     * be 4KiB aligned, which means this object needs to be the first
 394     * one allocated on the channel.
 395     */
 396    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 397                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 398                             .length = 32 }, sizeof(struct nv04_notify),
 399                             &screen->fence);
 400    if (ret)
 401       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 402
 403    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 404    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 405                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 406                             .length = 32 }, sizeof(struct nv04_notify),
 407                             &screen->ntfy);
 408    if (ret)
 409       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 410
 411    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 412     * the remainder of the "notifier block" assigned by the kernel for
 413     * use as query objects
 414     */
 415    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 416                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 417                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 418                             &screen->query);
 419    if (ret)
 420       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 421
 422    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 423    if (ret)
 424       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 425
 426    LIST_INITHEAD(&screen->queries);
 427
 428    /* Vertex program resources (code/data), currently 6 of the constant
 429     * slots are reserved to implement user clipping planes
 430     */
 431    if (oclass < NV40_3D_CLASS) {
 432       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 433       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 434    } else {
 435       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 436       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 437    }
 438
 439    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 440    if (ret == 0)
 441       nouveau_bo_map(screen->notify, 0, screen->base.client);
 442    if (ret)
 443       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 444
 445    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 446                             NULL, 0, &screen->eng3d);
 447    if (ret)
 448       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 449
 450    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 451    PUSH_DATA (push, screen->eng3d->handle);
 452    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 453    PUSH_DATA (push, screen->ntfy->handle);
 454    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 455    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 456    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 457    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 458    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 459    PUSH_DATA (push, fifo->vram);     /* ZETA */
 460    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 461    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 462    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 463    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 464    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 465    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 466    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 467       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 468       PUSH_DATA (push, 0x00100000);
 469       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 470       PUSH_DATA (push, 3);
 471
 472       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 473       PUSH_DATA (push, 0);
 474       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 475       PUSH_DATA (push, fui(0.0));
 476       PUSH_DATA (push, fui(0.0));
 477       PUSH_DATA (push, fui(1.0));
 478       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 479       for (i = 0; i < 16; i++)
 480          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 481
 482       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 483       PUSH_DATA (push, 0);
 484    } else {
 485       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 486       PUSH_DATA (push, fifo->vram);
 487       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 488
 489       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 490       PUSH_DATA (push, 0x00000004);
 491
 492       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 493       PUSH_DATA (push, 0x00000010);
 494       PUSH_DATA (push, 0x01000100);
 495       PUSH_DATA (push, 0xff800006);
 496
 497       /* vtxprog output routing */
 498       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 499       PUSH_DATA (push, 0x06144321);
 500       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 501       PUSH_DATA (push, 0xedcba987);
 502       PUSH_DATA (push, 0x0000006f);
 503       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 504       PUSH_DATA (push, 0x00171615);
 505       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 506       PUSH_DATA (push, 0x001b1a19);
 507
 508       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 509       PUSH_DATA (push, 0x0020ffff);
 510       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 511       PUSH_DATA (push, 0x01d300d4);
 512
 513       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 514       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 515    }
 516
 517    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 518                             NULL, 0, &screen->m2mf);
 519    if (ret)
 520       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 521
 522    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 523    PUSH_DATA (push, screen->m2mf->handle);
 524    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 525    PUSH_DATA (push, screen->ntfy->handle);
 526
 527    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 528                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 529    if (ret)
 530       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 531
 532    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 533    PUSH_DATA (push, screen->surf2d->handle);
 534    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 535    PUSH_DATA (push, screen->ntfy->handle);
 536
 537    if (dev->chipset < 0x40)
 538       oclass = NV30_SURFACE_SWZ_CLASS;
 539    else
 540       oclass = NV40_SURFACE_SWZ_CLASS;
 541
 542    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 543                             NULL, 0, &screen->swzsurf);
 544    if (ret)
 545       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 546
 547    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 548    PUSH_DATA (push, screen->swzsurf->handle);
 549    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 550    PUSH_DATA (push, screen->ntfy->handle);
 551
 552    if (dev->chipset < 0x40)
 553       oclass = NV30_SIFM_CLASS;
 554    else
 555       oclass = NV40_SIFM_CLASS;
 556
 557    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 558                             NULL, 0, &screen->sifm);
 559    if (ret)
 560       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 561
 562    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 563    PUSH_DATA (push, screen->sifm->handle);
 564    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 565    PUSH_DATA (push, screen->ntfy->handle);
 566    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 567    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 568
 569    nouveau_pushbuf_kick(push, push->channel);
 570
 571    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 572    return pscreen;
 573 }