src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format_s3tc.h"
  27
  28 #include "nouveau/nv_object.xml.h"
  29 #include "nouveau/nv_m2mf.xml.h"
  30 #include "nv30-40_3d.xml.h"
  31 #include "nv01_2d.xml.h"
  32
  33 #include "nouveau/nouveau_fence.h"
  34 #include "nv30_screen.h"
  35 #include "nv30_context.h"
  36 #include "nv30_resource.h"
  37 #include "nv30_format.h"
  38
  39 #define RANKINE_0397_CHIPSET 0x00000003
  40 #define RANKINE_0497_CHIPSET 0x000001e0
  41 #define RANKINE_0697_CHIPSET 0x00000010
  42 #define CURIE_4097_CHIPSET   0x00000baf
  43 #define CURIE_4497_CHIPSET   0x00005450
  44 #define CURIE_4497_CHIPSET6X 0x00000088
  45
  46 static int
  47 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  48 {
  49    struct nv30_screen *screen = nv30_screen(pscreen);
  50    struct nouveau_object *eng3d = screen->eng3d;
  51
  52    switch (param) {
  53    /* non-boolean capabilities */
  54    case PIPE_CAP_MAX_RENDER_TARGETS:
  55       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  56    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57       return 13;
  58    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59       return 10;
  60    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  63       return 16;
  64    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  65       return 120;
  66    /* supported capabilities */
  67    case PIPE_CAP_TWO_SIDED_STENCIL:
  68    case PIPE_CAP_ANISOTROPIC_FILTER:
  69    case PIPE_CAP_POINT_SPRITE:
  70    case PIPE_CAP_SCALED_RESOLVE:
  71    case PIPE_CAP_OCCLUSION_QUERY:
  72    case PIPE_CAP_TIMER_QUERY:
  73    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  74    case PIPE_CAP_TEXTURE_SWIZZLE:
  75    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  76    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  77    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81    case PIPE_CAP_USER_VERTEX_BUFFERS:
  82    case PIPE_CAP_USER_INDEX_BUFFERS:
  83    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  84       return 1;
  85    /* nv4x capabilities */
  86    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  87    case PIPE_CAP_NPOT_TEXTURES:
  88    case PIPE_CAP_CONDITIONAL_RENDER:
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  90    case PIPE_CAP_PRIMITIVE_RESTART:
  91       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  92    /* unsupported */
  93    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  94    case PIPE_CAP_SM3:
  95    case PIPE_CAP_INDEP_BLEND_ENABLE:
  96    case PIPE_CAP_INDEP_BLEND_FUNC:
  97    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  98    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  99    case PIPE_CAP_TGSI_INSTANCEID:
 100    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 101    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 102    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104    case PIPE_CAP_MAX_TEXEL_OFFSET:
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 106    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 107    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 108    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 109    case PIPE_CAP_TEXTURE_BARRIER:
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 111    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 112    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 113    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115       return 0;
 116    default:
 117       debug_printf("unknown param %d\n", param);
 118       return 0;
 119    }
 120 }
 121
 122 static float
 123 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 124 {
 125    struct nv30_screen *screen = nv30_screen(pscreen);
 126    struct nouveau_object *eng3d = screen->eng3d;
 127
 128    switch (param) {
 129    case PIPE_CAPF_MAX_LINE_WIDTH:
 130    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 131       return 10.0;
 132    case PIPE_CAPF_MAX_POINT_WIDTH:
 133    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 134       return 64.0;
 135    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 136       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 137    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 138       return 15.0;
 139    default:
 140       debug_printf("unknown paramf %d\n", param);
 141       return 0;
 142    }
 143 }
 144
 145 static int
 146 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 147                              enum pipe_shader_cap param)
 148 {
 149    struct nv30_screen *screen = nv30_screen(pscreen);
 150    struct nouveau_object *eng3d = screen->eng3d;
 151
 152    switch (shader) {
 153    case PIPE_SHADER_VERTEX:
 154       switch (param) {
 155       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 156       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 157          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 158       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 159       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 160          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 161       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 162          return 0;
 163       case PIPE_SHADER_CAP_MAX_INPUTS:
 164          return 16;
 165       case PIPE_SHADER_CAP_MAX_CONSTS:
 166          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 167       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 168          return 1;
 169       case PIPE_SHADER_CAP_MAX_TEMPS:
 170          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 171       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 172          return 0;
 173       case PIPE_SHADER_CAP_MAX_ADDRS:
 174          return 2;
 175       case PIPE_SHADER_CAP_MAX_PREDS:
 176       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 177       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 178       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 179       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 180       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 181       case PIPE_SHADER_CAP_SUBROUTINES:
 182       case PIPE_SHADER_CAP_INTEGERS:
 183          return 0;
 184       default:
 185          debug_printf("unknown vertex shader param %d\n", param);
 186          return 0;
 187       }
 188       break;
 189    case PIPE_SHADER_FRAGMENT:
 190       switch (param) {
 191       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 192       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 193       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 194       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 195          return 4096;
 196       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 197          return 0;
 198       case PIPE_SHADER_CAP_MAX_INPUTS:
 199          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 200       case PIPE_SHADER_CAP_MAX_CONSTS:
 201          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 202       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 203          return 1;
 204       case PIPE_SHADER_CAP_MAX_TEMPS:
 205          return 32;
 206       case PIPE_SHADER_CAP_MAX_ADDRS:
 207          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 208       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 209          return 16;
 210       case PIPE_SHADER_CAP_MAX_PREDS:
 211       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 212       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 213       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 214       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 215       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 216       case PIPE_SHADER_CAP_SUBROUTINES:
 217          return 0;
 218       default:
 219          debug_printf("unknown fragment shader param %d\n", param);
 220          return 0;
 221       }
 222       break;
 223    default:
 224       return 0;
 225    }
 226 }
 227
 228 static boolean
 229 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 230                                 enum pipe_format format,
 231                                 enum pipe_texture_target target,
 232                                 unsigned sample_count,
 233                                 unsigned bindings)
 234 {
 235    if (!(0x00000017 & (1 << sample_count)))
 236       return FALSE;
 237
 238    if (!util_format_s3tc_enabled) {
 239       switch (format) {
 240       case PIPE_FORMAT_DXT1_RGB:
 241       case PIPE_FORMAT_DXT1_RGBA:
 242       case PIPE_FORMAT_DXT3_RGBA:
 243       case PIPE_FORMAT_DXT5_RGBA:
 244          return FALSE;
 245       default:
 246          break;
 247       }
 248    }
 249
 250    /* transfers & shared are always supported */
 251    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 252                  PIPE_BIND_TRANSFER_WRITE |
 253                  PIPE_BIND_SHARED);
 254
 255    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 256 }
 257
 258 static void
 259 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 260 {
 261    struct nv30_screen *screen = nv30_screen(pscreen);
 262    struct nouveau_pushbuf *push = screen->base.pushbuf;
 263
 264    *sequence = ++screen->base.fence.sequence;
 265
 266    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 267    PUSH_DATA (push, 0);
 268    PUSH_DATA (push, *sequence);
 269 }
 270
 271 static uint32_t
 272 nv30_screen_fence_update(struct pipe_screen *pscreen)
 273 {
 274    struct nv30_screen *screen = nv30_screen(pscreen);
 275    struct nv04_notify *fence = screen->fence->data;
 276    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 277 }
 278
 279 static void
 280 nv30_screen_destroy(struct pipe_screen *pscreen)
 281 {
 282    struct nv30_screen *screen = nv30_screen(pscreen);
 283
 284    if (screen->base.fence.current &&
 285        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 286       nouveau_fence_wait(screen->base.fence.current);
 287       nouveau_fence_ref (NULL, &screen->base.fence.current);
 288    }
 289
 290    nouveau_object_del(&screen->query);
 291    nouveau_object_del(&screen->fence);
 292    nouveau_object_del(&screen->ntfy);
 293
 294    nouveau_object_del(&screen->sifm);
 295    nouveau_object_del(&screen->swzsurf);
 296    nouveau_object_del(&screen->surf2d);
 297    nouveau_object_del(&screen->m2mf);
 298    nouveau_object_del(&screen->eng3d);
 299    nouveau_object_del(&screen->null);
 300
 301    nouveau_screen_fini(&screen->base);
 302    FREE(screen);
 303 }
 304
 305 #define FAIL_SCREEN_INIT(str, err)                    \
 306    do {                                               \
 307       NOUVEAU_ERR(str, err);                          \
 308       nv30_screen_destroy(pscreen);                   \
 309       return NULL;                                    \
 310    } while(0)
 311
 312 struct pipe_screen *
 313 nv30_screen_create(struct nouveau_device *dev)
 314 {
 315    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 316    struct pipe_screen *pscreen;
 317    struct nouveau_pushbuf *push;
 318    struct nv04_fifo *fifo;
 319    unsigned oclass = 0;
 320    int ret, i;
 321
 322    if (!screen)
 323       return NULL;
 324
 325    switch (dev->chipset & 0xf0) {
 326    case 0x30:
 327       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 328          oclass = NV30_3D_CLASS;
 329       else
 330       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 331          oclass = NV34_3D_CLASS;
 332       else
 333       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 334          oclass = NV35_3D_CLASS;
 335       break;
 336    case 0x40:
 337       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 338          oclass = NV40_3D_CLASS;
 339       else
 340       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 341          oclass = NV44_3D_CLASS;
 342       break;
 343    case 0x60:
 344       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 345          oclass = NV44_3D_CLASS;
 346       break;
 347    default:
 348       break;
 349    }
 350
 351    if (!oclass) {
 352       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 353       return NULL;
 354    }
 355
 356    pscreen = &screen->base.base;
 357    pscreen->destroy = nv30_screen_destroy;
 358    pscreen->get_param = nv30_screen_get_param;
 359    pscreen->get_paramf = nv30_screen_get_paramf;
 360    pscreen->get_shader_param = nv30_screen_get_shader_param;
 361    pscreen->context_create = nv30_context_create;
 362    pscreen->is_format_supported = nv30_screen_is_format_supported;
 363    nv30_resource_screen_init(pscreen);
 364
 365    screen->base.fence.emit = nv30_screen_fence_emit;
 366    screen->base.fence.update = nv30_screen_fence_update;
 367    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 368    if (oclass != NV40_3D_CLASS)
 369       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 370
 371    ret = nouveau_screen_init(&screen->base, dev);
 372    if (ret)
 373       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 374
 375    fifo = screen->base.channel->data;
 376    push = screen->base.pushbuf;
 377    push->rsvd_kick = 16;
 378
 379    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 380                             NULL, 0, &screen->null);
 381    if (ret)
 382       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 383
 384    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 385     * this means that the address pointed at by the DMA object must
 386     * be 4KiB aligned, which means this object needs to be the first
 387     * one allocated on the channel.
 388     */
 389    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 390                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 391                             .length = 32 }, sizeof(struct nv04_notify),
 392                             &screen->fence);
 393    if (ret)
 394       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 395
 396    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 397    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 398                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 399                             .length = 32 }, sizeof(struct nv04_notify),
 400                             &screen->ntfy);
 401    if (ret)
 402       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 403
 404    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 405     * the remainder of the "notifier block" assigned by the kernel for
 406     * use as query objects
 407     */
 408    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 409                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 410                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 411                             &screen->query);
 412    if (ret)
 413       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 414
 415    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 416    if (ret)
 417       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 418
 419    LIST_INITHEAD(&screen->queries);
 420
 421    /* Vertex program resources (code/data), currently 6 of the constant
 422     * slots are reserved to implement user clipping planes
 423     */
 424    if (oclass < NV40_3D_CLASS) {
 425       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 426       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 427    } else {
 428       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 429       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 430    }
 431
 432    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 433    if (ret == 0)
 434       nouveau_bo_map(screen->notify, 0, screen->base.client);
 435    if (ret)
 436       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 437
 438    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 439                             NULL, 0, &screen->eng3d);
 440    if (ret)
 441       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 442
 443    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 444    PUSH_DATA (push, screen->eng3d->handle);
 445    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 446    PUSH_DATA (push, screen->ntfy->handle);
 447    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 448    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 449    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 450    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 451    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 452    PUSH_DATA (push, fifo->vram);     /* ZETA */
 453    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 454    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 455    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 456    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 457    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 458    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 459    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 460       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 461       PUSH_DATA (push, 0x00100000);
 462       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 463       PUSH_DATA (push, 3);
 464
 465       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 466       PUSH_DATA (push, 0);
 467       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 468       PUSH_DATA (push, fui(0.0));
 469       PUSH_DATA (push, fui(0.0));
 470       PUSH_DATA (push, fui(1.0));
 471       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 472       for (i = 0; i < 16; i++)
 473          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 474
 475       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 476       PUSH_DATA (push, 0);
 477    } else {
 478       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 479       PUSH_DATA (push, fifo->vram);
 480       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 481
 482       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 483       PUSH_DATA (push, 0x00000004);
 484
 485       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 486       PUSH_DATA (push, 0x00000010);
 487       PUSH_DATA (push, 0x01000100);
 488       PUSH_DATA (push, 0xff800006);
 489
 490       /* vtxprog output routing */
 491       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 492       PUSH_DATA (push, 0x06144321);
 493       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 494       PUSH_DATA (push, 0xedcba987);
 495       PUSH_DATA (push, 0x0000006f);
 496       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 497       PUSH_DATA (push, 0x00171615);
 498       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 499       PUSH_DATA (push, 0x001b1a19);
 500
 501       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 502       PUSH_DATA (push, 0x0020ffff);
 503       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 504       PUSH_DATA (push, 0x01d300d4);
 505
 506       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 507       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 508    }
 509
 510    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 511                             NULL, 0, &screen->m2mf);
 512    if (ret)
 513       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 514
 515    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 516    PUSH_DATA (push, screen->m2mf->handle);
 517    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 518    PUSH_DATA (push, screen->ntfy->handle);
 519
 520    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 521                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 522    if (ret)
 523       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 524
 525    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 526    PUSH_DATA (push, screen->surf2d->handle);
 527    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 528    PUSH_DATA (push, screen->ntfy->handle);
 529
 530    if (dev->chipset < 0x40)
 531       oclass = NV30_SURFACE_SWZ_CLASS;
 532    else
 533       oclass = NV40_SURFACE_SWZ_CLASS;
 534
 535    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 536                             NULL, 0, &screen->swzsurf);
 537    if (ret)
 538       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 539
 540    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 541    PUSH_DATA (push, screen->swzsurf->handle);
 542    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 543    PUSH_DATA (push, screen->ntfy->handle);
 544
 545    if (dev->chipset < 0x40)
 546       oclass = NV30_SIFM_CLASS;
 547    else
 548       oclass = NV40_SIFM_CLASS;
 549
 550    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 551                             NULL, 0, &screen->sifm);
 552    if (ret)
 553       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 554
 555    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 556    PUSH_DATA (push, screen->sifm->handle);
 557    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 558    PUSH_DATA (push, screen->ntfy->handle);
 559    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 560    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 561
 562    nouveau_pushbuf_kick(push, push->channel);
 563
 564    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 565    return pscreen;
 566 }