src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format_s3tc.h"
  27
  28 #include "nouveau/nv_object.xml.h"
  29 #include "nouveau/nv_m2mf.xml.h"
  30 #include "nv30-40_3d.xml.h"
  31 #include "nv01_2d.xml.h"
  32
  33 #include "nouveau/nouveau_fence.h"
  34 #include "nv30_screen.h"
  35 #include "nv30_context.h"
  36 #include "nv30_resource.h"
  37 #include "nv30_format.h"
  38
  39 #define RANKINE_0397_CHIPSET 0x00000003
  40 #define RANKINE_0497_CHIPSET 0x000001e0
  41 #define RANKINE_0697_CHIPSET 0x00000010
  42 #define CURIE_4097_CHIPSET   0x00000baf
  43 #define CURIE_4497_CHIPSET   0x00005450
  44 #define CURIE_4497_CHIPSET6X 0x00000088
  45
  46 static int
  47 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  48 {
  49    struct nv30_screen *screen = nv30_screen(pscreen);
  50    struct nouveau_object *eng3d = screen->eng3d;
  51
  52    switch (param) {
  53    /* non-boolean capabilities */
  54    case PIPE_CAP_MAX_RENDER_TARGETS:
  55       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  56    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57       return 13;
  58    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59       return 10;
  60    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61       return 13;
  62    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  63       return 16;
  64    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  65       return 120;
  66    /* supported capabilities */
  67    case PIPE_CAP_TWO_SIDED_STENCIL:
  68    case PIPE_CAP_ANISOTROPIC_FILTER:
  69    case PIPE_CAP_POINT_SPRITE:
  70    case PIPE_CAP_SCALED_RESOLVE:
  71    case PIPE_CAP_OCCLUSION_QUERY:
  72    case PIPE_CAP_TIMER_QUERY:
  73    case PIPE_CAP_QUERY_TIMESTAMP:
  74    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  75    case PIPE_CAP_TEXTURE_SWIZZLE:
  76    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  77    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  82    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  83    case PIPE_CAP_USER_INDEX_BUFFERS:
  84       return 1;
  85    case PIPE_CAP_USER_VERTEX_BUFFERS:
  86       return 0;
  87    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  88       return 16;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 112    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 113    case PIPE_CAP_TEXTURE_BARRIER:
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 116    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 117    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 118    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 119    case PIPE_CAP_START_INSTANCE:
 120    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 121       return 0;
 122    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 123    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 124    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 125       return 1;
 126    default:
 127       debug_printf("unknown param %d\n", param);
 128       return 0;
 129    }
 130 }
 131
 132 static float
 133 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 134 {
 135    struct nv30_screen *screen = nv30_screen(pscreen);
 136    struct nouveau_object *eng3d = screen->eng3d;
 137
 138    switch (param) {
 139    case PIPE_CAPF_MAX_LINE_WIDTH:
 140    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 141       return 10.0;
 142    case PIPE_CAPF_MAX_POINT_WIDTH:
 143    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 144       return 64.0;
 145    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 146       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 147    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 148       return 15.0;
 149    default:
 150       debug_printf("unknown paramf %d\n", param);
 151       return 0;
 152    }
 153 }
 154
 155 static int
 156 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 157                              enum pipe_shader_cap param)
 158 {
 159    struct nv30_screen *screen = nv30_screen(pscreen);
 160    struct nouveau_object *eng3d = screen->eng3d;
 161
 162    switch (shader) {
 163    case PIPE_SHADER_VERTEX:
 164       switch (param) {
 165       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 166       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 167          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 168       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 169       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 170          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 171       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 172          return 0;
 173       case PIPE_SHADER_CAP_MAX_INPUTS:
 174          return 16;
 175       case PIPE_SHADER_CAP_MAX_CONSTS:
 176          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 177       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 178          return 1;
 179       case PIPE_SHADER_CAP_MAX_TEMPS:
 180          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 181       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 182          return 0;
 183       case PIPE_SHADER_CAP_MAX_ADDRS:
 184          return 2;
 185       case PIPE_SHADER_CAP_MAX_PREDS:
 186       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 187       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 188       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 189       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 190       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 191       case PIPE_SHADER_CAP_SUBROUTINES:
 192       case PIPE_SHADER_CAP_INTEGERS:
 193          return 0;
 194       default:
 195          debug_printf("unknown vertex shader param %d\n", param);
 196          return 0;
 197       }
 198       break;
 199    case PIPE_SHADER_FRAGMENT:
 200       switch (param) {
 201       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 202       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 203       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 204       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 205          return 4096;
 206       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 207          return 0;
 208       case PIPE_SHADER_CAP_MAX_INPUTS:
 209          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 210       case PIPE_SHADER_CAP_MAX_CONSTS:
 211          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 212       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 213          return 1;
 214       case PIPE_SHADER_CAP_MAX_TEMPS:
 215          return 32;
 216       case PIPE_SHADER_CAP_MAX_ADDRS:
 217          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 218       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 219          return 16;
 220       case PIPE_SHADER_CAP_MAX_PREDS:
 221       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 222       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 223       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 224       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 225       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 226       case PIPE_SHADER_CAP_SUBROUTINES:
 227          return 0;
 228       default:
 229          debug_printf("unknown fragment shader param %d\n", param);
 230          return 0;
 231       }
 232       break;
 233    default:
 234       return 0;
 235    }
 236 }
 237
 238 static boolean
 239 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 240                                 enum pipe_format format,
 241                                 enum pipe_texture_target target,
 242                                 unsigned sample_count,
 243                                 unsigned bindings)
 244 {
 245    if (!(0x00000017 & (1 << sample_count)))
 246       return FALSE;
 247
 248    if (!util_format_s3tc_enabled) {
 249       switch (format) {
 250       case PIPE_FORMAT_DXT1_RGB:
 251       case PIPE_FORMAT_DXT1_RGBA:
 252       case PIPE_FORMAT_DXT3_RGBA:
 253       case PIPE_FORMAT_DXT5_RGBA:
 254          return FALSE;
 255       default:
 256          break;
 257       }
 258    }
 259
 260    /* transfers & shared are always supported */
 261    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 262                  PIPE_BIND_TRANSFER_WRITE |
 263                  PIPE_BIND_SHARED);
 264
 265    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 266 }
 267
 268 static void
 269 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 270 {
 271    struct nv30_screen *screen = nv30_screen(pscreen);
 272    struct nouveau_pushbuf *push = screen->base.pushbuf;
 273
 274    *sequence = ++screen->base.fence.sequence;
 275
 276    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 277    PUSH_DATA (push, 0);
 278    PUSH_DATA (push, *sequence);
 279 }
 280
 281 static uint32_t
 282 nv30_screen_fence_update(struct pipe_screen *pscreen)
 283 {
 284    struct nv30_screen *screen = nv30_screen(pscreen);
 285    struct nv04_notify *fence = screen->fence->data;
 286    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 287 }
 288
 289 static void
 290 nv30_screen_destroy(struct pipe_screen *pscreen)
 291 {
 292    struct nv30_screen *screen = nv30_screen(pscreen);
 293
 294    if (screen->base.fence.current &&
 295        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 296       nouveau_fence_wait(screen->base.fence.current);
 297       nouveau_fence_ref (NULL, &screen->base.fence.current);
 298    }
 299
 300    nouveau_object_del(&screen->query);
 301    nouveau_object_del(&screen->fence);
 302    nouveau_object_del(&screen->ntfy);
 303
 304    nouveau_object_del(&screen->sifm);
 305    nouveau_object_del(&screen->swzsurf);
 306    nouveau_object_del(&screen->surf2d);
 307    nouveau_object_del(&screen->m2mf);
 308    nouveau_object_del(&screen->eng3d);
 309    nouveau_object_del(&screen->null);
 310
 311    nouveau_screen_fini(&screen->base);
 312    FREE(screen);
 313 }
 314
 315 #define FAIL_SCREEN_INIT(str, err)                    \
 316    do {                                               \
 317       NOUVEAU_ERR(str, err);                          \
 318       nv30_screen_destroy(pscreen);                   \
 319       return NULL;                                    \
 320    } while(0)
 321
 322 struct pipe_screen *
 323 nv30_screen_create(struct nouveau_device *dev)
 324 {
 325    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 326    struct pipe_screen *pscreen;
 327    struct nouveau_pushbuf *push;
 328    struct nv04_fifo *fifo;
 329    unsigned oclass = 0;
 330    int ret, i;
 331
 332    if (!screen)
 333       return NULL;
 334
 335    switch (dev->chipset & 0xf0) {
 336    case 0x30:
 337       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 338          oclass = NV30_3D_CLASS;
 339       else
 340       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 341          oclass = NV34_3D_CLASS;
 342       else
 343       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 344          oclass = NV35_3D_CLASS;
 345       break;
 346    case 0x40:
 347       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 348          oclass = NV40_3D_CLASS;
 349       else
 350       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 351          oclass = NV44_3D_CLASS;
 352       break;
 353    case 0x60:
 354       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 355          oclass = NV44_3D_CLASS;
 356       break;
 357    default:
 358       break;
 359    }
 360
 361    if (!oclass) {
 362       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 363       return NULL;
 364    }
 365
 366    pscreen = &screen->base.base;
 367    pscreen->destroy = nv30_screen_destroy;
 368    pscreen->get_param = nv30_screen_get_param;
 369    pscreen->get_paramf = nv30_screen_get_paramf;
 370    pscreen->get_shader_param = nv30_screen_get_shader_param;
 371    pscreen->context_create = nv30_context_create;
 372    pscreen->is_format_supported = nv30_screen_is_format_supported;
 373    nv30_resource_screen_init(pscreen);
 374
 375    screen->base.fence.emit = nv30_screen_fence_emit;
 376    screen->base.fence.update = nv30_screen_fence_update;
 377
 378    ret = nouveau_screen_init(&screen->base, dev);
 379    if (ret)
 380       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 381
 382    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 383    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 384    if (oclass == NV40_3D_CLASS) {
 385       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 386       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 387    }
 388
 389    fifo = screen->base.channel->data;
 390    push = screen->base.pushbuf;
 391    push->rsvd_kick = 16;
 392
 393    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 394                             NULL, 0, &screen->null);
 395    if (ret)
 396       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 397
 398    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 399     * this means that the address pointed at by the DMA object must
 400     * be 4KiB aligned, which means this object needs to be the first
 401     * one allocated on the channel.
 402     */
 403    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 404                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 405                             .length = 32 }, sizeof(struct nv04_notify),
 406                             &screen->fence);
 407    if (ret)
 408       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 409
 410    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 411    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 412                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 413                             .length = 32 }, sizeof(struct nv04_notify),
 414                             &screen->ntfy);
 415    if (ret)
 416       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 417
 418    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 419     * the remainder of the "notifier block" assigned by the kernel for
 420     * use as query objects
 421     */
 422    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 423                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 424                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 425                             &screen->query);
 426    if (ret)
 427       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 428
 429    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 430    if (ret)
 431       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 432
 433    LIST_INITHEAD(&screen->queries);
 434
 435    /* Vertex program resources (code/data), currently 6 of the constant
 436     * slots are reserved to implement user clipping planes
 437     */
 438    if (oclass < NV40_3D_CLASS) {
 439       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 440       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 441    } else {
 442       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 443       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 444    }
 445
 446    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 447    if (ret == 0)
 448       nouveau_bo_map(screen->notify, 0, screen->base.client);
 449    if (ret)
 450       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 451
 452    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 453                             NULL, 0, &screen->eng3d);
 454    if (ret)
 455       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 456
 457    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 458    PUSH_DATA (push, screen->eng3d->handle);
 459    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 460    PUSH_DATA (push, screen->ntfy->handle);
 461    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 462    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 463    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 464    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 465    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 466    PUSH_DATA (push, fifo->vram);     /* ZETA */
 467    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 468    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 469    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 470    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 471    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 472    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 473    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 474       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 475       PUSH_DATA (push, 0x00100000);
 476       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 477       PUSH_DATA (push, 3);
 478
 479       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 480       PUSH_DATA (push, 0);
 481       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 482       PUSH_DATA (push, fui(0.0));
 483       PUSH_DATA (push, fui(0.0));
 484       PUSH_DATA (push, fui(1.0));
 485       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 486       for (i = 0; i < 16; i++)
 487          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 488
 489       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 490       PUSH_DATA (push, 0);
 491    } else {
 492       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 493       PUSH_DATA (push, fifo->vram);
 494       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 495
 496       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 497       PUSH_DATA (push, 0x00000004);
 498
 499       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 500       PUSH_DATA (push, 0x00000010);
 501       PUSH_DATA (push, 0x01000100);
 502       PUSH_DATA (push, 0xff800006);
 503
 504       /* vtxprog output routing */
 505       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 506       PUSH_DATA (push, 0x06144321);
 507       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 508       PUSH_DATA (push, 0xedcba987);
 509       PUSH_DATA (push, 0x0000006f);
 510       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 511       PUSH_DATA (push, 0x00171615);
 512       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 513       PUSH_DATA (push, 0x001b1a19);
 514
 515       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 516       PUSH_DATA (push, 0x0020ffff);
 517       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 518       PUSH_DATA (push, 0x01d300d4);
 519
 520       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 521       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 522    }
 523
 524    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 525                             NULL, 0, &screen->m2mf);
 526    if (ret)
 527       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 528
 529    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 530    PUSH_DATA (push, screen->m2mf->handle);
 531    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 532    PUSH_DATA (push, screen->ntfy->handle);
 533
 534    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 535                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 536    if (ret)
 537       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 538
 539    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 540    PUSH_DATA (push, screen->surf2d->handle);
 541    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 542    PUSH_DATA (push, screen->ntfy->handle);
 543
 544    if (dev->chipset < 0x40)
 545       oclass = NV30_SURFACE_SWZ_CLASS;
 546    else
 547       oclass = NV40_SURFACE_SWZ_CLASS;
 548
 549    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 550                             NULL, 0, &screen->swzsurf);
 551    if (ret)
 552       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 553
 554    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 555    PUSH_DATA (push, screen->swzsurf->handle);
 556    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 557    PUSH_DATA (push, screen->ntfy->handle);
 558
 559    if (dev->chipset < 0x40)
 560       oclass = NV30_SIFM_CLASS;
 561    else
 562       oclass = NV40_SIFM_CLASS;
 563
 564    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 565                             NULL, 0, &screen->sifm);
 566    if (ret)
 567       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 568
 569    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 570    PUSH_DATA (push, screen->sifm->handle);
 571    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 572    PUSH_DATA (push, screen->ntfy->handle);
 573    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 574    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 575
 576    nouveau_pushbuf_kick(push, push->channel);
 577
 578    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 579    return pscreen;
 580 }