2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
29 #include "nouveau/nv_object.xml.h"
30 #include "nouveau/nv_m2mf.xml.h"
31 #include "nv30-40_3d.xml.h"
32 #include "nv01_2d.xml.h"
34 #include "nouveau/nouveau_fence.h"
35 #include "nv30_screen.h"
36 #include "nv30_context.h"
37 #include "nv30_resource.h"
38 #include "nv30_format.h"
40 #define RANKINE_0397_CHIPSET 0x00000003
41 #define RANKINE_0497_CHIPSET 0x000001e0
42 #define RANKINE_0697_CHIPSET 0x00000010
43 #define CURIE_4097_CHIPSET 0x00000baf
44 #define CURIE_4497_CHIPSET 0x00005450
45 #define CURIE_4497_CHIPSET6X 0x00000088
48 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
50 struct nv30_screen
*screen
= nv30_screen(pscreen
);
51 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 /* non-boolean capabilities */
55 case PIPE_CAP_MAX_RENDER_TARGETS
:
56 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
57 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
59 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
61 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
63 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
65 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
67 /* supported capabilities */
68 case PIPE_CAP_TWO_SIDED_STENCIL
:
69 case PIPE_CAP_ANISOTROPIC_FILTER
:
70 case PIPE_CAP_POINT_SPRITE
:
71 case PIPE_CAP_SCALED_RESOLVE
:
72 case PIPE_CAP_OCCLUSION_QUERY
:
73 case PIPE_CAP_QUERY_TIME_ELAPSED
:
74 case PIPE_CAP_QUERY_TIMESTAMP
:
75 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
76 case PIPE_CAP_TEXTURE_SWIZZLE
:
77 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
78 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
79 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
80 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
81 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
82 case PIPE_CAP_TGSI_TEXCOORD
:
83 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
84 case PIPE_CAP_USER_INDEX_BUFFERS
:
86 case PIPE_CAP_USER_VERTEX_BUFFERS
:
88 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
90 /* nv4x capabilities */
91 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
92 case PIPE_CAP_NPOT_TEXTURES
:
93 case PIPE_CAP_CONDITIONAL_RENDER
:
94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
95 case PIPE_CAP_PRIMITIVE_RESTART
:
96 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
98 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
100 case PIPE_CAP_INDEP_BLEND_ENABLE
:
101 case PIPE_CAP_INDEP_BLEND_FUNC
:
102 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
103 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
104 case PIPE_CAP_TGSI_INSTANCEID
:
105 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
106 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
107 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
108 case PIPE_CAP_MIN_TEXEL_OFFSET
:
109 case PIPE_CAP_MAX_TEXEL_OFFSET
:
110 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
111 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
112 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
113 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
114 case PIPE_CAP_TEXTURE_BARRIER
:
115 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
116 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
117 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
118 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
119 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
120 case PIPE_CAP_START_INSTANCE
:
121 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
122 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
123 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
124 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
126 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
127 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
128 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
131 debug_printf("unknown param %d\n", param
);
137 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
139 struct nv30_screen
*screen
= nv30_screen(pscreen
);
140 struct nouveau_object
*eng3d
= screen
->eng3d
;
143 case PIPE_CAPF_MAX_LINE_WIDTH
:
144 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
146 case PIPE_CAPF_MAX_POINT_WIDTH
:
147 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
149 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
150 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
151 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
154 debug_printf("unknown paramf %d\n", param
);
160 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
161 enum pipe_shader_cap param
)
163 struct nv30_screen
*screen
= nv30_screen(pscreen
);
164 struct nouveau_object
*eng3d
= screen
->eng3d
;
167 case PIPE_SHADER_VERTEX
:
169 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
170 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
171 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
172 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
173 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
174 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
175 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
177 case PIPE_SHADER_CAP_MAX_INPUTS
:
179 case PIPE_SHADER_CAP_MAX_CONSTS
:
180 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6);
181 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
183 case PIPE_SHADER_CAP_MAX_TEMPS
:
184 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
185 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
187 case PIPE_SHADER_CAP_MAX_ADDRS
:
189 case PIPE_SHADER_CAP_MAX_PREDS
:
190 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
191 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
192 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
193 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
194 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
195 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
196 case PIPE_SHADER_CAP_SUBROUTINES
:
197 case PIPE_SHADER_CAP_INTEGERS
:
200 debug_printf("unknown vertex shader param %d\n", param
);
204 case PIPE_SHADER_FRAGMENT
:
206 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
207 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
208 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
209 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
211 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
213 case PIPE_SHADER_CAP_MAX_INPUTS
:
214 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 12 : 10;
215 case PIPE_SHADER_CAP_MAX_CONSTS
:
216 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32;
217 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
219 case PIPE_SHADER_CAP_MAX_TEMPS
:
221 case PIPE_SHADER_CAP_MAX_ADDRS
:
222 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
223 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
225 case PIPE_SHADER_CAP_MAX_PREDS
:
226 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
227 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
228 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
229 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
230 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
231 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
232 case PIPE_SHADER_CAP_SUBROUTINES
:
235 debug_printf("unknown fragment shader param %d\n", param
);
245 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
246 enum pipe_format format
,
247 enum pipe_texture_target target
,
248 unsigned sample_count
,
251 if (sample_count
> 4)
253 if (!(0x00000017 & (1 << sample_count
)))
256 if (!util_format_is_supported(format
, bindings
)) {
260 /* transfers & shared are always supported */
261 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
262 PIPE_BIND_TRANSFER_WRITE
|
265 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
269 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
271 struct nv30_screen
*screen
= nv30_screen(pscreen
);
272 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
274 *sequence
= ++screen
->base
.fence
.sequence
;
276 BEGIN_NV04(push
, NV30_3D(FENCE_OFFSET
), 2);
278 PUSH_DATA (push
, *sequence
);
282 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
284 struct nv30_screen
*screen
= nv30_screen(pscreen
);
285 struct nv04_notify
*fence
= screen
->fence
->data
;
286 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
290 nv30_screen_destroy(struct pipe_screen
*pscreen
)
292 struct nv30_screen
*screen
= nv30_screen(pscreen
);
294 if (screen
->base
.fence
.current
&&
295 screen
->base
.fence
.current
->state
>= NOUVEAU_FENCE_STATE_EMITTED
) {
296 nouveau_fence_wait(screen
->base
.fence
.current
);
297 nouveau_fence_ref (NULL
, &screen
->base
.fence
.current
);
300 nouveau_object_del(&screen
->query
);
301 nouveau_object_del(&screen
->fence
);
302 nouveau_object_del(&screen
->ntfy
);
304 nouveau_object_del(&screen
->sifm
);
305 nouveau_object_del(&screen
->swzsurf
);
306 nouveau_object_del(&screen
->surf2d
);
307 nouveau_object_del(&screen
->m2mf
);
308 nouveau_object_del(&screen
->eng3d
);
309 nouveau_object_del(&screen
->null
);
311 nouveau_screen_fini(&screen
->base
);
315 #define FAIL_SCREEN_INIT(str, err) \
317 NOUVEAU_ERR(str, err); \
318 nv30_screen_destroy(pscreen); \
323 nv30_screen_create(struct nouveau_device
*dev
)
325 struct nv30_screen
*screen
= CALLOC_STRUCT(nv30_screen
);
326 struct pipe_screen
*pscreen
;
327 struct nouveau_pushbuf
*push
;
328 struct nv04_fifo
*fifo
;
335 switch (dev
->chipset
& 0xf0) {
337 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
338 oclass
= NV30_3D_CLASS
;
340 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
341 oclass
= NV34_3D_CLASS
;
343 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
344 oclass
= NV35_3D_CLASS
;
347 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
348 oclass
= NV40_3D_CLASS
;
350 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
351 oclass
= NV44_3D_CLASS
;
354 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
355 oclass
= NV44_3D_CLASS
;
362 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
367 pscreen
= &screen
->base
.base
;
368 pscreen
->destroy
= nv30_screen_destroy
;
369 pscreen
->get_param
= nv30_screen_get_param
;
370 pscreen
->get_paramf
= nv30_screen_get_paramf
;
371 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
372 pscreen
->context_create
= nv30_context_create
;
373 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
374 nv30_resource_screen_init(pscreen
);
376 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
377 screen
->base
.fence
.update
= nv30_screen_fence_update
;
379 ret
= nouveau_screen_init(&screen
->base
, dev
);
381 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
383 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
384 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
385 if (oclass
== NV40_3D_CLASS
) {
386 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
387 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
390 fifo
= screen
->base
.channel
->data
;
391 push
= screen
->base
.pushbuf
;
392 push
->rsvd_kick
= 16;
394 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
395 NULL
, 0, &screen
->null
);
397 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
399 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
400 * this means that the address pointed at by the DMA object must
401 * be 4KiB aligned, which means this object needs to be the first
402 * one allocated on the channel.
404 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
405 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
406 .length
= 32 }, sizeof(struct nv04_notify
),
409 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
411 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
412 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
413 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
414 .length
= 32 }, sizeof(struct nv04_notify
),
417 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
419 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
420 * the remainder of the "notifier block" assigned by the kernel for
421 * use as query objects
423 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
424 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
425 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
428 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
430 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
432 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
434 LIST_INITHEAD(&screen
->queries
);
436 /* Vertex program resources (code/data), currently 6 of the constant
437 * slots are reserved to implement user clipping planes
439 if (oclass
< NV40_3D_CLASS
) {
440 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
441 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
443 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
444 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
447 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
449 nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
451 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
453 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
454 NULL
, 0, &screen
->eng3d
);
456 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
458 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
459 PUSH_DATA (push
, screen
->eng3d
->handle
);
460 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
461 PUSH_DATA (push
, screen
->ntfy
->handle
);
462 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
463 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
464 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
465 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
466 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
467 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
468 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
469 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
470 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
471 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
472 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
473 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
474 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
475 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
476 PUSH_DATA (push
, 0x00100000);
477 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
480 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
482 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
483 PUSH_DATA (push
, fui(0.0));
484 PUSH_DATA (push
, fui(0.0));
485 PUSH_DATA (push
, fui(1.0));
486 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
487 for (i
= 0; i
< 16; i
++)
488 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
490 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
493 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
494 PUSH_DATA (push
, fifo
->vram
);
495 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
497 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
498 PUSH_DATA (push
, 0x00000004);
500 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
501 PUSH_DATA (push
, 0x00000010);
502 PUSH_DATA (push
, 0x01000100);
503 PUSH_DATA (push
, 0xff800006);
505 /* vtxprog output routing */
506 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
507 PUSH_DATA (push
, 0x06144321);
508 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
509 PUSH_DATA (push
, 0xedcba987);
510 PUSH_DATA (push
, 0x0000006f);
511 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
512 PUSH_DATA (push
, 0x00171615);
513 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
514 PUSH_DATA (push
, 0x001b1a19);
516 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
517 PUSH_DATA (push
, 0x0020ffff);
518 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
519 PUSH_DATA (push
, 0x01d300d4);
521 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
522 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
525 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
526 NULL
, 0, &screen
->m2mf
);
528 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
530 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
531 PUSH_DATA (push
, screen
->m2mf
->handle
);
532 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
533 PUSH_DATA (push
, screen
->ntfy
->handle
);
535 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
536 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
538 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
540 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
541 PUSH_DATA (push
, screen
->surf2d
->handle
);
542 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
543 PUSH_DATA (push
, screen
->ntfy
->handle
);
545 if (dev
->chipset
< 0x40)
546 oclass
= NV30_SURFACE_SWZ_CLASS
;
548 oclass
= NV40_SURFACE_SWZ_CLASS
;
550 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
551 NULL
, 0, &screen
->swzsurf
);
553 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
555 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
556 PUSH_DATA (push
, screen
->swzsurf
->handle
);
557 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
558 PUSH_DATA (push
, screen
->ntfy
->handle
);
560 if (dev
->chipset
< 0x40)
561 oclass
= NV30_SIFM_CLASS
;
563 oclass
= NV40_SIFM_CLASS
;
565 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
566 NULL
, 0, &screen
->sifm
);
568 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
570 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
571 PUSH_DATA (push
, screen
->sifm
->handle
);
572 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
573 PUSH_DATA (push
, screen
->ntfy
->handle
);
574 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
575 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
577 nouveau_pushbuf_kick(push
, push
->channel
);
579 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);