src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nouveau/nv_m2mf.xml.h"
  31 #include "nv30-40_3d.xml.h"
  32 #include "nv01_2d.xml.h"
  33
  34 #include "nouveau/nouveau_fence.h"
  35 #include "nv30_screen.h"
  36 #include "nv30_context.h"
  37 #include "nv30_resource.h"
  38 #include "nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64       return 16;
  65    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  66       return 120;
  67    /* supported capabilities */
  68    case PIPE_CAP_TWO_SIDED_STENCIL:
  69    case PIPE_CAP_ANISOTROPIC_FILTER:
  70    case PIPE_CAP_POINT_SPRITE:
  71    case PIPE_CAP_SCALED_RESOLVE:
  72    case PIPE_CAP_OCCLUSION_QUERY:
  73    case PIPE_CAP_QUERY_TIME_ELAPSED:
  74    case PIPE_CAP_QUERY_TIMESTAMP:
  75    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  76    case PIPE_CAP_TEXTURE_SWIZZLE:
  77    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  82    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  83    case PIPE_CAP_USER_INDEX_BUFFERS:
  84       return 1;
  85    case PIPE_CAP_USER_VERTEX_BUFFERS:
  86       return 0;
  87    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  88       return 16;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 112    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 113    case PIPE_CAP_TEXTURE_BARRIER:
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 116    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 117    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 118    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 119    case PIPE_CAP_START_INSTANCE:
 120    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 121    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 122    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 123    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 124       return 0;
 125    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 126    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 127    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 128       return 1;
 129    default:
 130       debug_printf("unknown param %d\n", param);
 131       return 0;
 132    }
 133 }
 134
 135 static float
 136 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 137 {
 138    struct nv30_screen *screen = nv30_screen(pscreen);
 139    struct nouveau_object *eng3d = screen->eng3d;
 140
 141    switch (param) {
 142    case PIPE_CAPF_MAX_LINE_WIDTH:
 143    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 144       return 10.0;
 145    case PIPE_CAPF_MAX_POINT_WIDTH:
 146    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 147       return 64.0;
 148    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 149       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 150    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 151       return 15.0;
 152    default:
 153       debug_printf("unknown paramf %d\n", param);
 154       return 0;
 155    }
 156 }
 157
 158 static int
 159 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 160                              enum pipe_shader_cap param)
 161 {
 162    struct nv30_screen *screen = nv30_screen(pscreen);
 163    struct nouveau_object *eng3d = screen->eng3d;
 164
 165    switch (shader) {
 166    case PIPE_SHADER_VERTEX:
 167       switch (param) {
 168       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 169       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 170          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 171       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 172       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 173          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 174       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 175          return 0;
 176       case PIPE_SHADER_CAP_MAX_INPUTS:
 177          return 16;
 178       case PIPE_SHADER_CAP_MAX_CONSTS:
 179          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 180       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 181          return 1;
 182       case PIPE_SHADER_CAP_MAX_TEMPS:
 183          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 184       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 185          return 0;
 186       case PIPE_SHADER_CAP_MAX_ADDRS:
 187          return 2;
 188       case PIPE_SHADER_CAP_MAX_PREDS:
 189       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 190       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 191       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 192       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 193       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 194       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 195       case PIPE_SHADER_CAP_SUBROUTINES:
 196       case PIPE_SHADER_CAP_INTEGERS:
 197          return 0;
 198       default:
 199          debug_printf("unknown vertex shader param %d\n", param);
 200          return 0;
 201       }
 202       break;
 203    case PIPE_SHADER_FRAGMENT:
 204       switch (param) {
 205       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 206       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 207       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 208       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 209          return 4096;
 210       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 211          return 0;
 212       case PIPE_SHADER_CAP_MAX_INPUTS:
 213          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 214       case PIPE_SHADER_CAP_MAX_CONSTS:
 215          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 216       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 217          return 1;
 218       case PIPE_SHADER_CAP_MAX_TEMPS:
 219          return 32;
 220       case PIPE_SHADER_CAP_MAX_ADDRS:
 221          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 222       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 223          return 16;
 224       case PIPE_SHADER_CAP_MAX_PREDS:
 225       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 226       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 227       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 228       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 229       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 230       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 231       case PIPE_SHADER_CAP_SUBROUTINES:
 232          return 0;
 233       default:
 234          debug_printf("unknown fragment shader param %d\n", param);
 235          return 0;
 236       }
 237       break;
 238    default:
 239       return 0;
 240    }
 241 }
 242
 243 static boolean
 244 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 245                                 enum pipe_format format,
 246                                 enum pipe_texture_target target,
 247                                 unsigned sample_count,
 248                                 unsigned bindings)
 249 {
 250    if (sample_count > 4)
 251       return FALSE;
 252    if (!(0x00000017 & (1 << sample_count)))
 253       return FALSE;
 254
 255    if (!util_format_is_supported(format, bindings)) {
 256       return FALSE;
 257    }
 258
 259    /* transfers & shared are always supported */
 260    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 261                  PIPE_BIND_TRANSFER_WRITE |
 262                  PIPE_BIND_SHARED);
 263
 264    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 265 }
 266
 267 static void
 268 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 269 {
 270    struct nv30_screen *screen = nv30_screen(pscreen);
 271    struct nouveau_pushbuf *push = screen->base.pushbuf;
 272
 273    *sequence = ++screen->base.fence.sequence;
 274
 275    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 276    PUSH_DATA (push, 0);
 277    PUSH_DATA (push, *sequence);
 278 }
 279
 280 static uint32_t
 281 nv30_screen_fence_update(struct pipe_screen *pscreen)
 282 {
 283    struct nv30_screen *screen = nv30_screen(pscreen);
 284    struct nv04_notify *fence = screen->fence->data;
 285    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 286 }
 287
 288 static void
 289 nv30_screen_destroy(struct pipe_screen *pscreen)
 290 {
 291    struct nv30_screen *screen = nv30_screen(pscreen);
 292
 293    if (screen->base.fence.current &&
 294        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 295       nouveau_fence_wait(screen->base.fence.current);
 296       nouveau_fence_ref (NULL, &screen->base.fence.current);
 297    }
 298
 299    nouveau_object_del(&screen->query);
 300    nouveau_object_del(&screen->fence);
 301    nouveau_object_del(&screen->ntfy);
 302
 303    nouveau_object_del(&screen->sifm);
 304    nouveau_object_del(&screen->swzsurf);
 305    nouveau_object_del(&screen->surf2d);
 306    nouveau_object_del(&screen->m2mf);
 307    nouveau_object_del(&screen->eng3d);
 308    nouveau_object_del(&screen->null);
 309
 310    nouveau_screen_fini(&screen->base);
 311    FREE(screen);
 312 }
 313
 314 #define FAIL_SCREEN_INIT(str, err)                    \
 315    do {                                               \
 316       NOUVEAU_ERR(str, err);                          \
 317       nv30_screen_destroy(pscreen);                   \
 318       return NULL;                                    \
 319    } while(0)
 320
 321 struct pipe_screen *
 322 nv30_screen_create(struct nouveau_device *dev)
 323 {
 324    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 325    struct pipe_screen *pscreen;
 326    struct nouveau_pushbuf *push;
 327    struct nv04_fifo *fifo;
 328    unsigned oclass = 0;
 329    int ret, i;
 330
 331    if (!screen)
 332       return NULL;
 333
 334    switch (dev->chipset & 0xf0) {
 335    case 0x30:
 336       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 337          oclass = NV30_3D_CLASS;
 338       else
 339       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 340          oclass = NV34_3D_CLASS;
 341       else
 342       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 343          oclass = NV35_3D_CLASS;
 344       break;
 345    case 0x40:
 346       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 347          oclass = NV40_3D_CLASS;
 348       else
 349       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 350          oclass = NV44_3D_CLASS;
 351       break;
 352    case 0x60:
 353       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 354          oclass = NV44_3D_CLASS;
 355       break;
 356    default:
 357       break;
 358    }
 359
 360    if (!oclass) {
 361       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 362       return NULL;
 363    }
 364
 365    pscreen = &screen->base.base;
 366    pscreen->destroy = nv30_screen_destroy;
 367    pscreen->get_param = nv30_screen_get_param;
 368    pscreen->get_paramf = nv30_screen_get_paramf;
 369    pscreen->get_shader_param = nv30_screen_get_shader_param;
 370    pscreen->context_create = nv30_context_create;
 371    pscreen->is_format_supported = nv30_screen_is_format_supported;
 372    nv30_resource_screen_init(pscreen);
 373
 374    screen->base.fence.emit = nv30_screen_fence_emit;
 375    screen->base.fence.update = nv30_screen_fence_update;
 376
 377    ret = nouveau_screen_init(&screen->base, dev);
 378    if (ret)
 379       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 380
 381    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 382    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 383    if (oclass == NV40_3D_CLASS) {
 384       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 385       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 386    }
 387
 388    fifo = screen->base.channel->data;
 389    push = screen->base.pushbuf;
 390    push->rsvd_kick = 16;
 391
 392    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 393                             NULL, 0, &screen->null);
 394    if (ret)
 395       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 396
 397    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 398     * this means that the address pointed at by the DMA object must
 399     * be 4KiB aligned, which means this object needs to be the first
 400     * one allocated on the channel.
 401     */
 402    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 403                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 404                             .length = 32 }, sizeof(struct nv04_notify),
 405                             &screen->fence);
 406    if (ret)
 407       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 408
 409    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 410    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 411                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 412                             .length = 32 }, sizeof(struct nv04_notify),
 413                             &screen->ntfy);
 414    if (ret)
 415       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 416
 417    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 418     * the remainder of the "notifier block" assigned by the kernel for
 419     * use as query objects
 420     */
 421    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 422                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 423                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 424                             &screen->query);
 425    if (ret)
 426       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 427
 428    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 429    if (ret)
 430       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 431
 432    LIST_INITHEAD(&screen->queries);
 433
 434    /* Vertex program resources (code/data), currently 6 of the constant
 435     * slots are reserved to implement user clipping planes
 436     */
 437    if (oclass < NV40_3D_CLASS) {
 438       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 439       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 440    } else {
 441       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 442       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 443    }
 444
 445    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 446    if (ret == 0)
 447       nouveau_bo_map(screen->notify, 0, screen->base.client);
 448    if (ret)
 449       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 450
 451    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 452                             NULL, 0, &screen->eng3d);
 453    if (ret)
 454       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 455
 456    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 457    PUSH_DATA (push, screen->eng3d->handle);
 458    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 459    PUSH_DATA (push, screen->ntfy->handle);
 460    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 461    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 462    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 463    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 464    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 465    PUSH_DATA (push, fifo->vram);     /* ZETA */
 466    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 467    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 468    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 469    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 470    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 471    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 472    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 473       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 474       PUSH_DATA (push, 0x00100000);
 475       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 476       PUSH_DATA (push, 3);
 477
 478       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 479       PUSH_DATA (push, 0);
 480       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 481       PUSH_DATA (push, fui(0.0));
 482       PUSH_DATA (push, fui(0.0));
 483       PUSH_DATA (push, fui(1.0));
 484       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 485       for (i = 0; i < 16; i++)
 486          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 487
 488       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 489       PUSH_DATA (push, 0);
 490    } else {
 491       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 492       PUSH_DATA (push, fifo->vram);
 493       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 494
 495       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 496       PUSH_DATA (push, 0x00000004);
 497
 498       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 499       PUSH_DATA (push, 0x00000010);
 500       PUSH_DATA (push, 0x01000100);
 501       PUSH_DATA (push, 0xff800006);
 502
 503       /* vtxprog output routing */
 504       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 505       PUSH_DATA (push, 0x06144321);
 506       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 507       PUSH_DATA (push, 0xedcba987);
 508       PUSH_DATA (push, 0x0000006f);
 509       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 510       PUSH_DATA (push, 0x00171615);
 511       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 512       PUSH_DATA (push, 0x001b1a19);
 513
 514       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 515       PUSH_DATA (push, 0x0020ffff);
 516       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 517       PUSH_DATA (push, 0x01d300d4);
 518
 519       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 520       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 521    }
 522
 523    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 524                             NULL, 0, &screen->m2mf);
 525    if (ret)
 526       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 527
 528    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 529    PUSH_DATA (push, screen->m2mf->handle);
 530    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 531    PUSH_DATA (push, screen->ntfy->handle);
 532
 533    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 534                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 535    if (ret)
 536       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 537
 538    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 539    PUSH_DATA (push, screen->surf2d->handle);
 540    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 541    PUSH_DATA (push, screen->ntfy->handle);
 542
 543    if (dev->chipset < 0x40)
 544       oclass = NV30_SURFACE_SWZ_CLASS;
 545    else
 546       oclass = NV40_SURFACE_SWZ_CLASS;
 547
 548    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 549                             NULL, 0, &screen->swzsurf);
 550    if (ret)
 551       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 552
 553    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 554    PUSH_DATA (push, screen->swzsurf->handle);
 555    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 556    PUSH_DATA (push, screen->ntfy->handle);
 557
 558    if (dev->chipset < 0x40)
 559       oclass = NV30_SIFM_CLASS;
 560    else
 561       oclass = NV40_SIFM_CLASS;
 562
 563    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 564                             NULL, 0, &screen->sifm);
 565    if (ret)
 566       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 567
 568    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 569    PUSH_DATA (push, screen->sifm->handle);
 570    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 571    PUSH_DATA (push, screen->ntfy->handle);
 572    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 573    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 574
 575    nouveau_pushbuf_kick(push, push->channel);
 576
 577    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 578    return pscreen;
 579 }