2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
29 #include "nouveau/nv_object.xml.h"
30 #include "nouveau/nv_m2mf.xml.h"
31 #include "nv30-40_3d.xml.h"
32 #include "nv01_2d.xml.h"
34 #include "nouveau/nouveau_fence.h"
35 #include "nv30_screen.h"
36 #include "nv30_context.h"
37 #include "nv30_resource.h"
38 #include "nv30_format.h"
40 #define RANKINE_0397_CHIPSET 0x00000003
41 #define RANKINE_0497_CHIPSET 0x000001e0
42 #define RANKINE_0697_CHIPSET 0x00000010
43 #define CURIE_4097_CHIPSET 0x00000baf
44 #define CURIE_4497_CHIPSET 0x00005450
45 #define CURIE_4497_CHIPSET6X 0x00000088
48 nv30_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
50 struct nv30_screen
*screen
= nv30_screen(pscreen
);
51 struct nouveau_object
*eng3d
= screen
->eng3d
;
54 /* non-boolean capabilities */
55 case PIPE_CAP_MAX_RENDER_TARGETS
:
56 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 4 : 1;
57 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
59 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
61 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
63 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
65 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
67 /* supported capabilities */
68 case PIPE_CAP_TWO_SIDED_STENCIL
:
69 case PIPE_CAP_ANISOTROPIC_FILTER
:
70 case PIPE_CAP_POINT_SPRITE
:
71 case PIPE_CAP_SCALED_RESOLVE
:
72 case PIPE_CAP_OCCLUSION_QUERY
:
73 case PIPE_CAP_QUERY_TIME_ELAPSED
:
74 case PIPE_CAP_QUERY_TIMESTAMP
:
75 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
76 case PIPE_CAP_TEXTURE_SWIZZLE
:
77 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
78 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
79 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
80 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
81 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
82 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
83 case PIPE_CAP_USER_INDEX_BUFFERS
:
85 case PIPE_CAP_USER_VERTEX_BUFFERS
:
87 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
89 /* nv4x capabilities */
90 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
91 case PIPE_CAP_NPOT_TEXTURES
:
92 case PIPE_CAP_CONDITIONAL_RENDER
:
93 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
94 case PIPE_CAP_PRIMITIVE_RESTART
:
95 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
97 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
99 case PIPE_CAP_INDEP_BLEND_ENABLE
:
100 case PIPE_CAP_INDEP_BLEND_FUNC
:
101 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
102 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
103 case PIPE_CAP_TGSI_INSTANCEID
:
104 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* XXX: yes? */
105 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
106 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
107 case PIPE_CAP_MIN_TEXEL_OFFSET
:
108 case PIPE_CAP_MAX_TEXEL_OFFSET
:
109 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
110 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
111 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
112 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
113 case PIPE_CAP_TEXTURE_BARRIER
:
114 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
115 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
116 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
117 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
118 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
119 case PIPE_CAP_START_INSTANCE
:
120 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
121 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
122 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
123 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
125 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
126 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
127 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
130 debug_printf("unknown param %d\n", param
);
136 nv30_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
138 struct nv30_screen
*screen
= nv30_screen(pscreen
);
139 struct nouveau_object
*eng3d
= screen
->eng3d
;
142 case PIPE_CAPF_MAX_LINE_WIDTH
:
143 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
145 case PIPE_CAPF_MAX_POINT_WIDTH
:
146 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
148 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
149 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 16.0 : 8.0;
150 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
153 debug_printf("unknown paramf %d\n", param
);
159 nv30_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
160 enum pipe_shader_cap param
)
162 struct nv30_screen
*screen
= nv30_screen(pscreen
);
163 struct nouveau_object
*eng3d
= screen
->eng3d
;
166 case PIPE_SHADER_VERTEX
:
168 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
169 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
170 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 256;
171 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
172 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
173 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 512 : 0;
174 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
176 case PIPE_SHADER_CAP_MAX_INPUTS
:
178 case PIPE_SHADER_CAP_MAX_CONSTS
:
179 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? (468 - 6): (256 - 6);
180 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
182 case PIPE_SHADER_CAP_MAX_TEMPS
:
183 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 32 : 13;
184 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
186 case PIPE_SHADER_CAP_MAX_ADDRS
:
188 case PIPE_SHADER_CAP_MAX_PREDS
:
189 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
190 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
191 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
192 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
193 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
194 case PIPE_SHADER_CAP_SUBROUTINES
:
195 case PIPE_SHADER_CAP_INTEGERS
:
198 debug_printf("unknown vertex shader param %d\n", param
);
202 case PIPE_SHADER_FRAGMENT
:
204 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
205 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
206 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
207 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
209 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
211 case PIPE_SHADER_CAP_MAX_INPUTS
:
212 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 12 : 10;
213 case PIPE_SHADER_CAP_MAX_CONSTS
:
214 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 224 : 32;
215 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
217 case PIPE_SHADER_CAP_MAX_TEMPS
:
219 case PIPE_SHADER_CAP_MAX_ADDRS
:
220 return (eng3d
->oclass
>= NV40_3D_CLASS
) ? 1 : 0;
221 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
223 case PIPE_SHADER_CAP_MAX_PREDS
:
224 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
225 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
226 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
227 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
228 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
229 case PIPE_SHADER_CAP_SUBROUTINES
:
232 debug_printf("unknown fragment shader param %d\n", param
);
242 nv30_screen_is_format_supported(struct pipe_screen
*pscreen
,
243 enum pipe_format format
,
244 enum pipe_texture_target target
,
245 unsigned sample_count
,
248 if (sample_count
> 4)
250 if (!(0x00000017 & (1 << sample_count
)))
253 if (!util_format_is_supported(format
, bindings
)) {
257 /* transfers & shared are always supported */
258 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
259 PIPE_BIND_TRANSFER_WRITE
|
262 return (nv30_format_info(pscreen
, format
)->bindings
& bindings
) == bindings
;
266 nv30_screen_fence_emit(struct pipe_screen
*pscreen
, uint32_t *sequence
)
268 struct nv30_screen
*screen
= nv30_screen(pscreen
);
269 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
271 *sequence
= ++screen
->base
.fence
.sequence
;
273 BEGIN_NV04(push
, NV30_3D(FENCE_OFFSET
), 2);
275 PUSH_DATA (push
, *sequence
);
279 nv30_screen_fence_update(struct pipe_screen
*pscreen
)
281 struct nv30_screen
*screen
= nv30_screen(pscreen
);
282 struct nv04_notify
*fence
= screen
->fence
->data
;
283 return *(uint32_t *)((char *)screen
->notify
->map
+ fence
->offset
);
287 nv30_screen_destroy(struct pipe_screen
*pscreen
)
289 struct nv30_screen
*screen
= nv30_screen(pscreen
);
291 if (screen
->base
.fence
.current
&&
292 screen
->base
.fence
.current
->state
>= NOUVEAU_FENCE_STATE_EMITTED
) {
293 nouveau_fence_wait(screen
->base
.fence
.current
);
294 nouveau_fence_ref (NULL
, &screen
->base
.fence
.current
);
297 nouveau_object_del(&screen
->query
);
298 nouveau_object_del(&screen
->fence
);
299 nouveau_object_del(&screen
->ntfy
);
301 nouveau_object_del(&screen
->sifm
);
302 nouveau_object_del(&screen
->swzsurf
);
303 nouveau_object_del(&screen
->surf2d
);
304 nouveau_object_del(&screen
->m2mf
);
305 nouveau_object_del(&screen
->eng3d
);
306 nouveau_object_del(&screen
->null
);
308 nouveau_screen_fini(&screen
->base
);
312 #define FAIL_SCREEN_INIT(str, err) \
314 NOUVEAU_ERR(str, err); \
315 nv30_screen_destroy(pscreen); \
320 nv30_screen_create(struct nouveau_device
*dev
)
322 struct nv30_screen
*screen
= CALLOC_STRUCT(nv30_screen
);
323 struct pipe_screen
*pscreen
;
324 struct nouveau_pushbuf
*push
;
325 struct nv04_fifo
*fifo
;
332 switch (dev
->chipset
& 0xf0) {
334 if (RANKINE_0397_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
335 oclass
= NV30_3D_CLASS
;
337 if (RANKINE_0697_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
338 oclass
= NV34_3D_CLASS
;
340 if (RANKINE_0497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
341 oclass
= NV35_3D_CLASS
;
344 if (CURIE_4097_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
345 oclass
= NV40_3D_CLASS
;
347 if (CURIE_4497_CHIPSET
& (1 << (dev
->chipset
& 0x0f)))
348 oclass
= NV44_3D_CLASS
;
351 if (CURIE_4497_CHIPSET6X
& (1 << (dev
->chipset
& 0x0f)))
352 oclass
= NV44_3D_CLASS
;
359 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev
->chipset
);
363 pscreen
= &screen
->base
.base
;
364 pscreen
->destroy
= nv30_screen_destroy
;
365 pscreen
->get_param
= nv30_screen_get_param
;
366 pscreen
->get_paramf
= nv30_screen_get_paramf
;
367 pscreen
->get_shader_param
= nv30_screen_get_shader_param
;
368 pscreen
->context_create
= nv30_context_create
;
369 pscreen
->is_format_supported
= nv30_screen_is_format_supported
;
370 nv30_resource_screen_init(pscreen
);
372 screen
->base
.fence
.emit
= nv30_screen_fence_emit
;
373 screen
->base
.fence
.update
= nv30_screen_fence_update
;
375 ret
= nouveau_screen_init(&screen
->base
, dev
);
377 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret
);
379 screen
->base
.vidmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
380 screen
->base
.sysmem_bindings
|= PIPE_BIND_VERTEX_BUFFER
;
381 if (oclass
== NV40_3D_CLASS
) {
382 screen
->base
.vidmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
383 screen
->base
.sysmem_bindings
|= PIPE_BIND_INDEX_BUFFER
;
386 fifo
= screen
->base
.channel
->data
;
387 push
= screen
->base
.pushbuf
;
388 push
->rsvd_kick
= 16;
390 ret
= nouveau_object_new(screen
->base
.channel
, 0x00000000, NV01_NULL_CLASS
,
391 NULL
, 0, &screen
->null
);
393 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret
);
395 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
396 * this means that the address pointed at by the DMA object must
397 * be 4KiB aligned, which means this object needs to be the first
398 * one allocated on the channel.
400 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef1e00,
401 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
402 .length
= 32 }, sizeof(struct nv04_notify
),
405 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret
);
407 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
408 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0301,
409 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
410 .length
= 32 }, sizeof(struct nv04_notify
),
413 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret
);
415 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
416 * the remainder of the "notifier block" assigned by the kernel for
417 * use as query objects
419 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef0351,
420 NOUVEAU_NOTIFIER_CLASS
, &(struct nv04_notify
) {
421 .length
= 4096 - 128 }, sizeof(struct nv04_notify
),
424 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret
);
426 ret
= nouveau_heap_init(&screen
->query_heap
, 0, 4096 - 128);
428 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret
);
430 LIST_INITHEAD(&screen
->queries
);
432 /* Vertex program resources (code/data), currently 6 of the constant
433 * slots are reserved to implement user clipping planes
435 if (oclass
< NV40_3D_CLASS
) {
436 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 256);
437 nouveau_heap_init(&screen
->vp_data_heap
, 6, 256 - 6);
439 nouveau_heap_init(&screen
->vp_exec_heap
, 0, 512);
440 nouveau_heap_init(&screen
->vp_data_heap
, 6, 468 - 6);
443 ret
= nouveau_bo_wrap(screen
->base
.device
, fifo
->notify
, &screen
->notify
);
445 nouveau_bo_map(screen
->notify
, 0, screen
->base
.client
);
447 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret
);
449 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3097, oclass
,
450 NULL
, 0, &screen
->eng3d
);
452 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret
);
454 BEGIN_NV04(push
, NV01_SUBC(3D
, OBJECT
), 1);
455 PUSH_DATA (push
, screen
->eng3d
->handle
);
456 BEGIN_NV04(push
, NV30_3D(DMA_NOTIFY
), 13);
457 PUSH_DATA (push
, screen
->ntfy
->handle
);
458 PUSH_DATA (push
, fifo
->vram
); /* TEXTURE0 */
459 PUSH_DATA (push
, fifo
->gart
); /* TEXTURE1 */
460 PUSH_DATA (push
, fifo
->vram
); /* COLOR1 */
461 PUSH_DATA (push
, screen
->null
->handle
); /* UNK190 */
462 PUSH_DATA (push
, fifo
->vram
); /* COLOR0 */
463 PUSH_DATA (push
, fifo
->vram
); /* ZETA */
464 PUSH_DATA (push
, fifo
->vram
); /* VTXBUF0 */
465 PUSH_DATA (push
, fifo
->gart
); /* VTXBUF1 */
466 PUSH_DATA (push
, screen
->fence
->handle
); /* FENCE */
467 PUSH_DATA (push
, screen
->query
->handle
); /* QUERY - intr 0x80 if nullobj */
468 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1AC */
469 PUSH_DATA (push
, screen
->null
->handle
); /* UNK1B0 */
470 if (screen
->eng3d
->oclass
< NV40_3D_CLASS
) {
471 BEGIN_NV04(push
, SUBC_3D(0x03b0), 1);
472 PUSH_DATA (push
, 0x00100000);
473 BEGIN_NV04(push
, SUBC_3D(0x1d80), 1);
476 BEGIN_NV04(push
, SUBC_3D(0x1e98), 1);
478 BEGIN_NV04(push
, SUBC_3D(0x17e0), 3);
479 PUSH_DATA (push
, fui(0.0));
480 PUSH_DATA (push
, fui(0.0));
481 PUSH_DATA (push
, fui(1.0));
482 BEGIN_NV04(push
, SUBC_3D(0x1f80), 16);
483 for (i
= 0; i
< 16; i
++)
484 PUSH_DATA (push
, (i
== 8) ? 0x0000ffff : 0);
486 BEGIN_NV04(push
, NV30_3D(RC_ENABLE
), 1);
489 BEGIN_NV04(push
, NV40_3D(DMA_COLOR2
), 2);
490 PUSH_DATA (push
, fifo
->vram
);
491 PUSH_DATA (push
, fifo
->vram
); /* COLOR3 */
493 BEGIN_NV04(push
, SUBC_3D(0x1450), 1);
494 PUSH_DATA (push
, 0x00000004);
496 BEGIN_NV04(push
, SUBC_3D(0x1ea4), 3); /* ZCULL */
497 PUSH_DATA (push
, 0x00000010);
498 PUSH_DATA (push
, 0x01000100);
499 PUSH_DATA (push
, 0xff800006);
501 /* vtxprog output routing */
502 BEGIN_NV04(push
, SUBC_3D(0x1fc4), 1);
503 PUSH_DATA (push
, 0x06144321);
504 BEGIN_NV04(push
, SUBC_3D(0x1fc8), 2);
505 PUSH_DATA (push
, 0xedcba987);
506 PUSH_DATA (push
, 0x0000006f);
507 BEGIN_NV04(push
, SUBC_3D(0x1fd0), 1);
508 PUSH_DATA (push
, 0x00171615);
509 BEGIN_NV04(push
, SUBC_3D(0x1fd4), 1);
510 PUSH_DATA (push
, 0x001b1a19);
512 BEGIN_NV04(push
, SUBC_3D(0x1ef8), 1);
513 PUSH_DATA (push
, 0x0020ffff);
514 BEGIN_NV04(push
, SUBC_3D(0x1d64), 1);
515 PUSH_DATA (push
, 0x01d300d4);
517 BEGIN_NV04(push
, NV40_3D(MIPMAP_ROUNDING
), 1);
518 PUSH_DATA (push
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
521 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef3901, NV03_M2MF_CLASS
,
522 NULL
, 0, &screen
->m2mf
);
524 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret
);
526 BEGIN_NV04(push
, NV01_SUBC(M2MF
, OBJECT
), 1);
527 PUSH_DATA (push
, screen
->m2mf
->handle
);
528 BEGIN_NV04(push
, NV03_M2MF(DMA_NOTIFY
), 1);
529 PUSH_DATA (push
, screen
->ntfy
->handle
);
531 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef6201,
532 NV10_SURFACE_2D_CLASS
, NULL
, 0, &screen
->surf2d
);
534 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret
);
536 BEGIN_NV04(push
, NV01_SUBC(SF2D
, OBJECT
), 1);
537 PUSH_DATA (push
, screen
->surf2d
->handle
);
538 BEGIN_NV04(push
, NV04_SF2D(DMA_NOTIFY
), 1);
539 PUSH_DATA (push
, screen
->ntfy
->handle
);
541 if (dev
->chipset
< 0x40)
542 oclass
= NV30_SURFACE_SWZ_CLASS
;
544 oclass
= NV40_SURFACE_SWZ_CLASS
;
546 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef5201, oclass
,
547 NULL
, 0, &screen
->swzsurf
);
549 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret
);
551 BEGIN_NV04(push
, NV01_SUBC(SSWZ
, OBJECT
), 1);
552 PUSH_DATA (push
, screen
->swzsurf
->handle
);
553 BEGIN_NV04(push
, NV04_SSWZ(DMA_NOTIFY
), 1);
554 PUSH_DATA (push
, screen
->ntfy
->handle
);
556 if (dev
->chipset
< 0x40)
557 oclass
= NV30_SIFM_CLASS
;
559 oclass
= NV40_SIFM_CLASS
;
561 ret
= nouveau_object_new(screen
->base
.channel
, 0xbeef7701, oclass
,
562 NULL
, 0, &screen
->sifm
);
564 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret
);
566 BEGIN_NV04(push
, NV01_SUBC(SIFM
, OBJECT
), 1);
567 PUSH_DATA (push
, screen
->sifm
->handle
);
568 BEGIN_NV04(push
, NV03_SIFM(DMA_NOTIFY
), 1);
569 PUSH_DATA (push
, screen
->ntfy
->handle
);
570 BEGIN_NV04(push
, NV05_SIFM(COLOR_CONVERSION
), 1);
571 PUSH_DATA (push
, NV05_SIFM_COLOR_CONVERSION_TRUNCATE
);
573 nouveau_pushbuf_kick(push
, push
->channel
);
575 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);