src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nouveau/nv_m2mf.xml.h"
  31 #include "nv30-40_3d.xml.h"
  32 #include "nv01_2d.xml.h"
  33
  34 #include "nouveau/nouveau_fence.h"
  35 #include "nv30_screen.h"
  36 #include "nv30_context.h"
  37 #include "nv30_resource.h"
  38 #include "nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64       return 16;
  65    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  66       return 120;
  67    /* supported capabilities */
  68    case PIPE_CAP_TWO_SIDED_STENCIL:
  69    case PIPE_CAP_ANISOTROPIC_FILTER:
  70    case PIPE_CAP_POINT_SPRITE:
  71    case PIPE_CAP_SCALED_RESOLVE:
  72    case PIPE_CAP_OCCLUSION_QUERY:
  73    case PIPE_CAP_QUERY_TIME_ELAPSED:
  74    case PIPE_CAP_QUERY_TIMESTAMP:
  75    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  76    case PIPE_CAP_TEXTURE_SWIZZLE:
  77    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  82    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  83    case PIPE_CAP_USER_INDEX_BUFFERS:
  84       return 1;
  85    case PIPE_CAP_USER_VERTEX_BUFFERS:
  86       return 0;
  87    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  88       return 16;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 112    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 113    case PIPE_CAP_TEXTURE_BARRIER:
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 116    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 117    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 118    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 119    case PIPE_CAP_START_INSTANCE:
 120    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 121    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 122    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 123       return 0;
 124    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 125    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 126    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 127       return 1;
 128    default:
 129       debug_printf("unknown param %d\n", param);
 130       return 0;
 131    }
 132 }
 133
 134 static float
 135 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 136 {
 137    struct nv30_screen *screen = nv30_screen(pscreen);
 138    struct nouveau_object *eng3d = screen->eng3d;
 139
 140    switch (param) {
 141    case PIPE_CAPF_MAX_LINE_WIDTH:
 142    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 143       return 10.0;
 144    case PIPE_CAPF_MAX_POINT_WIDTH:
 145    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 146       return 64.0;
 147    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 148       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 149    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 150       return 15.0;
 151    default:
 152       debug_printf("unknown paramf %d\n", param);
 153       return 0;
 154    }
 155 }
 156
 157 static int
 158 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 159                              enum pipe_shader_cap param)
 160 {
 161    struct nv30_screen *screen = nv30_screen(pscreen);
 162    struct nouveau_object *eng3d = screen->eng3d;
 163
 164    switch (shader) {
 165    case PIPE_SHADER_VERTEX:
 166       switch (param) {
 167       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 168       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 169          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 170       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 171       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 172          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 173       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 174          return 0;
 175       case PIPE_SHADER_CAP_MAX_INPUTS:
 176          return 16;
 177       case PIPE_SHADER_CAP_MAX_CONSTS:
 178          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 179       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 180          return 1;
 181       case PIPE_SHADER_CAP_MAX_TEMPS:
 182          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 183       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 184          return 0;
 185       case PIPE_SHADER_CAP_MAX_ADDRS:
 186          return 2;
 187       case PIPE_SHADER_CAP_MAX_PREDS:
 188       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 189       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 190       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 191       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 192       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 193       case PIPE_SHADER_CAP_SUBROUTINES:
 194       case PIPE_SHADER_CAP_INTEGERS:
 195          return 0;
 196       default:
 197          debug_printf("unknown vertex shader param %d\n", param);
 198          return 0;
 199       }
 200       break;
 201    case PIPE_SHADER_FRAGMENT:
 202       switch (param) {
 203       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 204       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 205       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 206       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 207          return 4096;
 208       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 209          return 0;
 210       case PIPE_SHADER_CAP_MAX_INPUTS:
 211          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 212       case PIPE_SHADER_CAP_MAX_CONSTS:
 213          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 214       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 215          return 1;
 216       case PIPE_SHADER_CAP_MAX_TEMPS:
 217          return 32;
 218       case PIPE_SHADER_CAP_MAX_ADDRS:
 219          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 220       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 221          return 16;
 222       case PIPE_SHADER_CAP_MAX_PREDS:
 223       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 224       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 225       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 226       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 227       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 228       case PIPE_SHADER_CAP_SUBROUTINES:
 229          return 0;
 230       default:
 231          debug_printf("unknown fragment shader param %d\n", param);
 232          return 0;
 233       }
 234       break;
 235    default:
 236       return 0;
 237    }
 238 }
 239
 240 static boolean
 241 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 242                                 enum pipe_format format,
 243                                 enum pipe_texture_target target,
 244                                 unsigned sample_count,
 245                                 unsigned bindings)
 246 {
 247    if (sample_count > 4)
 248       return FALSE;
 249    if (!(0x00000017 & (1 << sample_count)))
 250       return FALSE;
 251
 252    if (!util_format_is_supported(format, bindings)) {
 253       return FALSE;
 254    }
 255
 256    /* transfers & shared are always supported */
 257    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 258                  PIPE_BIND_TRANSFER_WRITE |
 259                  PIPE_BIND_SHARED);
 260
 261    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 262 }
 263
 264 static void
 265 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 266 {
 267    struct nv30_screen *screen = nv30_screen(pscreen);
 268    struct nouveau_pushbuf *push = screen->base.pushbuf;
 269
 270    *sequence = ++screen->base.fence.sequence;
 271
 272    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 273    PUSH_DATA (push, 0);
 274    PUSH_DATA (push, *sequence);
 275 }
 276
 277 static uint32_t
 278 nv30_screen_fence_update(struct pipe_screen *pscreen)
 279 {
 280    struct nv30_screen *screen = nv30_screen(pscreen);
 281    struct nv04_notify *fence = screen->fence->data;
 282    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 283 }
 284
 285 static void
 286 nv30_screen_destroy(struct pipe_screen *pscreen)
 287 {
 288    struct nv30_screen *screen = nv30_screen(pscreen);
 289
 290    if (screen->base.fence.current &&
 291        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 292       nouveau_fence_wait(screen->base.fence.current);
 293       nouveau_fence_ref (NULL, &screen->base.fence.current);
 294    }
 295
 296    nouveau_object_del(&screen->query);
 297    nouveau_object_del(&screen->fence);
 298    nouveau_object_del(&screen->ntfy);
 299
 300    nouveau_object_del(&screen->sifm);
 301    nouveau_object_del(&screen->swzsurf);
 302    nouveau_object_del(&screen->surf2d);
 303    nouveau_object_del(&screen->m2mf);
 304    nouveau_object_del(&screen->eng3d);
 305    nouveau_object_del(&screen->null);
 306
 307    nouveau_screen_fini(&screen->base);
 308    FREE(screen);
 309 }
 310
 311 #define FAIL_SCREEN_INIT(str, err)                    \
 312    do {                                               \
 313       NOUVEAU_ERR(str, err);                          \
 314       nv30_screen_destroy(pscreen);                   \
 315       return NULL;                                    \
 316    } while(0)
 317
 318 struct pipe_screen *
 319 nv30_screen_create(struct nouveau_device *dev)
 320 {
 321    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 322    struct pipe_screen *pscreen;
 323    struct nouveau_pushbuf *push;
 324    struct nv04_fifo *fifo;
 325    unsigned oclass = 0;
 326    int ret, i;
 327
 328    if (!screen)
 329       return NULL;
 330
 331    switch (dev->chipset & 0xf0) {
 332    case 0x30:
 333       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 334          oclass = NV30_3D_CLASS;
 335       else
 336       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 337          oclass = NV34_3D_CLASS;
 338       else
 339       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 340          oclass = NV35_3D_CLASS;
 341       break;
 342    case 0x40:
 343       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 344          oclass = NV40_3D_CLASS;
 345       else
 346       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 347          oclass = NV44_3D_CLASS;
 348       break;
 349    case 0x60:
 350       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 351          oclass = NV44_3D_CLASS;
 352       break;
 353    default:
 354       break;
 355    }
 356
 357    if (!oclass) {
 358       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 359       return NULL;
 360    }
 361
 362    pscreen = &screen->base.base;
 363    pscreen->destroy = nv30_screen_destroy;
 364    pscreen->get_param = nv30_screen_get_param;
 365    pscreen->get_paramf = nv30_screen_get_paramf;
 366    pscreen->get_shader_param = nv30_screen_get_shader_param;
 367    pscreen->context_create = nv30_context_create;
 368    pscreen->is_format_supported = nv30_screen_is_format_supported;
 369    nv30_resource_screen_init(pscreen);
 370
 371    screen->base.fence.emit = nv30_screen_fence_emit;
 372    screen->base.fence.update = nv30_screen_fence_update;
 373
 374    ret = nouveau_screen_init(&screen->base, dev);
 375    if (ret)
 376       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 377
 378    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 379    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 380    if (oclass == NV40_3D_CLASS) {
 381       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 382       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 383    }
 384
 385    fifo = screen->base.channel->data;
 386    push = screen->base.pushbuf;
 387    push->rsvd_kick = 16;
 388
 389    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 390                             NULL, 0, &screen->null);
 391    if (ret)
 392       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 393
 394    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 395     * this means that the address pointed at by the DMA object must
 396     * be 4KiB aligned, which means this object needs to be the first
 397     * one allocated on the channel.
 398     */
 399    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 400                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 401                             .length = 32 }, sizeof(struct nv04_notify),
 402                             &screen->fence);
 403    if (ret)
 404       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 405
 406    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 407    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 408                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 409                             .length = 32 }, sizeof(struct nv04_notify),
 410                             &screen->ntfy);
 411    if (ret)
 412       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 413
 414    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 415     * the remainder of the "notifier block" assigned by the kernel for
 416     * use as query objects
 417     */
 418    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 419                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 420                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 421                             &screen->query);
 422    if (ret)
 423       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 424
 425    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 426    if (ret)
 427       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 428
 429    LIST_INITHEAD(&screen->queries);
 430
 431    /* Vertex program resources (code/data), currently 6 of the constant
 432     * slots are reserved to implement user clipping planes
 433     */
 434    if (oclass < NV40_3D_CLASS) {
 435       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 436       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 437    } else {
 438       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 439       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 440    }
 441
 442    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 443    if (ret == 0)
 444       nouveau_bo_map(screen->notify, 0, screen->base.client);
 445    if (ret)
 446       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 447
 448    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 449                             NULL, 0, &screen->eng3d);
 450    if (ret)
 451       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 452
 453    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 454    PUSH_DATA (push, screen->eng3d->handle);
 455    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 456    PUSH_DATA (push, screen->ntfy->handle);
 457    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 458    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 459    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 460    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 461    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 462    PUSH_DATA (push, fifo->vram);     /* ZETA */
 463    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 464    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 465    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 466    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 467    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 468    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 469    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 470       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 471       PUSH_DATA (push, 0x00100000);
 472       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 473       PUSH_DATA (push, 3);
 474
 475       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 476       PUSH_DATA (push, 0);
 477       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 478       PUSH_DATA (push, fui(0.0));
 479       PUSH_DATA (push, fui(0.0));
 480       PUSH_DATA (push, fui(1.0));
 481       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 482       for (i = 0; i < 16; i++)
 483          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 484
 485       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 486       PUSH_DATA (push, 0);
 487    } else {
 488       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 489       PUSH_DATA (push, fifo->vram);
 490       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 491
 492       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 493       PUSH_DATA (push, 0x00000004);
 494
 495       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 496       PUSH_DATA (push, 0x00000010);
 497       PUSH_DATA (push, 0x01000100);
 498       PUSH_DATA (push, 0xff800006);
 499
 500       /* vtxprog output routing */
 501       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 502       PUSH_DATA (push, 0x06144321);
 503       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 504       PUSH_DATA (push, 0xedcba987);
 505       PUSH_DATA (push, 0x0000006f);
 506       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 507       PUSH_DATA (push, 0x00171615);
 508       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 509       PUSH_DATA (push, 0x001b1a19);
 510
 511       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 512       PUSH_DATA (push, 0x0020ffff);
 513       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 514       PUSH_DATA (push, 0x01d300d4);
 515
 516       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 517       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 518    }
 519
 520    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 521                             NULL, 0, &screen->m2mf);
 522    if (ret)
 523       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 524
 525    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 526    PUSH_DATA (push, screen->m2mf->handle);
 527    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 528    PUSH_DATA (push, screen->ntfy->handle);
 529
 530    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 531                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 532    if (ret)
 533       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 534
 535    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 536    PUSH_DATA (push, screen->surf2d->handle);
 537    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 538    PUSH_DATA (push, screen->ntfy->handle);
 539
 540    if (dev->chipset < 0x40)
 541       oclass = NV30_SURFACE_SWZ_CLASS;
 542    else
 543       oclass = NV40_SURFACE_SWZ_CLASS;
 544
 545    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 546                             NULL, 0, &screen->swzsurf);
 547    if (ret)
 548       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 549
 550    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 551    PUSH_DATA (push, screen->swzsurf->handle);
 552    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 553    PUSH_DATA (push, screen->ntfy->handle);
 554
 555    if (dev->chipset < 0x40)
 556       oclass = NV30_SIFM_CLASS;
 557    else
 558       oclass = NV40_SIFM_CLASS;
 559
 560    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 561                             NULL, 0, &screen->sifm);
 562    if (ret)
 563       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 564
 565    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 566    PUSH_DATA (push, screen->sifm->handle);
 567    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 568    PUSH_DATA (push, screen->ntfy->handle);
 569    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 570    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 571
 572    nouveau_pushbuf_kick(push, push->channel);
 573
 574    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 575    return pscreen;
 576 }