src/gallium/drivers/nv30/nv30_state.c

   1 #include "pipe/p_state.h"
   2 #include "pipe/p_defines.h"
   3 #include "pipe/p_util.h"
   4
   5 #include "nv30_context.h"
   6 #include "nv30_state.h"
   7
   8 static void *
   9 nv30_blend_state_create(struct pipe_context *pipe,
  10                         const struct pipe_blend_state *cso)
  11 {
  12         struct nv30_blend_state *cb;
  13
  14         cb = malloc(sizeof(struct nv30_blend_state));
  15
  16         cb->b_enable = cso->blend_enable ? 1 : 0;
  17         cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) |
  18                          (nvgl_blend_func(cso->rgb_src_factor)));
  19         cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) |
  20                          (nvgl_blend_func(cso->rgb_dst_factor)));
  21         cb->b_eqn = ((nvgl_blend_eqn(cso->alpha_func) << 16) |
  22                      (nvgl_blend_eqn(cso->rgb_func)));
  23
  24         cb->l_enable = cso->logicop_enable ? 1 : 0;
  25         cb->l_op = nvgl_logicop_func(cso->logicop_func);
  26
  27         cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) |
  28                       ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) |
  29                       ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) |
  30                       ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0));
  31
  32         cb->d_enable = cso->dither ? 1 : 0;
  33
  34         return (void *)cb;
  35 }
  36
  37 static void
  38 nv30_blend_state_bind(struct pipe_context *pipe, void *hwcso)
  39 {
  40         struct nv30_context *nv30 = nv30_context(pipe);
  41         struct nv30_blend_state *cb = hwcso;
  42
  43         BEGIN_RING(rankine, NV34TCL_DITHER_ENABLE, 1);
  44         OUT_RING  (cb->d_enable);
  45
  46         BEGIN_RING(rankine, NV34TCL_BLEND_FUNC_ENABLE, 3);
  47         OUT_RING  (cb->b_enable);
  48         OUT_RING  (cb->b_srcfunc);
  49         OUT_RING  (cb->b_dstfunc);
  50         BEGIN_RING(rankine, NV34TCL_BLEND_FUNC_EQUATION, 1);
  51         OUT_RING  (cb->b_eqn);
  52
  53         BEGIN_RING(rankine, NV34TCL_COLOR_MASK, 1);
  54         OUT_RING  (cb->c_mask);
  55
  56         BEGIN_RING(rankine, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
  57         OUT_RING  (cb->l_enable);
  58         OUT_RING  (cb->l_op);
  59 }
  60
  61 static void
  62 nv30_blend_state_delete(struct pipe_context *pipe, void *hwcso)
  63 {
  64         free(hwcso);
  65 }
  66
  67
  68 static INLINE unsigned
  69 wrap_mode(unsigned wrap) {
  70         unsigned ret;
  71
  72         switch (wrap) {
  73         case PIPE_TEX_WRAP_REPEAT:
  74                 ret = NV34TCL_TX_WRAP_S_REPEAT;
  75                 break;
  76         case PIPE_TEX_WRAP_MIRROR_REPEAT:
  77                 ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT;
  78                 break;
  79         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
  80                 ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE;
  81                 break;
  82         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
  83                 ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER;
  84                 break;
  85         case PIPE_TEX_WRAP_CLAMP:
  86                 ret = NV34TCL_TX_WRAP_S_CLAMP;
  87                 break;
  88 /*      case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
  89                 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
  90                 break;
  91         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
  92                 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
  93                 break;
  94         case PIPE_TEX_WRAP_MIRROR_CLAMP:
  95                 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP;
  96                 break;*/
  97         default:
  98                 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
  99                 ret = NV34TCL_TX_WRAP_S_REPEAT;
 100                 break;
 101         }
 102
 103         return ret >> NV34TCL_TX_WRAP_S_SHIFT;
 104 }
 105
 106 static void *
 107 nv30_sampler_state_create(struct pipe_context *pipe,
 108                           const struct pipe_sampler_state *cso)
 109 {
 110         struct nv30_sampler_state *ps;
 111         uint32_t filter = 0;
 112
 113         ps = malloc(sizeof(struct nv30_sampler_state));
 114
 115         ps->fmt = 0;
 116         if (!cso->normalized_coords)
 117                 ps->fmt |= NV34TCL_TX_FORMAT_RECT;
 118
 119         ps->wrap = ((wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) |
 120                     (wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) |
 121                     (wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT));
 122
 123         ps->en = 0;
 124         if (cso->max_anisotropy >= 2.0) {
 125                 /* no idea, binary driver sets it, works without it.. meh.. */
 126                 ps->wrap |= (1 << 5);
 127
 128 /*              if (cso->max_anisotropy >= 16.0) {
 129                         ps->en |= NV34TCL_TX_ENABLE_ANISO_16X;
 130                 } else
 131                 if (cso->max_anisotropy >= 12.0) {
 132                         ps->en |= NV34TCL_TX_ENABLE_ANISO_12X;
 133                 } else
 134                 if (cso->max_anisotropy >= 10.0) {
 135                         ps->en |= NV34TCL_TX_ENABLE_ANISO_10X;
 136                 } else
 137                 if (cso->max_anisotropy >= 8.0) {
 138                         ps->en |= NV34TCL_TX_ENABLE_ANISO_8X;
 139                 } else
 140                 if (cso->max_anisotropy >= 6.0) {
 141                         ps->en |= NV34TCL_TX_ENABLE_ANISO_6X;
 142                 } else
 143                 if (cso->max_anisotropy >= 4.0) {
 144                         ps->en |= NV34TCL_TX_ENABLE_ANISO_4X;
 145                 } else {
 146                         ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
 147                 }*/
 148         }
 149
 150         switch (cso->mag_img_filter) {
 151         case PIPE_TEX_FILTER_LINEAR:
 152                 filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR;
 153                 break;
 154         case PIPE_TEX_FILTER_NEAREST:
 155         default:
 156                 filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST;
 157                 break;
 158         }
 159
 160         switch (cso->min_img_filter) {
 161         case PIPE_TEX_FILTER_LINEAR:
 162                 switch (cso->min_mip_filter) {
 163                 case PIPE_TEX_MIPFILTER_NEAREST:
 164                         filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST;
 165                         break;
 166                 case PIPE_TEX_MIPFILTER_LINEAR:
 167                         filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR;
 168                         break;
 169                 case PIPE_TEX_MIPFILTER_NONE:
 170                 default:
 171                         filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR;
 172                         break;
 173                 }
 174                 break;
 175         case PIPE_TEX_FILTER_NEAREST:
 176         default:
 177                 switch (cso->min_mip_filter) {
 178                 case PIPE_TEX_MIPFILTER_NEAREST:
 179                         filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST;
 180                 break;
 181                 case PIPE_TEX_MIPFILTER_LINEAR:
 182                         filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR;
 183                         break;
 184                 case PIPE_TEX_MIPFILTER_NONE:
 185                 default:
 186                         filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST;
 187                         break;
 188                 }
 189                 break;
 190         }
 191
 192         ps->filt = filter;
 193
 194 /*      if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
 195                 switch (cso->compare_func) {
 196                 case PIPE_FUNC_NEVER:
 197                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NEVER;
 198                         break;
 199                 case PIPE_FUNC_GREATER:
 200                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GREATER;
 201                         break;
 202                 case PIPE_FUNC_EQUAL:
 203                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_EQUAL;
 204                         break;
 205                 case PIPE_FUNC_GEQUAL:
 206                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GEQUAL;
 207                         break;
 208                 case PIPE_FUNC_LESS:
 209                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LESS;
 210                         break;
 211                 case PIPE_FUNC_NOTEQUAL:
 212                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NOTEQUAL;
 213                         break;
 214                 case PIPE_FUNC_LEQUAL:
 215                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LEQUAL;
 216                         break;
 217                 case PIPE_FUNC_ALWAYS:
 218                         ps->wrap |= NV34TCL_TX_WRAP_RCOMP_ALWAYS;
 219                         break;
 220                 default:
 221                         break;
 222                 }
 223         }*/
 224
 225         ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
 226                     (float_to_ubyte(cso->border_color[0]) << 16) |
 227                     (float_to_ubyte(cso->border_color[1]) <<  8) |
 228                     (float_to_ubyte(cso->border_color[2]) <<  0));
 229
 230         return (void *)ps;
 231 }
 232
 233 static void
 234 nv30_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
 235 {
 236         struct nv30_context *nv30 = nv30_context(pipe);
 237         unsigned unit;
 238
 239         for (unit = 0; unit < nr; unit++) {
 240                 nv30->tex_sampler[unit] = sampler[unit];
 241                 nv30->dirty_samplers |= (1 << unit);
 242         }
 243 }
 244
 245 static void
 246 nv30_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
 247 {
 248         free(hwcso);
 249 }
 250
 251 static void
 252 nv30_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
 253                          struct pipe_texture **miptree)
 254 {
 255         struct nv30_context *nv30 = nv30_context(pipe);
 256         unsigned unit;
 257
 258         for (unit = 0; unit < nr; unit++) {
 259                 nv30->tex_miptree[unit] = (struct nv30_miptree *)miptree[unit];
 260                 nv30->dirty_samplers |= (1 << unit);
 261         }
 262 }
 263
 264 static void *
 265 nv30_rasterizer_state_create(struct pipe_context *pipe,
 266                              const struct pipe_rasterizer_state *cso)
 267 {
 268         struct nv30_rasterizer_state *rs;
 269         int i;
 270
 271         /*XXX: ignored:
 272          *      light_twoside
 273          *      offset_cw/ccw -nohw
 274          *      scissor
 275          *      point_smooth -nohw
 276          *      multisample
 277          *      offset_units / offset_scale
 278          */
 279         rs = malloc(sizeof(struct nv30_rasterizer_state));
 280
 281         rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01;
 282
 283         rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff;
 284         rs->line_smooth_en = cso->line_smooth ? 1 : 0;
 285         rs->line_stipple_en = cso->line_stipple_enable ? 1 : 0;
 286         rs->line_stipple = (cso->line_stipple_pattern << 16) |
 287                             cso->line_stipple_factor;
 288
 289         rs->point_size = *(uint32_t*)&cso->point_size;
 290
 291         rs->poly_smooth_en = cso->poly_smooth ? 1 : 0;
 292         rs->poly_stipple_en = cso->poly_stipple_enable ? 1 : 0;
 293
 294         if (cso->front_winding == PIPE_WINDING_CCW) {
 295                 rs->front_face = NV34TCL_FRONT_FACE_CCW;
 296                 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw);
 297                 rs->poly_mode_back  = nvgl_polygon_mode(cso->fill_cw);
 298         } else {
 299                 rs->front_face = NV34TCL_FRONT_FACE_CW;
 300                 rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw);
 301                 rs->poly_mode_back  = nvgl_polygon_mode(cso->fill_ccw);
 302         }
 303
 304         switch (cso->cull_mode) {
 305         case PIPE_WINDING_CCW:
 306                 rs->cull_face_en = 1;
 307                 if (cso->front_winding == PIPE_WINDING_CCW)
 308                         rs->cull_face    = NV34TCL_CULL_FACE_FRONT;
 309                 else
 310                         rs->cull_face    = NV34TCL_CULL_FACE_BACK;
 311                 break;
 312         case PIPE_WINDING_CW:
 313                 rs->cull_face_en = 1;
 314                 if (cso->front_winding == PIPE_WINDING_CW)
 315                         rs->cull_face    = NV34TCL_CULL_FACE_FRONT;
 316                 else
 317                         rs->cull_face    = NV34TCL_CULL_FACE_BACK;
 318                 break;
 319         case PIPE_WINDING_BOTH:
 320                 rs->cull_face_en = 1;
 321                 rs->cull_face    = NV34TCL_CULL_FACE_FRONT_AND_BACK;
 322                 break;
 323         case PIPE_WINDING_NONE:
 324         default:
 325                 rs->cull_face_en = 0;
 326                 rs->cull_face    = 0;
 327                 break;
 328         }
 329
 330         if (cso->point_sprite) {
 331                 rs->point_sprite = (1 << 0);
 332                 for (i = 0; i < 8; i++) {
 333                         if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
 334                                 rs->point_sprite |= (1 << (8 + i));
 335                 }
 336         } else {
 337                 rs->point_sprite = 0;
 338         }
 339
 340         return (void *)rs;
 341 }
 342
 343 static void
 344 nv30_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 345 {
 346         struct nv30_context *nv30 = nv30_context(pipe);
 347         struct nv30_rasterizer_state *rs = hwcso;
 348
 349         BEGIN_RING(rankine, NV34TCL_SHADE_MODEL, 1);
 350         OUT_RING  (rs->shade_model);
 351
 352         BEGIN_RING(rankine, NV34TCL_LINE_WIDTH, 2);
 353         OUT_RING  (rs->line_width);
 354         OUT_RING  (rs->line_smooth_en);
 355         BEGIN_RING(rankine, NV34TCL_LINE_STIPPLE_ENABLE, 2);
 356         OUT_RING  (rs->line_stipple_en);
 357         OUT_RING  (rs->line_stipple);
 358
 359         BEGIN_RING(rankine, NV34TCL_POINT_SIZE, 1);
 360         OUT_RING  (rs->point_size);
 361
 362         BEGIN_RING(rankine, NV34TCL_POLYGON_MODE_FRONT, 6);
 363         OUT_RING  (rs->poly_mode_front);
 364         OUT_RING  (rs->poly_mode_back);
 365         OUT_RING  (rs->cull_face);
 366         OUT_RING  (rs->front_face);
 367         OUT_RING  (rs->poly_smooth_en);
 368         OUT_RING  (rs->cull_face_en);
 369
 370         BEGIN_RING(rankine, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 371         OUT_RING  (rs->poly_stipple_en);
 372
 373         BEGIN_RING(rankine, NV34TCL_POINT_SPRITE, 1);
 374         OUT_RING  (rs->point_sprite);
 375 }
 376
 377 static void
 378 nv30_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
 379 {
 380         free(hwcso);
 381 }
 382
 383 static void
 384 nv30_translate_stencil(const struct pipe_depth_stencil_alpha_state *cso,
 385                        unsigned idx, struct nv30_stencil_push *hw)
 386 {
 387         hw->enable = cso->stencil[idx].enabled ? 1 : 0;
 388         hw->wmask = cso->stencil[idx].write_mask;
 389         hw->func = nvgl_comparison_op(cso->stencil[idx].func);
 390         hw->ref = cso->stencil[idx].ref_value;
 391         hw->vmask = cso->stencil[idx].value_mask;
 392         hw->fail = nvgl_stencil_op(cso->stencil[idx].fail_op);
 393         hw->zfail = nvgl_stencil_op(cso->stencil[idx].zfail_op);
 394         hw->zpass = nvgl_stencil_op(cso->stencil[idx].zpass_op);
 395 }
 396
 397 static void *
 398 nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 399                         const struct pipe_depth_stencil_alpha_state *cso)
 400 {
 401         struct nv30_depth_stencil_alpha_state *hw;
 402
 403         hw = malloc(sizeof(struct nv30_depth_stencil_alpha_state));
 404
 405         hw->depth.func          = nvgl_comparison_op(cso->depth.func);
 406         hw->depth.write_enable  = cso->depth.writemask ? 1 : 0;
 407         hw->depth.test_enable   = cso->depth.enabled ? 1 : 0;
 408
 409         nv30_translate_stencil(cso, 0, &hw->stencil.front);
 410         nv30_translate_stencil(cso, 1, &hw->stencil.back);
 411
 412         hw->alpha.enabled = cso->alpha.enabled ? 1 : 0;
 413         hw->alpha.func = nvgl_comparison_op(cso->alpha.func);
 414         hw->alpha.ref  = float_to_ubyte(cso->alpha.ref);
 415
 416         return (void *)hw;
 417 }
 418
 419 static void
 420 nv30_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
 421 {
 422         struct nv30_context *nv30 = nv30_context(pipe);
 423         struct nv30_depth_stencil_alpha_state *hw = hwcso;
 424
 425         BEGIN_RING(rankine, NV34TCL_DEPTH_FUNC, 3);
 426         OUT_RINGp ((uint32_t *)&hw->depth, 3);
 427         BEGIN_RING(rankine, NV34TCL_STENCIL_BACK_ENABLE, 16);
 428         OUT_RINGp ((uint32_t *)&hw->stencil.back, 8);
 429         OUT_RINGp ((uint32_t *)&hw->stencil.front, 8);
 430         BEGIN_RING(rankine, NV34TCL_ALPHA_FUNC_ENABLE, 3);
 431         OUT_RINGp ((uint32_t *)&hw->alpha.enabled, 3);
 432 }
 433
 434 static void
 435 nv30_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
 436 {
 437         free(hwcso);
 438 }
 439
 440 static void *
 441 nv30_vp_state_create(struct pipe_context *pipe,
 442                      const struct pipe_shader_state *cso)
 443 {
 444         struct nv30_vertex_program *vp;
 445
 446         vp = CALLOC(1, sizeof(struct nv30_vertex_program));
 447         vp->pipe = *cso;
 448
 449         return (void *)vp;
 450 }
 451
 452 static void
 453 nv30_vp_state_bind(struct pipe_context *pipe, void *hwcso)
 454 {
 455         struct nv30_context *nv30 = nv30_context(pipe);
 456         struct nv30_vertex_program *vp = hwcso;
 457
 458         nv30->vertprog.current = vp;
 459         nv30->dirty |= NV30_NEW_VERTPROG;
 460 }
 461
 462 static void
 463 nv30_vp_state_delete(struct pipe_context *pipe, void *hwcso)
 464 {
 465         struct nv30_context *nv30 = nv30_context(pipe);
 466         struct nv30_vertex_program *vp = hwcso;
 467
 468         nv30_vertprog_destroy(nv30, vp);
 469         free(vp);
 470 }
 471
 472 static void *
 473 nv30_fp_state_create(struct pipe_context *pipe,
 474                      const struct pipe_shader_state *cso)
 475 {
 476         struct nv30_fragment_program *fp;
 477
 478         fp = CALLOC(1, sizeof(struct nv30_fragment_program));
 479         fp->pipe = *cso;
 480
 481         return (void *)fp;
 482 }
 483
 484 static void
 485 nv30_fp_state_bind(struct pipe_context *pipe, void *hwcso)
 486 {
 487         struct nv30_context *nv30 = nv30_context(pipe);
 488         struct nv30_fragment_program *fp = hwcso;
 489
 490         nv30->fragprog.current = fp;
 491         nv30->dirty |= NV30_NEW_FRAGPROG;
 492 }
 493
 494 static void
 495 nv30_fp_state_delete(struct pipe_context *pipe, void *hwcso)
 496 {
 497         struct nv30_context *nv30 = nv30_context(pipe);
 498         struct nv30_fragment_program *fp = hwcso;
 499
 500         nv30_fragprog_destroy(nv30, fp);
 501         free(fp);
 502 }
 503
 504 static void
 505 nv30_set_blend_color(struct pipe_context *pipe,
 506                      const struct pipe_blend_color *bcol)
 507 {
 508         struct nv30_context *nv30 = nv30_context(pipe);
 509
 510         BEGIN_RING(rankine, NV34TCL_BLEND_FUNC_COLOR, 1);
 511         OUT_RING  ((float_to_ubyte(bcol->color[3]) << 24) |
 512                    (float_to_ubyte(bcol->color[0]) << 16) |
 513                    (float_to_ubyte(bcol->color[1]) <<  8) |
 514                    (float_to_ubyte(bcol->color[2]) <<  0));
 515 }
 516
 517 static void
 518 nv30_set_clip_state(struct pipe_context *pipe,
 519                     const struct pipe_clip_state *clip)
 520 {
 521 }
 522
 523 static void
 524 nv30_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
 525                          const struct pipe_constant_buffer *buf )
 526 {
 527         struct nv30_context *nv30 = nv30_context(pipe);
 528
 529         if (shader == PIPE_SHADER_VERTEX) {
 530                 nv30->vertprog.constant_buf = buf->buffer;
 531                 nv30->dirty |= NV30_NEW_VERTPROG;
 532         } else
 533         if (shader == PIPE_SHADER_FRAGMENT) {
 534                 nv30->fragprog.constant_buf = buf->buffer;
 535                 nv30->dirty |= NV30_NEW_FRAGPROG;
 536         }
 537 }
 538
 539 static void
 540 nv30_set_framebuffer_state(struct pipe_context *pipe,
 541                            const struct pipe_framebuffer_state *fb)
 542 {
 543         struct nv30_context *nv30 = nv30_context(pipe);
 544         struct pipe_surface *rt[4], *zeta = NULL;
 545         uint32_t rt_enable, rt_format, w = 0, h = 0;
 546         int i, colour_format = 0, zeta_format = 0;
 547
 548         rt_enable = 0;
 549         for (i = 0; i < 2; i++) {
 550                 if (!fb->cbufs[i])
 551                         continue;
 552
 553                 if (colour_format) {
 554                         assert(w == fb->cbufs[i]->width);
 555                         assert(h == fb->cbufs[i]->height);
 556                         assert(colour_format == fb->cbufs[i]->format);
 557                 } else {
 558                         w = fb->cbufs[i]->width;
 559                         h = fb->cbufs[i]->height;
 560                         colour_format = fb->cbufs[i]->format;
 561                         rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
 562                         rt[i] = fb->cbufs[i];
 563                 }
 564         }
 565
 566         if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 | NV34TCL_RT_ENABLE_COLOR2 |
 567                          NV34TCL_RT_ENABLE_COLOR3))
 568                 rt_enable |= NV34TCL_RT_ENABLE_MRT;
 569
 570         if (fb->zsbuf) {
 571                 if (colour_format) {
 572                         assert(w == fb->zsbuf->width);
 573                         assert(h == fb->zsbuf->height);
 574                 } else {
 575                         w = fb->zsbuf->width;
 576                         h = fb->zsbuf->height;
 577                 }
 578
 579                 zeta_format = fb->zsbuf->format;
 580                 zeta = fb->zsbuf;
 581         }
 582
 583         rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
 584
 585         switch (colour_format) {
 586         case PIPE_FORMAT_A8R8G8B8_UNORM:
 587         case 0:
 588                 rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
 589                 break;
 590         case PIPE_FORMAT_R5G6B5_UNORM:
 591                 rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
 592                 break;
 593         default:
 594                 assert(0);
 595         }
 596
 597         switch (zeta_format) {
 598         case PIPE_FORMAT_Z16_UNORM:
 599                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
 600                 break;
 601         case PIPE_FORMAT_Z24S8_UNORM:
 602         case 0:
 603                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
 604                 break;
 605         default:
 606                 assert(0);
 607         }
 608
 609         if (rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
 610                 uint32_t pitch = rt[0]->pitch * rt[0]->cpp;
 611                 if (zeta) {
 612                         pitch |= (zeta->pitch * zeta->cpp)<<16;
 613                 } else {
 614                         pitch |= pitch<<16;
 615                 }
 616
 617                 BEGIN_RING(rankine, NV34TCL_COLOR0_PITCH, 1);
 618                 OUT_RING  ( pitch );
 619                 nv30->rt[0] = rt[0]->buffer;
 620         }
 621
 622         if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
 623                 BEGIN_RING(rankine, NV34TCL_COLOR1_PITCH, 1);
 624                 OUT_RING  (rt[1]->pitch * rt[1]->cpp);
 625                 nv30->rt[1] = rt[1]->buffer;
 626         }
 627
 628         if (zeta_format)
 629         {
 630                 nv30->zeta = zeta->buffer;
 631         }
 632
 633         nv30->rt_enable = rt_enable;
 634         BEGIN_RING(rankine, NV34TCL_RT_ENABLE, 1);
 635         OUT_RING  (rt_enable);
 636         BEGIN_RING(rankine, NV34TCL_RT_HORIZ, 3);
 637         OUT_RING  ((w << 16) | 0);
 638         OUT_RING  ((h << 16) | 0);
 639         OUT_RING  (rt_format);
 640         BEGIN_RING(rankine, NV34TCL_VIEWPORT_HORIZ, 2);
 641         OUT_RING  ((w << 16) | 0);
 642         OUT_RING  ((h << 16) | 0);
 643         BEGIN_RING(rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 644         OUT_RING  (((w - 1) << 16) | 0);
 645         OUT_RING  (((h - 1) << 16) | 0);
 646 }
 647
 648 static void
 649 nv30_set_polygon_stipple(struct pipe_context *pipe,
 650                          const struct pipe_poly_stipple *stipple)
 651 {
 652         struct nv30_context *nv30 = nv30_context(pipe);
 653
 654         BEGIN_RING(rankine, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
 655         OUT_RINGp ((uint32_t *)stipple->stipple, 32);
 656 }
 657
 658 static void
 659 nv30_set_scissor_state(struct pipe_context *pipe,
 660                        const struct pipe_scissor_state *s)
 661 {
 662         struct nv30_context *nv30 = nv30_context(pipe);
 663
 664         BEGIN_RING(rankine, NV34TCL_SCISSOR_HORIZ, 2);
 665         OUT_RING  (((s->maxx - s->minx) << 16) | s->minx);
 666         OUT_RING  (((s->maxy - s->miny) << 16) | s->miny);
 667 }
 668
 669 static void
 670 nv30_set_viewport_state(struct pipe_context *pipe,
 671                         const struct pipe_viewport_state *vpt)
 672 {
 673         struct nv30_context *nv30 = nv30_context(pipe);
 674
 675         BEGIN_RING(rankine, NV34TCL_VIEWPORT_TRANSLATE_X, 8);
 676         OUT_RINGf (vpt->translate[0]);
 677         OUT_RINGf (vpt->translate[1]);
 678         OUT_RINGf (vpt->translate[2]);
 679         OUT_RINGf (vpt->translate[3]);
 680         OUT_RINGf (vpt->scale[0]);
 681         OUT_RINGf (vpt->scale[1]);
 682         OUT_RINGf (vpt->scale[2]);
 683         OUT_RINGf (vpt->scale[3]);
 684 }
 685
 686 static void
 687 nv30_set_vertex_buffer(struct pipe_context *pipe, unsigned index,
 688                        const struct pipe_vertex_buffer *vb)
 689 {
 690         struct nv30_context *nv30 = nv30_context(pipe);
 691
 692         nv30->vtxbuf[index] = *vb;
 693
 694         nv30->dirty |= NV30_NEW_ARRAYS;
 695 }
 696
 697 static void
 698 nv30_set_vertex_element(struct pipe_context *pipe, unsigned index,
 699                         const struct pipe_vertex_element *ve)
 700 {
 701         struct nv30_context *nv30 = nv30_context(pipe);
 702
 703         nv30->vtxelt[index] = *ve;
 704
 705         nv30->dirty |= NV30_NEW_ARRAYS;
 706 }
 707
 708 void
 709 nv30_init_state_functions(struct nv30_context *nv30)
 710 {
 711         nv30->pipe.create_blend_state = nv30_blend_state_create;
 712         nv30->pipe.bind_blend_state = nv30_blend_state_bind;
 713         nv30->pipe.delete_blend_state = nv30_blend_state_delete;
 714
 715         nv30->pipe.create_sampler_state = nv30_sampler_state_create;
 716         nv30->pipe.bind_sampler_states = nv30_sampler_state_bind;
 717         nv30->pipe.delete_sampler_state = nv30_sampler_state_delete;
 718         nv30->pipe.set_sampler_textures = nv30_set_sampler_texture;
 719
 720         nv30->pipe.create_rasterizer_state = nv30_rasterizer_state_create;
 721         nv30->pipe.bind_rasterizer_state = nv30_rasterizer_state_bind;
 722         nv30->pipe.delete_rasterizer_state = nv30_rasterizer_state_delete;
 723
 724         nv30->pipe.create_depth_stencil_alpha_state =
 725                 nv30_depth_stencil_alpha_state_create;
 726         nv30->pipe.bind_depth_stencil_alpha_state =
 727                 nv30_depth_stencil_alpha_state_bind;
 728         nv30->pipe.delete_depth_stencil_alpha_state =
 729                 nv30_depth_stencil_alpha_state_delete;
 730
 731         nv30->pipe.create_vs_state = nv30_vp_state_create;
 732         nv30->pipe.bind_vs_state = nv30_vp_state_bind;
 733         nv30->pipe.delete_vs_state = nv30_vp_state_delete;
 734
 735         nv30->pipe.create_fs_state = nv30_fp_state_create;
 736         nv30->pipe.bind_fs_state = nv30_fp_state_bind;
 737         nv30->pipe.delete_fs_state = nv30_fp_state_delete;
 738
 739         nv30->pipe.set_blend_color = nv30_set_blend_color;
 740         nv30->pipe.set_clip_state = nv30_set_clip_state;
 741         nv30->pipe.set_constant_buffer = nv30_set_constant_buffer;
 742         nv30->pipe.set_framebuffer_state = nv30_set_framebuffer_state;
 743         nv30->pipe.set_polygon_stipple = nv30_set_polygon_stipple;
 744         nv30->pipe.set_scissor_state = nv30_set_scissor_state;
 745         nv30->pipe.set_viewport_state = nv30_set_viewport_state;
 746
 747         nv30->pipe.set_vertex_buffer = nv30_set_vertex_buffer;
 748         nv30->pipe.set_vertex_element = nv30_set_vertex_element;
 749 }
 750