1 #include "pipe/p_state.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_util.h"
5 #include "nv30_context.h"
6 #include "nv30_state.h"
9 nv30_blend_state_create(struct pipe_context
*pipe
,
10 const struct pipe_blend_state
*cso
)
12 struct nv30_blend_state
*cb
;
14 cb
= malloc(sizeof(struct nv30_blend_state
));
16 cb
->b_enable
= cso
->blend_enable
? 1 : 0;
17 cb
->b_srcfunc
= ((nvgl_blend_func(cso
->alpha_src_factor
)<<16) |
18 (nvgl_blend_func(cso
->rgb_src_factor
)));
19 cb
->b_dstfunc
= ((nvgl_blend_func(cso
->alpha_dst_factor
)<<16) |
20 (nvgl_blend_func(cso
->rgb_dst_factor
)));
21 cb
->b_eqn
= ((nvgl_blend_eqn(cso
->alpha_func
) << 16) |
22 (nvgl_blend_eqn(cso
->rgb_func
)));
24 cb
->l_enable
= cso
->logicop_enable
? 1 : 0;
25 cb
->l_op
= nvgl_logicop_func(cso
->logicop_func
);
27 cb
->c_mask
= (((cso
->colormask
& PIPE_MASK_A
) ? (0x01<<24) : 0) |
28 ((cso
->colormask
& PIPE_MASK_R
) ? (0x01<<16) : 0) |
29 ((cso
->colormask
& PIPE_MASK_G
) ? (0x01<< 8) : 0) |
30 ((cso
->colormask
& PIPE_MASK_B
) ? (0x01<< 0) : 0));
32 cb
->d_enable
= cso
->dither
? 1 : 0;
38 nv30_blend_state_bind(struct pipe_context
*pipe
, void *hwcso
)
40 struct nv30_context
*nv30
= nv30_context(pipe
);
41 struct nv30_blend_state
*cb
= hwcso
;
47 BEGIN_RING(rankine
, NV34TCL_DITHER_ENABLE
, 1);
48 OUT_RING (cb
->d_enable
);
50 BEGIN_RING(rankine
, NV34TCL_BLEND_FUNC_ENABLE
, 3);
51 OUT_RING (cb
->b_enable
);
52 OUT_RING (cb
->b_srcfunc
);
53 OUT_RING (cb
->b_dstfunc
);
54 BEGIN_RING(rankine
, NV34TCL_BLEND_EQUATION
, 1);
57 BEGIN_RING(rankine
, NV34TCL_COLOR_MASK
, 1);
58 OUT_RING (cb
->c_mask
);
60 BEGIN_RING(rankine
, NV34TCL_COLOR_LOGIC_OP_ENABLE
, 2);
61 OUT_RING (cb
->l_enable
);
66 nv30_blend_state_delete(struct pipe_context
*pipe
, void *hwcso
)
72 static INLINE
unsigned
73 wrap_mode(unsigned wrap
) {
77 case PIPE_TEX_WRAP_REPEAT
:
78 ret
= NV34TCL_TX_WRAP_S_REPEAT
;
80 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
81 ret
= NV34TCL_TX_WRAP_S_MIRRORED_REPEAT
;
83 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
84 ret
= NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE
;
86 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
87 ret
= NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER
;
89 case PIPE_TEX_WRAP_CLAMP
:
90 ret
= NV34TCL_TX_WRAP_S_CLAMP
;
92 /* case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
93 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
95 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
96 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
98 case PIPE_TEX_WRAP_MIRROR_CLAMP:
99 ret = NV34TCL_TX_WRAP_S_MIRROR_CLAMP;
102 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap
);
103 ret
= NV34TCL_TX_WRAP_S_REPEAT
;
107 return ret
>> NV34TCL_TX_WRAP_S_SHIFT
;
111 nv30_sampler_state_create(struct pipe_context
*pipe
,
112 const struct pipe_sampler_state
*cso
)
114 struct nv30_sampler_state
*ps
;
117 ps
= malloc(sizeof(struct nv30_sampler_state
));
120 if (!cso
->normalized_coords
)
121 ps
->fmt
|= NV34TCL_TX_FORMAT_RECT
;
123 ps
->wrap
= ((wrap_mode(cso
->wrap_s
) << NV34TCL_TX_WRAP_S_SHIFT
) |
124 (wrap_mode(cso
->wrap_t
) << NV34TCL_TX_WRAP_T_SHIFT
) |
125 (wrap_mode(cso
->wrap_r
) << NV34TCL_TX_WRAP_R_SHIFT
));
128 if (cso
->max_anisotropy
>= 2.0) {
129 /* no idea, binary driver sets it, works without it.. meh.. */
130 ps
->wrap
|= (1 << 5);
132 /* if (cso->max_anisotropy >= 16.0) {
133 ps->en |= NV34TCL_TX_ENABLE_ANISO_16X;
135 if (cso->max_anisotropy >= 12.0) {
136 ps->en |= NV34TCL_TX_ENABLE_ANISO_12X;
138 if (cso->max_anisotropy >= 10.0) {
139 ps->en |= NV34TCL_TX_ENABLE_ANISO_10X;
141 if (cso->max_anisotropy >= 8.0) {
142 ps->en |= NV34TCL_TX_ENABLE_ANISO_8X;
144 if (cso->max_anisotropy >= 6.0) {
145 ps->en |= NV34TCL_TX_ENABLE_ANISO_6X;
147 if (cso->max_anisotropy >= 4.0) {
148 ps->en |= NV34TCL_TX_ENABLE_ANISO_4X;
150 ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
154 switch (cso
->mag_img_filter
) {
155 case PIPE_TEX_FILTER_LINEAR
:
156 filter
|= NV34TCL_TX_FILTER_MAGNIFY_LINEAR
;
158 case PIPE_TEX_FILTER_NEAREST
:
160 filter
|= NV34TCL_TX_FILTER_MAGNIFY_NEAREST
;
164 switch (cso
->min_img_filter
) {
165 case PIPE_TEX_FILTER_LINEAR
:
166 switch (cso
->min_mip_filter
) {
167 case PIPE_TEX_MIPFILTER_NEAREST
:
168 filter
|= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST
;
170 case PIPE_TEX_MIPFILTER_LINEAR
:
171 filter
|= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR
;
173 case PIPE_TEX_MIPFILTER_NONE
:
175 filter
|= NV34TCL_TX_FILTER_MINIFY_LINEAR
;
179 case PIPE_TEX_FILTER_NEAREST
:
181 switch (cso
->min_mip_filter
) {
182 case PIPE_TEX_MIPFILTER_NEAREST
:
183 filter
|= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST
;
185 case PIPE_TEX_MIPFILTER_LINEAR
:
186 filter
|= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR
;
188 case PIPE_TEX_MIPFILTER_NONE
:
190 filter
|= NV34TCL_TX_FILTER_MINIFY_NEAREST
;
198 /* if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
199 switch (cso->compare_func) {
200 case PIPE_FUNC_NEVER:
201 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NEVER;
203 case PIPE_FUNC_GREATER:
204 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GREATER;
206 case PIPE_FUNC_EQUAL:
207 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_EQUAL;
209 case PIPE_FUNC_GEQUAL:
210 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GEQUAL;
213 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LESS;
215 case PIPE_FUNC_NOTEQUAL:
216 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NOTEQUAL;
218 case PIPE_FUNC_LEQUAL:
219 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LEQUAL;
221 case PIPE_FUNC_ALWAYS:
222 ps->wrap |= NV34TCL_TX_WRAP_RCOMP_ALWAYS;
229 ps
->bcol
= ((float_to_ubyte(cso
->border_color
[3]) << 24) |
230 (float_to_ubyte(cso
->border_color
[0]) << 16) |
231 (float_to_ubyte(cso
->border_color
[1]) << 8) |
232 (float_to_ubyte(cso
->border_color
[2]) << 0));
238 nv30_sampler_state_bind(struct pipe_context
*pipe
, unsigned nr
, void **sampler
)
240 struct nv30_context
*nv30
= nv30_context(pipe
);
247 for (unit
= 0; unit
< nr
; unit
++) {
248 nv30
->tex_sampler
[unit
] = sampler
[unit
];
249 nv30
->dirty_samplers
|= (1 << unit
);
254 nv30_sampler_state_delete(struct pipe_context
*pipe
, void *hwcso
)
260 nv30_set_sampler_texture(struct pipe_context
*pipe
, unsigned nr
,
261 struct pipe_texture
**miptree
)
263 struct nv30_context
*nv30
= nv30_context(pipe
);
266 for (unit
= 0; unit
< nr
; unit
++) {
267 nv30
->tex_miptree
[unit
] = (struct nv30_miptree
*)miptree
[unit
];
268 nv30
->dirty_samplers
|= (1 << unit
);
273 nv30_rasterizer_state_create(struct pipe_context
*pipe
,
274 const struct pipe_rasterizer_state
*cso
)
276 struct nv30_rasterizer_state
*rs
;
281 * offset_cw/ccw -nohw
285 * offset_units / offset_scale
287 rs
= malloc(sizeof(struct nv30_rasterizer_state
));
289 rs
->shade_model
= cso
->flatshade
? 0x1d00 : 0x1d01;
291 rs
->line_width
= (unsigned char)(cso
->line_width
* 8.0) & 0xff;
292 rs
->line_smooth_en
= cso
->line_smooth
? 1 : 0;
293 rs
->line_stipple_en
= cso
->line_stipple_enable
? 1 : 0;
294 rs
->line_stipple
= (cso
->line_stipple_pattern
<< 16) |
295 cso
->line_stipple_factor
;
297 rs
->point_size
= *(uint32_t*)&cso
->point_size
;
299 rs
->poly_smooth_en
= cso
->poly_smooth
? 1 : 0;
300 rs
->poly_stipple_en
= cso
->poly_stipple_enable
? 1 : 0;
302 if (cso
->front_winding
== PIPE_WINDING_CCW
) {
303 rs
->front_face
= NV34TCL_FRONT_FACE_CCW
;
304 rs
->poly_mode_front
= nvgl_polygon_mode(cso
->fill_ccw
);
305 rs
->poly_mode_back
= nvgl_polygon_mode(cso
->fill_cw
);
307 rs
->front_face
= NV34TCL_FRONT_FACE_CW
;
308 rs
->poly_mode_front
= nvgl_polygon_mode(cso
->fill_cw
);
309 rs
->poly_mode_back
= nvgl_polygon_mode(cso
->fill_ccw
);
312 switch (cso
->cull_mode
) {
313 case PIPE_WINDING_CCW
:
314 rs
->cull_face_en
= 1;
315 if (cso
->front_winding
== PIPE_WINDING_CCW
)
316 rs
->cull_face
= NV34TCL_CULL_FACE_FRONT
;
318 rs
->cull_face
= NV34TCL_CULL_FACE_BACK
;
320 case PIPE_WINDING_CW
:
321 rs
->cull_face_en
= 1;
322 if (cso
->front_winding
== PIPE_WINDING_CW
)
323 rs
->cull_face
= NV34TCL_CULL_FACE_FRONT
;
325 rs
->cull_face
= NV34TCL_CULL_FACE_BACK
;
327 case PIPE_WINDING_BOTH
:
328 rs
->cull_face_en
= 1;
329 rs
->cull_face
= NV34TCL_CULL_FACE_FRONT_AND_BACK
;
331 case PIPE_WINDING_NONE
:
333 rs
->cull_face_en
= 0;
338 if (cso
->point_sprite
) {
339 rs
->point_sprite
= (1 << 0);
340 for (i
= 0; i
< 8; i
++) {
341 if (cso
->sprite_coord_mode
[i
] != PIPE_SPRITE_COORD_NONE
)
342 rs
->point_sprite
|= (1 << (8 + i
));
345 rs
->point_sprite
= 0;
352 nv30_rasterizer_state_bind(struct pipe_context
*pipe
, void *hwcso
)
354 struct nv30_context
*nv30
= nv30_context(pipe
);
355 struct nv30_rasterizer_state
*rs
= hwcso
;
361 BEGIN_RING(rankine
, NV34TCL_SHADE_MODEL
, 1);
362 OUT_RING (rs
->shade_model
);
364 BEGIN_RING(rankine
, NV34TCL_LINE_WIDTH
, 2);
365 OUT_RING (rs
->line_width
);
366 OUT_RING (rs
->line_smooth_en
);
367 BEGIN_RING(rankine
, NV34TCL_LINE_STIPPLE_ENABLE
, 2);
368 OUT_RING (rs
->line_stipple_en
);
369 OUT_RING (rs
->line_stipple
);
371 BEGIN_RING(rankine
, NV34TCL_POINT_SIZE
, 1);
372 OUT_RING (rs
->point_size
);
374 BEGIN_RING(rankine
, NV34TCL_POLYGON_MODE_FRONT
, 6);
375 OUT_RING (rs
->poly_mode_front
);
376 OUT_RING (rs
->poly_mode_back
);
377 OUT_RING (rs
->cull_face
);
378 OUT_RING (rs
->front_face
);
379 OUT_RING (rs
->poly_smooth_en
);
380 OUT_RING (rs
->cull_face_en
);
382 BEGIN_RING(rankine
, NV34TCL_POLYGON_STIPPLE_ENABLE
, 1);
383 OUT_RING (rs
->poly_stipple_en
);
385 BEGIN_RING(rankine
, NV34TCL_POINT_SPRITE
, 1);
386 OUT_RING (rs
->point_sprite
);
390 nv30_rasterizer_state_delete(struct pipe_context
*pipe
, void *hwcso
)
396 nv30_translate_stencil(const struct pipe_depth_stencil_alpha_state
*cso
,
397 unsigned idx
, struct nv30_stencil_push
*hw
)
399 hw
->enable
= cso
->stencil
[idx
].enabled
? 1 : 0;
400 hw
->wmask
= cso
->stencil
[idx
].write_mask
;
401 hw
->func
= nvgl_comparison_op(cso
->stencil
[idx
].func
);
402 hw
->ref
= cso
->stencil
[idx
].ref_value
;
403 hw
->vmask
= cso
->stencil
[idx
].value_mask
;
404 hw
->fail
= nvgl_stencil_op(cso
->stencil
[idx
].fail_op
);
405 hw
->zfail
= nvgl_stencil_op(cso
->stencil
[idx
].zfail_op
);
406 hw
->zpass
= nvgl_stencil_op(cso
->stencil
[idx
].zpass_op
);
410 nv30_depth_stencil_alpha_state_create(struct pipe_context
*pipe
,
411 const struct pipe_depth_stencil_alpha_state
*cso
)
413 struct nv30_depth_stencil_alpha_state
*hw
;
415 hw
= malloc(sizeof(struct nv30_depth_stencil_alpha_state
));
417 hw
->depth
.func
= nvgl_comparison_op(cso
->depth
.func
);
418 hw
->depth
.write_enable
= cso
->depth
.writemask
? 1 : 0;
419 hw
->depth
.test_enable
= cso
->depth
.enabled
? 1 : 0;
421 nv30_translate_stencil(cso
, 0, &hw
->stencil
.front
);
422 nv30_translate_stencil(cso
, 1, &hw
->stencil
.back
);
424 hw
->alpha
.enabled
= cso
->alpha
.enabled
? 1 : 0;
425 hw
->alpha
.func
= nvgl_comparison_op(cso
->alpha
.func
);
426 hw
->alpha
.ref
= float_to_ubyte(cso
->alpha
.ref
);
432 nv30_depth_stencil_alpha_state_bind(struct pipe_context
*pipe
, void *hwcso
)
434 struct nv30_context
*nv30
= nv30_context(pipe
);
435 struct nv30_depth_stencil_alpha_state
*hw
= hwcso
;
441 BEGIN_RING(rankine
, NV34TCL_DEPTH_FUNC
, 3);
442 OUT_RINGp ((uint32_t *)&hw
->depth
, 3);
443 BEGIN_RING(rankine
, NV34TCL_STENCIL_BACK_ENABLE
, 16);
444 OUT_RINGp ((uint32_t *)&hw
->stencil
.back
, 8);
445 OUT_RINGp ((uint32_t *)&hw
->stencil
.front
, 8);
446 BEGIN_RING(rankine
, NV34TCL_ALPHA_FUNC_ENABLE
, 3);
447 OUT_RINGp ((uint32_t *)&hw
->alpha
.enabled
, 3);
451 nv30_depth_stencil_alpha_state_delete(struct pipe_context
*pipe
, void *hwcso
)
457 nv30_vp_state_create(struct pipe_context
*pipe
,
458 const struct pipe_shader_state
*cso
)
460 struct nv30_vertex_program
*vp
;
462 vp
= CALLOC(1, sizeof(struct nv30_vertex_program
));
469 nv30_vp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
471 struct nv30_context
*nv30
= nv30_context(pipe
);
472 struct nv30_vertex_program
*vp
= hwcso
;
478 nv30
->vertprog
.current
= vp
;
479 nv30
->dirty
|= NV30_NEW_VERTPROG
;
483 nv30_vp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
485 struct nv30_context
*nv30
= nv30_context(pipe
);
486 struct nv30_vertex_program
*vp
= hwcso
;
488 nv30_vertprog_destroy(nv30
, vp
);
493 nv30_fp_state_create(struct pipe_context
*pipe
,
494 const struct pipe_shader_state
*cso
)
496 struct nv30_fragment_program
*fp
;
498 fp
= CALLOC(1, sizeof(struct nv30_fragment_program
));
505 nv30_fp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
507 struct nv30_context
*nv30
= nv30_context(pipe
);
508 struct nv30_fragment_program
*fp
= hwcso
;
514 nv30
->fragprog
.current
= fp
;
515 nv30
->dirty
|= NV30_NEW_FRAGPROG
;
519 nv30_fp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
521 struct nv30_context
*nv30
= nv30_context(pipe
);
522 struct nv30_fragment_program
*fp
= hwcso
;
524 nv30_fragprog_destroy(nv30
, fp
);
529 nv30_set_blend_color(struct pipe_context
*pipe
,
530 const struct pipe_blend_color
*bcol
)
532 struct nv30_context
*nv30
= nv30_context(pipe
);
534 BEGIN_RING(rankine
, NV34TCL_BLEND_COLOR
, 1);
535 OUT_RING ((float_to_ubyte(bcol
->color
[3]) << 24) |
536 (float_to_ubyte(bcol
->color
[0]) << 16) |
537 (float_to_ubyte(bcol
->color
[1]) << 8) |
538 (float_to_ubyte(bcol
->color
[2]) << 0));
542 nv30_set_clip_state(struct pipe_context
*pipe
,
543 const struct pipe_clip_state
*clip
)
548 nv30_set_constant_buffer(struct pipe_context
*pipe
, uint shader
, uint index
,
549 const struct pipe_constant_buffer
*buf
)
551 struct nv30_context
*nv30
= nv30_context(pipe
);
553 if (shader
== PIPE_SHADER_VERTEX
) {
554 nv30
->vertprog
.constant_buf
= buf
->buffer
;
555 nv30
->dirty
|= NV30_NEW_VERTPROG
;
557 if (shader
== PIPE_SHADER_FRAGMENT
) {
558 nv30
->fragprog
.constant_buf
= buf
->buffer
;
559 nv30
->dirty
|= NV30_NEW_FRAGPROG
;
564 nv30_set_framebuffer_state(struct pipe_context
*pipe
,
565 const struct pipe_framebuffer_state
*fb
)
567 struct nv30_context
*nv30
= nv30_context(pipe
);
568 struct pipe_surface
*rt
[2], *zeta
= NULL
;
569 uint32_t rt_enable
, rt_format
, w
= 0, h
= 0;
570 int i
, colour_format
= 0, zeta_format
= 0;
573 for (i
= 0; i
< 2; i
++) {
578 assert(w
== fb
->cbufs
[i
]->width
);
579 assert(h
== fb
->cbufs
[i
]->height
);
580 assert(colour_format
== fb
->cbufs
[i
]->format
);
582 w
= fb
->cbufs
[i
]->width
;
583 h
= fb
->cbufs
[i
]->height
;
584 colour_format
= fb
->cbufs
[i
]->format
;
585 rt_enable
|= (NV34TCL_RT_ENABLE_COLOR0
<< i
);
586 rt
[i
] = fb
->cbufs
[i
];
590 if (rt_enable
& (NV34TCL_RT_ENABLE_COLOR1
| NV34TCL_RT_ENABLE_COLOR2
|
591 NV34TCL_RT_ENABLE_COLOR3
))
592 rt_enable
|= NV34TCL_RT_ENABLE_MRT
;
596 assert(w
== fb
->zsbuf
->width
);
597 assert(h
== fb
->zsbuf
->height
);
599 w
= fb
->zsbuf
->width
;
600 h
= fb
->zsbuf
->height
;
603 zeta_format
= fb
->zsbuf
->format
;
607 rt_format
= NV34TCL_RT_FORMAT_TYPE_LINEAR
;
609 switch (colour_format
) {
610 case PIPE_FORMAT_A8R8G8B8_UNORM
:
612 rt_format
|= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8
;
614 case PIPE_FORMAT_R5G6B5_UNORM
:
615 rt_format
|= NV34TCL_RT_FORMAT_COLOR_R5G6B5
;
621 switch (zeta_format
) {
622 case PIPE_FORMAT_Z16_UNORM
:
623 rt_format
|= NV34TCL_RT_FORMAT_ZETA_Z16
;
625 case PIPE_FORMAT_Z24S8_UNORM
:
627 rt_format
|= NV34TCL_RT_FORMAT_ZETA_Z24S8
;
633 if (rt_enable
& NV34TCL_RT_ENABLE_COLOR0
) {
634 uint32_t pitch
= rt
[0]->stride
;
636 pitch
|= (zeta
->stride
<< 16);
638 pitch
|= (pitch
<< 16);
641 BEGIN_RING(rankine
, NV34TCL_COLOR0_PITCH
, 1);
643 nv30
->rt
[0] = rt
[0]->buffer
;
646 if (rt_enable
& NV34TCL_RT_ENABLE_COLOR1
) {
647 BEGIN_RING(rankine
, NV34TCL_COLOR1_PITCH
, 1);
648 OUT_RING (rt
[1]->stride
);
649 nv30
->rt
[1] = rt
[1]->buffer
;
654 nv30
->zeta
= zeta
->buffer
;
657 nv30
->rt_enable
= rt_enable
;
658 BEGIN_RING(rankine
, NV34TCL_RT_ENABLE
, 1);
659 OUT_RING (rt_enable
);
660 BEGIN_RING(rankine
, NV34TCL_RT_HORIZ
, 3);
661 OUT_RING ((w
<< 16) | 0);
662 OUT_RING ((h
<< 16) | 0);
663 OUT_RING (rt_format
);
664 BEGIN_RING(rankine
, NV34TCL_VIEWPORT_HORIZ
, 2);
665 OUT_RING ((w
<< 16) | 0);
666 OUT_RING ((h
<< 16) | 0);
667 BEGIN_RING(rankine
, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
668 OUT_RING (((w
- 1) << 16) | 0);
669 OUT_RING (((h
- 1) << 16) | 0);
670 BEGIN_RING(rankine
, NV34TCL_VIEWPORT_TX_ORIGIN
, 1);
675 nv30_set_polygon_stipple(struct pipe_context
*pipe
,
676 const struct pipe_poly_stipple
*stipple
)
678 struct nv30_context
*nv30
= nv30_context(pipe
);
680 BEGIN_RING(rankine
, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
681 OUT_RINGp ((uint32_t *)stipple
->stipple
, 32);
685 nv30_set_scissor_state(struct pipe_context
*pipe
,
686 const struct pipe_scissor_state
*s
)
688 struct nv30_context
*nv30
= nv30_context(pipe
);
690 BEGIN_RING(rankine
, NV34TCL_SCISSOR_HORIZ
, 2);
691 OUT_RING (((s
->maxx
- s
->minx
) << 16) | s
->minx
);
692 OUT_RING (((s
->maxy
- s
->miny
) << 16) | s
->miny
);
696 nv30_set_viewport_state(struct pipe_context
*pipe
,
697 const struct pipe_viewport_state
*vpt
)
699 struct nv30_context
*nv30
= nv30_context(pipe
);
701 BEGIN_RING(rankine
, NV34TCL_VIEWPORT_TRANSLATE_X
, 8);
702 OUT_RINGf (vpt
->translate
[0]);
703 OUT_RINGf (vpt
->translate
[1]);
704 OUT_RINGf (vpt
->translate
[2]);
705 OUT_RINGf (vpt
->translate
[3]);
706 OUT_RINGf (vpt
->scale
[0]);
707 OUT_RINGf (vpt
->scale
[1]);
708 OUT_RINGf (vpt
->scale
[2]);
709 OUT_RINGf (vpt
->scale
[3]);
713 nv30_set_vertex_buffers(struct pipe_context
*pipe
, unsigned count
,
714 const struct pipe_vertex_buffer
*vb
)
716 struct nv30_context
*nv30
= nv30_context(pipe
);
718 memcpy(nv30
->vtxbuf
, vb
, sizeof(*vb
) * count
);
719 nv30
->dirty
|= NV30_NEW_ARRAYS
;
723 nv30_set_vertex_elements(struct pipe_context
*pipe
, unsigned count
,
724 const struct pipe_vertex_element
*ve
)
726 struct nv30_context
*nv30
= nv30_context(pipe
);
728 memcpy(nv30
->vtxelt
, ve
, sizeof(*ve
) * count
);
729 nv30
->dirty
|= NV30_NEW_ARRAYS
;
733 nv30_init_state_functions(struct nv30_context
*nv30
)
735 nv30
->pipe
.create_blend_state
= nv30_blend_state_create
;
736 nv30
->pipe
.bind_blend_state
= nv30_blend_state_bind
;
737 nv30
->pipe
.delete_blend_state
= nv30_blend_state_delete
;
739 nv30
->pipe
.create_sampler_state
= nv30_sampler_state_create
;
740 nv30
->pipe
.bind_sampler_states
= nv30_sampler_state_bind
;
741 nv30
->pipe
.delete_sampler_state
= nv30_sampler_state_delete
;
742 nv30
->pipe
.set_sampler_textures
= nv30_set_sampler_texture
;
744 nv30
->pipe
.create_rasterizer_state
= nv30_rasterizer_state_create
;
745 nv30
->pipe
.bind_rasterizer_state
= nv30_rasterizer_state_bind
;
746 nv30
->pipe
.delete_rasterizer_state
= nv30_rasterizer_state_delete
;
748 nv30
->pipe
.create_depth_stencil_alpha_state
=
749 nv30_depth_stencil_alpha_state_create
;
750 nv30
->pipe
.bind_depth_stencil_alpha_state
=
751 nv30_depth_stencil_alpha_state_bind
;
752 nv30
->pipe
.delete_depth_stencil_alpha_state
=
753 nv30_depth_stencil_alpha_state_delete
;
755 nv30
->pipe
.create_vs_state
= nv30_vp_state_create
;
756 nv30
->pipe
.bind_vs_state
= nv30_vp_state_bind
;
757 nv30
->pipe
.delete_vs_state
= nv30_vp_state_delete
;
759 nv30
->pipe
.create_fs_state
= nv30_fp_state_create
;
760 nv30
->pipe
.bind_fs_state
= nv30_fp_state_bind
;
761 nv30
->pipe
.delete_fs_state
= nv30_fp_state_delete
;
763 nv30
->pipe
.set_blend_color
= nv30_set_blend_color
;
764 nv30
->pipe
.set_clip_state
= nv30_set_clip_state
;
765 nv30
->pipe
.set_constant_buffer
= nv30_set_constant_buffer
;
766 nv30
->pipe
.set_framebuffer_state
= nv30_set_framebuffer_state
;
767 nv30
->pipe
.set_polygon_stipple
= nv30_set_polygon_stipple
;
768 nv30
->pipe
.set_scissor_state
= nv30_set_scissor_state
;
769 nv30
->pipe
.set_viewport_state
= nv30_set_viewport_state
;
771 nv30
->pipe
.set_vertex_buffers
= nv30_set_vertex_buffers
;
772 nv30
->pipe
.set_vertex_elements
= nv30_set_vertex_elements
;