src/gallium/drivers/nv30/nv30_state_emit.c

   1 #include "nv30_context.h"
   2 #include "nv30_state.h"
   3
   4 void
   5 nv30_emit_hw_state(struct nv30_context *nv30)
   6 {
   7         int i;
   8
   9         if (nv30->dirty & NV30_NEW_FRAGPROG) {
  10                 nv30_fragprog_bind(nv30, nv30->fragprog.current);
  11                 /*XXX: clear NV30_NEW_FRAGPROG if no new program uploaded */
  12         }
  13
  14         if (nv30->dirty_samplers || (nv30->dirty & NV30_NEW_FRAGPROG)) {
  15                 nv30_fragtex_bind(nv30);
  16 /*
  17                 BEGIN_RING(rankine, NV34TCL_TX_CACHE_CTL, 1);
  18                 OUT_RING  (2);
  19                 BEGIN_RING(rankine, NV34TCL_TX_CACHE_CTL, 1);
  20                 OUT_RING  (1);*/
  21                 nv30->dirty &= ~NV30_NEW_FRAGPROG;
  22         }
  23
  24         if (nv30->dirty & NV30_NEW_VERTPROG) {
  25                 nv30_vertprog_bind(nv30, nv30->vertprog.current);
  26                 nv30->dirty &= ~NV30_NEW_VERTPROG;
  27         }
  28
  29         nv30->dirty_samplers = 0;
  30
  31         /* Emit relocs for every referenced buffer.
  32          * This is to ensure the bufmgr has an accurate idea of how
  33          * the buffer is used.  This isn't very efficient, but we don't
  34          * seem to take a significant performance hit.  Will be improved
  35          * at some point.  Vertex arrays are emitted by nv30_vbo.c
  36          */
  37
  38         /* Render targets */
  39         if (nv30->rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
  40                 BEGIN_RING(rankine, NV34TCL_DMA_COLOR0, 1);
  41                 OUT_RELOCo(nv30->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  42                 BEGIN_RING(rankine, NV34TCL_COLOR0_OFFSET, 1);
  43                 OUT_RELOCl(nv30->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  44         }
  45
  46         if (nv30->rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
  47                 BEGIN_RING(rankine, NV34TCL_DMA_COLOR1, 1);
  48                 OUT_RELOCo(nv30->rt[1], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  49                 BEGIN_RING(rankine, NV34TCL_COLOR1_OFFSET, 1);
  50                 OUT_RELOCl(nv30->rt[1], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  51         }
  52
  53         if (nv30->zeta) {
  54                 BEGIN_RING(rankine, NV34TCL_DMA_ZETA, 1);
  55                 OUT_RELOCo(nv30->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  56                 BEGIN_RING(rankine, NV34TCL_ZETA_OFFSET, 1);
  57                 OUT_RELOCl(nv30->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  58                 /* XXX allocate LMA */
  59 /*              BEGIN_RING(rankine, NV34TCL_LMA_DEPTH_OFFSET, 1);
  60                 OUT_RING(0);*/
  61         }
  62
  63         /* Texture images */
  64         for (i = 0; i < 16; i++) {
  65                 if (!(nv30->fp_samplers & (1 << i)))
  66                         continue;
  67                 BEGIN_RING(rankine, NV34TCL_TX_OFFSET(i), 2);
  68                 OUT_RELOCl(nv30->tex[i].buffer, 0, NOUVEAU_BO_VRAM |
  69                            NOUVEAU_BO_GART | NOUVEAU_BO_RD);
  70                 OUT_RELOCd(nv30->tex[i].buffer, nv30->tex[i].format,
  71                            NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
  72                            NOUVEAU_BO_OR, NV34TCL_TX_FORMAT_DMA0,
  73                            NV34TCL_TX_FORMAT_DMA1);
  74         }
  75
  76         /* Fragment program */
  77         BEGIN_RING(rankine, NV34TCL_FP_ACTIVE_PROGRAM, 1);
  78         OUT_RELOC (nv30->fragprog.active->buffer, 0, NOUVEAU_BO_VRAM |
  79                    NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
  80                    NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
  81                    NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
  82 }
  83