src/gallium/drivers/nv30/nv30_state_fb.c

   1 #include "nv30_context.h"
   2 #include "nouveau/nouveau_util.h"
   3
   4 static boolean
   5 nv30_state_framebuffer_validate(struct nv30_context *nv30)
   6 {
   7         struct pipe_framebuffer_state *fb = &nv30->framebuffer;
   8         struct pipe_surface *rt[2], *zeta = NULL;
   9         uint32_t rt_enable, rt_format;
  10         int i, colour_format = 0, zeta_format = 0;
  11         struct nouveau_stateobj *so = so_new(64, 10);
  12         unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
  13         unsigned w = fb->width;
  14         unsigned h = fb->height;
  15
  16         rt_enable = 0;
  17         for (i = 0; i < fb->num_cbufs; i++) {
  18                 if (colour_format) {
  19                         assert(colour_format == fb->cbufs[i]->format);
  20                 } else {
  21                         colour_format = fb->cbufs[i]->format;
  22                         rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
  23                         rt[i] = fb->cbufs[i];
  24                 }
  25         }
  26
  27         if (rt_enable & NV34TCL_RT_ENABLE_COLOR1)
  28                 rt_enable |= NV34TCL_RT_ENABLE_MRT;
  29
  30         if (fb->zsbuf) {
  31                 zeta_format = fb->zsbuf->format;
  32                 zeta = fb->zsbuf;
  33         }
  34
  35         if (!(rt[0]->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
  36                 assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
  37                 for (i = 1; i < fb->num_cbufs; i++)
  38                         assert(!(rt[i]->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR));
  39
  40                 /* FIXME: NV34TCL_RT_FORMAT_LOG2_[WIDTH/HEIGHT] */
  41                 rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
  42                 log2i(fb->width) << 16 /*NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT*/ |
  43                 log2i(fb->height) << 24 /*NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT*/;
  44         }
  45         else
  46                 rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
  47
  48         switch (colour_format) {
  49         case PIPE_FORMAT_A8R8G8B8_UNORM:
  50         case 0:
  51                 rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
  52                 break;
  53         case PIPE_FORMAT_R5G6B5_UNORM:
  54                 rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
  55                 break;
  56         default:
  57                 assert(0);
  58         }
  59
  60         switch (zeta_format) {
  61         case PIPE_FORMAT_Z16_UNORM:
  62                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
  63                 break;
  64         case PIPE_FORMAT_Z24S8_UNORM:
  65         case 0:
  66                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
  67                 break;
  68         default:
  69                 assert(0);
  70         }
  71
  72         if (rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
  73                 uint32_t pitch = rt[0]->stride;
  74                 if (zeta) {
  75                         pitch |= (zeta->stride << 16);
  76                 } else {
  77                         pitch |= (pitch << 16);
  78                 }
  79
  80                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR0, 1);
  81                 so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  82                           nv30->nvws->channel->vram->handle,
  83                           nv30->nvws->channel->gart->handle);
  84                 so_method(so, nv30->screen->rankine, NV34TCL_COLOR0_PITCH, 2);
  85                 so_data  (so, pitch);
  86                 so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags |
  87                           NOUVEAU_BO_LOW, 0, 0);
  88         }
  89
  90         if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
  91                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR1, 1);
  92                 so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  93                           nv30->nvws->channel->vram->handle,
  94                           nv30->nvws->channel->gart->handle);
  95                 so_method(so, nv30->screen->rankine, NV34TCL_COLOR1_OFFSET, 2);
  96                 so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags |
  97                           NOUVEAU_BO_LOW, 0, 0);
  98                 so_data  (so, rt[1]->stride);
  99         }
 100
 101         if (zeta_format) {
 102                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_ZETA, 1);
 103                 so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR,
 104                           nv30->nvws->channel->vram->handle,
 105                           nv30->nvws->channel->gart->handle);
 106                 so_method(so, nv30->screen->rankine, NV34TCL_ZETA_OFFSET, 1);
 107                 so_reloc (so, zeta->buffer, zeta->offset, rt_flags |
 108                           NOUVEAU_BO_LOW, 0, 0);
 109                 /* TODO: allocate LMA depth buffer */
 110         }
 111
 112         so_method(so, nv30->screen->rankine, NV34TCL_RT_ENABLE, 1);
 113         so_data  (so, rt_enable);
 114         so_method(so, nv30->screen->rankine, NV34TCL_RT_HORIZ, 3);
 115         so_data  (so, (w << 16) | 0);
 116         so_data  (so, (h << 16) | 0);
 117         so_data  (so, rt_format);
 118         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_HORIZ, 2);
 119         so_data  (so, (w << 16) | 0);
 120         so_data  (so, (h << 16) | 0);
 121         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 122         so_data  (so, ((w - 1) << 16) | 0);
 123         so_data  (so, ((h - 1) << 16) | 0);
 124         so_method(so, nv30->screen->rankine, 0x1d88, 1);
 125         so_data  (so, (1 << 12) | h);
 126         /* Wonder why this is needed, context should all be set to zero on init */
 127         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_TX_ORIGIN, 1);
 128         so_data  (so, 0);
 129
 130         so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
 131         return TRUE;
 132 }
 133
 134 struct nv30_state_entry nv30_state_framebuffer = {
 135         .validate = nv30_state_framebuffer_validate,
 136         .dirty = {
 137                 .pipe = NV30_NEW_FB,
 138                 .hw = NV30_STATE_FB
 139         }
 140 };