2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_half.h"
30 #include "nouveau/nv_object.xml.h"
31 #include "nv30-40_3d.xml.h"
32 #include "nv30_context.h"
33 #include "nv30_format.h"
36 nv30_validate_fb(struct nv30_context
*nv30
)
38 struct pipe_screen
*pscreen
= &nv30
->screen
->base
.base
;
39 struct pipe_framebuffer_state
*fb
= &nv30
->framebuffer
;
40 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
41 struct nouveau_object
*eng3d
= nv30
->screen
->eng3d
;
48 nv30
->state
.rt_enable
= (NV30_3D_RT_ENABLE_COLOR0
<< fb
->nr_cbufs
) - 1;
49 if (nv30
->state
.rt_enable
> 1)
50 nv30
->state
.rt_enable
|= NV30_3D_RT_ENABLE_MRT
;
53 if (fb
->nr_cbufs
> 0) {
54 struct nv30_miptree
*mt
= nv30_miptree(fb
->cbufs
[0]->texture
);
55 rt_format
|= nv30_format(pscreen
, fb
->cbufs
[0]->format
)->hw
;
56 rt_format
|= mt
->ms_mode
;
58 rt_format
|= NV30_3D_RT_FORMAT_TYPE_SWIZZLED
;
60 rt_format
|= NV30_3D_RT_FORMAT_TYPE_LINEAR
;
62 if (fb
->zsbuf
&& util_format_get_blocksize(fb
->zsbuf
->format
) > 2)
63 rt_format
|= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8
;
65 rt_format
|= NV30_3D_RT_FORMAT_COLOR_R5G6B5
;
69 rt_format
|= nv30_format(pscreen
, fb
->zsbuf
->format
)->hw
;
70 if (nv30_miptree(fb
->zsbuf
->texture
)->swizzled
)
71 rt_format
|= NV30_3D_RT_FORMAT_TYPE_SWIZZLED
;
73 rt_format
|= NV30_3D_RT_FORMAT_TYPE_LINEAR
;
75 if (fb
->nr_cbufs
&& util_format_get_blocksize(fb
->cbufs
[0]->format
) > 2)
76 rt_format
|= NV30_3D_RT_FORMAT_ZETA_Z24S8
;
78 rt_format
|= NV30_3D_RT_FORMAT_ZETA_Z16
;
81 /* hardware rounds down render target offset to 64 bytes, but surfaces
82 * with a size of 2x2 pixel (16bpp) or 1x1 pixel (32bpp) have an
83 * unaligned start aaddress. For these two important square formats
84 * we can hack around this limitation by adjusting the viewport origin
86 if (nv30
->state
.rt_enable
) {
87 int off
= nv30_surface(fb
->cbufs
[0])->offset
& 63;
89 x
+= off
/ (util_format_get_blocksize(fb
->cbufs
[0]->format
) * 2);
95 if (rt_format
& NV30_3D_RT_FORMAT_TYPE_SWIZZLED
) {
96 rt_format
|= util_logbase2(w
) << 16;
97 rt_format
|= util_logbase2(h
) << 24;
100 if (!PUSH_SPACE(push
, 64))
102 PUSH_RESET(push
, BUFCTX_FB
);
104 BEGIN_NV04(push
, SUBC_3D(0x1da4), 1);
106 BEGIN_NV04(push
, NV30_3D(RT_HORIZ
), 3);
107 PUSH_DATA (push
, w
<< 16);
108 PUSH_DATA (push
, h
<< 16);
109 PUSH_DATA (push
, rt_format
);
110 BEGIN_NV04(push
, NV30_3D(VIEWPORT_HORIZ
), 2);
111 PUSH_DATA (push
, w
<< 16);
112 PUSH_DATA (push
, h
<< 16);
113 BEGIN_NV04(push
, NV30_3D(VIEWPORT_TX_ORIGIN
), 4);
114 PUSH_DATA (push
, (y
<< 16) | x
);
116 PUSH_DATA (push
, ((w
- 1) << 16) | 0);
117 PUSH_DATA (push
, ((h
- 1) << 16) | 0);
119 if ((nv30
->state
.rt_enable
& NV30_3D_RT_ENABLE_COLOR0
) || fb
->zsbuf
) {
120 struct nv30_surface
*rsf
= nv30_surface(fb
->cbufs
[0]);
121 struct nv30_surface
*zsf
= nv30_surface(fb
->zsbuf
);
122 struct nouveau_bo
*rbo
, *zbo
;
125 else if (!zsf
) zsf
= rsf
;
126 rbo
= nv30_miptree(rsf
->base
.texture
)->base
.bo
;
127 zbo
= nv30_miptree(zsf
->base
.texture
)->base
.bo
;
129 if (eng3d
->oclass
>= NV40_3D_CLASS
) {
130 BEGIN_NV04(push
, NV40_3D(ZETA_PITCH
), 1);
131 PUSH_DATA (push
, zsf
->pitch
);
132 BEGIN_NV04(push
, NV40_3D(COLOR0_PITCH
), 3);
133 PUSH_DATA (push
, rsf
->pitch
);
135 BEGIN_NV04(push
, NV30_3D(COLOR0_PITCH
), 3);
136 PUSH_DATA (push
, (zsf
->pitch
<< 16) | rsf
->pitch
);
138 PUSH_MTHDl(push
, NV30_3D(COLOR0_OFFSET
), BUFCTX_FB
, rbo
, rsf
->offset
& ~63,
139 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
140 PUSH_MTHDl(push
, NV30_3D(ZETA_OFFSET
), BUFCTX_FB
, zbo
, zsf
->offset
& ~63,
141 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
144 if (nv30
->state
.rt_enable
& NV30_3D_RT_ENABLE_COLOR1
) {
145 struct nv30_surface
*sf
= nv30_surface(fb
->cbufs
[1]);
146 struct nouveau_bo
*bo
= nv30_miptree(sf
->base
.texture
)->base
.bo
;
148 BEGIN_NV04(push
, NV30_3D(COLOR1_OFFSET
), 2);
149 PUSH_MTHDl(push
, NV30_3D(COLOR1_OFFSET
), BUFCTX_FB
, bo
, sf
->offset
,
150 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
151 PUSH_DATA (push
, sf
->pitch
);
154 if (nv30
->state
.rt_enable
& NV40_3D_RT_ENABLE_COLOR2
) {
155 struct nv30_surface
*sf
= nv30_surface(fb
->cbufs
[2]);
156 struct nouveau_bo
*bo
= nv30_miptree(sf
->base
.texture
)->base
.bo
;
158 BEGIN_NV04(push
, NV40_3D(COLOR2_OFFSET
), 1);
159 PUSH_MTHDl(push
, NV40_3D(COLOR2_OFFSET
), BUFCTX_FB
, bo
, sf
->offset
,
160 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
161 BEGIN_NV04(push
, NV40_3D(COLOR2_PITCH
), 1);
162 PUSH_DATA (push
, sf
->pitch
);
165 if (nv30
->state
.rt_enable
& NV40_3D_RT_ENABLE_COLOR3
) {
166 struct nv30_surface
*sf
= nv30_surface(fb
->cbufs
[3]);
167 struct nouveau_bo
*bo
= nv30_miptree(sf
->base
.texture
)->base
.bo
;
169 BEGIN_NV04(push
, NV40_3D(COLOR3_OFFSET
), 1);
170 PUSH_MTHDl(push
, NV40_3D(COLOR3_OFFSET
), BUFCTX_FB
, bo
, sf
->offset
,
171 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
172 BEGIN_NV04(push
, NV40_3D(COLOR3_PITCH
), 1);
173 PUSH_DATA (push
, sf
->pitch
);
178 nv30_validate_blend_colour(struct nv30_context
*nv30
)
180 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
181 float *rgba
= nv30
->blend_colour
.color
;
183 if (nv30
->framebuffer
.nr_cbufs
) {
184 switch (nv30
->framebuffer
.cbufs
[0]->format
) {
185 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
186 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
187 BEGIN_NV04(push
, NV30_3D(BLEND_COLOR
), 1);
188 PUSH_DATA (push
, (util_float_to_half(rgba
[0]) << 0) |
189 (util_float_to_half(rgba
[1]) << 16));
190 BEGIN_NV04(push
, SUBC_3D(0x037c), 1);
191 PUSH_DATA (push
, (util_float_to_half(rgba
[2]) << 0) |
192 (util_float_to_half(rgba
[3]) << 16));
199 BEGIN_NV04(push
, NV30_3D(BLEND_COLOR
), 1);
200 PUSH_DATA (push
, (float_to_ubyte(rgba
[3]) << 24) |
201 (float_to_ubyte(rgba
[0]) << 16) |
202 (float_to_ubyte(rgba
[1]) << 8) |
203 (float_to_ubyte(rgba
[2]) << 0));
207 nv30_validate_stencil_ref(struct nv30_context
*nv30
)
209 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
211 BEGIN_NV04(push
, NV30_3D(STENCIL_FUNC_REF(0)), 1);
212 PUSH_DATA (push
, nv30
->stencil_ref
.ref_value
[0]);
213 BEGIN_NV04(push
, NV30_3D(STENCIL_FUNC_REF(1)), 1);
214 PUSH_DATA (push
, nv30
->stencil_ref
.ref_value
[1]);
218 nv30_validate_stipple(struct nv30_context
*nv30
)
220 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
222 BEGIN_NV04(push
, NV30_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
223 PUSH_DATAp(push
, nv30
->stipple
.stipple
, 32);
227 nv30_validate_scissor(struct nv30_context
*nv30
)
229 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
230 struct pipe_scissor_state
*s
= &nv30
->scissor
;
232 if (!(nv30
->dirty
& NV30_NEW_SCISSOR
) &&
233 nv30
->rast
->pipe
.scissor
!= nv30
->state
.scissor_off
)
235 nv30
->state
.scissor_off
= !nv30
->rast
->pipe
.scissor
;
237 BEGIN_NV04(push
, NV30_3D(SCISSOR_HORIZ
), 2);
238 if (nv30
->rast
->pipe
.scissor
) {
239 PUSH_DATA (push
, ((s
->maxx
- s
->minx
) << 16) | s
->minx
);
240 PUSH_DATA (push
, ((s
->maxy
- s
->miny
) << 16) | s
->miny
);
242 PUSH_DATA (push
, 0x10000000);
243 PUSH_DATA (push
, 0x10000000);
248 nv30_validate_viewport(struct nv30_context
*nv30
)
250 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
251 struct pipe_viewport_state
*vp
= &nv30
->viewport
;
253 BEGIN_NV04(push
, NV30_3D(VIEWPORT_TRANSLATE_X
), 8);
254 PUSH_DATAf(push
, vp
->translate
[0]);
255 PUSH_DATAf(push
, vp
->translate
[1]);
256 PUSH_DATAf(push
, vp
->translate
[2]);
257 PUSH_DATAf(push
, vp
->translate
[3]);
258 PUSH_DATAf(push
, vp
->scale
[0]);
259 PUSH_DATAf(push
, vp
->scale
[1]);
260 PUSH_DATAf(push
, vp
->scale
[2]);
261 PUSH_DATAf(push
, vp
->scale
[3]);
262 BEGIN_NV04(push
, NV30_3D(DEPTH_RANGE_NEAR
), 2);
263 PUSH_DATAf(push
, vp
->translate
[2] - fabsf(vp
->scale
[2]));
264 PUSH_DATAf(push
, vp
->translate
[2] + fabsf(vp
->scale
[2]));
268 nv30_validate_clip(struct nv30_context
*nv30
)
270 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
272 uint32_t clpd_enable
= 0;
274 for (i
= 0; i
< 6; i
++) {
275 if (nv30
->rast
->pipe
.clip_plane_enable
& (1 << i
)) {
276 if (nv30
->dirty
& NV30_NEW_CLIP
) {
277 BEGIN_NV04(push
, NV30_3D(VP_UPLOAD_CONST_ID
), 5);
279 PUSH_DATAp(push
, nv30
->clip
.ucp
[i
], 4);
282 clpd_enable
|= 1 << (1 + 4*i
);
286 BEGIN_NV04(push
, NV30_3D(VP_CLIP_PLANES_ENABLE
), 1);
287 PUSH_DATA (push
, clpd_enable
);
291 nv30_validate_blend(struct nv30_context
*nv30
)
293 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
295 PUSH_SPACE(push
, nv30
->blend
->size
);
296 PUSH_DATAp(push
, nv30
->blend
->data
, nv30
->blend
->size
);
300 nv30_validate_zsa(struct nv30_context
*nv30
)
302 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
304 PUSH_SPACE(push
, nv30
->zsa
->size
);
305 PUSH_DATAp(push
, nv30
->zsa
->data
, nv30
->zsa
->size
);
309 nv30_validate_rasterizer(struct nv30_context
*nv30
)
311 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
313 PUSH_SPACE(push
, nv30
->rast
->size
);
314 PUSH_DATAp(push
, nv30
->rast
->data
, nv30
->rast
->size
);
318 nv30_validate_multisample(struct nv30_context
*nv30
)
320 struct pipe_rasterizer_state
*rasterizer
= &nv30
->rast
->pipe
;
321 struct pipe_blend_state
*blend
= &nv30
->blend
->pipe
;
322 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
323 uint32_t ctrl
= nv30
->sample_mask
<< 16;
325 if (blend
->alpha_to_one
)
327 if (blend
->alpha_to_coverage
)
329 if (rasterizer
->multisample
)
332 BEGIN_NV04(push
, NV30_3D(MULTISAMPLE_CONTROL
), 1);
333 PUSH_DATA (push
, ctrl
);
337 nv30_validate_fragment(struct nv30_context
*nv30
)
339 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
340 struct nv30_fragprog
*fp
= nv30
->fragprog
.program
;
342 BEGIN_NV04(push
, NV30_3D(RT_ENABLE
), 1);
343 PUSH_DATA (push
, nv30
->state
.rt_enable
& ~fp
->rt_enable
);
344 BEGIN_NV04(push
, NV30_3D(COORD_CONVENTIONS
), 1);
345 PUSH_DATA (push
, fp
->coord_conventions
| nv30
->framebuffer
.height
);
349 nv30_validate_point_coord(struct nv30_context
*nv30
)
351 struct pipe_rasterizer_state
*rasterizer
= &nv30
->rast
->pipe
;
352 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
353 struct nv30_fragprog
*fp
= nv30
->fragprog
.program
;
354 uint32_t hw
= 0x00000000;
357 hw
|= (nv30
->rast
->pipe
.sprite_coord_enable
& 0xff) << 8;
359 hw
|= fp
->point_sprite_control
;
361 if (rasterizer
->sprite_coord_mode
== PIPE_SPRITE_COORD_LOWER_LEFT
) {
363 nv30
->draw_flags
|= NV30_NEW_RASTERIZER
;
365 if (rasterizer
->point_quad_rasterization
) {
366 hw
|= NV30_3D_POINT_SPRITE_ENABLE
;
370 BEGIN_NV04(push
, NV30_3D(POINT_SPRITE
), 1);
371 PUSH_DATA (push
, hw
);
374 struct state_validate
{
375 void (*func
)(struct nv30_context
*);
379 static struct state_validate hwtnl_validate_list
[] = {
380 { nv30_validate_fb
, NV30_NEW_FRAMEBUFFER
},
381 { nv30_validate_blend
, NV30_NEW_BLEND
},
382 { nv30_validate_zsa
, NV30_NEW_ZSA
},
383 { nv30_validate_rasterizer
, NV30_NEW_RASTERIZER
},
384 { nv30_validate_multisample
, NV30_NEW_SAMPLE_MASK
| NV30_NEW_BLEND
|
385 NV30_NEW_RASTERIZER
},
386 { nv30_validate_blend_colour
, NV30_NEW_BLEND_COLOUR
|
387 NV30_NEW_FRAMEBUFFER
},
388 { nv30_validate_stencil_ref
, NV30_NEW_STENCIL_REF
},
389 { nv30_validate_stipple
, NV30_NEW_STIPPLE
},
390 { nv30_validate_scissor
, NV30_NEW_SCISSOR
| NV30_NEW_RASTERIZER
},
391 { nv30_validate_viewport
, NV30_NEW_VIEWPORT
},
392 { nv30_validate_clip
, NV30_NEW_CLIP
},
393 { nv30_fragprog_validate
, NV30_NEW_FRAGPROG
| NV30_NEW_FRAGCONST
},
394 { nv30_vertprog_validate
, NV30_NEW_VERTPROG
| NV30_NEW_VERTCONST
|
395 NV30_NEW_FRAGPROG
| NV30_NEW_RASTERIZER
},
396 { nv30_validate_fragment
, NV30_NEW_FRAMEBUFFER
| NV30_NEW_FRAGPROG
},
397 { nv30_validate_point_coord
, NV30_NEW_RASTERIZER
| NV30_NEW_FRAGPROG
},
398 { nv30_fragtex_validate
, NV30_NEW_FRAGTEX
},
399 { nv40_verttex_validate
, NV30_NEW_VERTTEX
},
400 { nv30_vbo_validate
, NV30_NEW_VERTEX
| NV30_NEW_ARRAYS
},
404 #define NV30_SWTNL_MASK (NV30_NEW_VIEWPORT | \
406 NV30_NEW_VERTPROG | \
407 NV30_NEW_VERTCONST | \
412 static struct state_validate swtnl_validate_list
[] = {
413 { nv30_validate_fb
, NV30_NEW_FRAMEBUFFER
},
414 { nv30_validate_blend
, NV30_NEW_BLEND
},
415 { nv30_validate_zsa
, NV30_NEW_ZSA
},
416 { nv30_validate_rasterizer
, NV30_NEW_RASTERIZER
},
417 { nv30_validate_multisample
, NV30_NEW_SAMPLE_MASK
| NV30_NEW_BLEND
|
418 NV30_NEW_RASTERIZER
},
419 { nv30_validate_blend_colour
, NV30_NEW_BLEND_COLOUR
|
420 NV30_NEW_FRAMEBUFFER
},
421 { nv30_validate_stencil_ref
, NV30_NEW_STENCIL_REF
},
422 { nv30_validate_stipple
, NV30_NEW_STIPPLE
},
423 { nv30_validate_scissor
, NV30_NEW_SCISSOR
| NV30_NEW_RASTERIZER
},
424 { nv30_fragprog_validate
, NV30_NEW_FRAGPROG
| NV30_NEW_FRAGCONST
},
425 { nv30_validate_fragment
, NV30_NEW_FRAMEBUFFER
| NV30_NEW_FRAGPROG
},
426 { nv30_fragtex_validate
, NV30_NEW_FRAGTEX
},
431 nv30_state_context_switch(struct nv30_context
*nv30
)
433 struct nv30_context
*prev
= nv30
->screen
->cur_ctx
;
436 nv30
->state
= prev
->state
;
437 nv30
->dirty
= NV30_NEW_ALL
;
440 nv30
->dirty
&= ~(NV30_NEW_VERTEX
| NV30_NEW_ARRAYS
);
442 if (!nv30
->vertprog
.program
)
443 nv30
->dirty
&= ~NV30_NEW_VERTPROG
;
444 if (!nv30
->fragprog
.program
)
445 nv30
->dirty
&= ~NV30_NEW_FRAGPROG
;
448 nv30
->dirty
&= ~NV30_NEW_BLEND
;
450 nv30
->dirty
&= ~NV30_NEW_RASTERIZER
;
452 nv30
->dirty
&= ~NV30_NEW_ZSA
;
454 nv30
->screen
->cur_ctx
= nv30
;
455 nv30
->base
.pushbuf
->user_priv
= &nv30
->bufctx
;
459 nv30_state_validate(struct nv30_context
*nv30
, boolean hwtnl
)
461 struct nouveau_screen
*screen
= &nv30
->screen
->base
;
462 struct nouveau_pushbuf
*push
= nv30
->base
.pushbuf
;
463 struct nouveau_bufctx
*bctx
= nv30
->bufctx
;
464 struct nouveau_bufref
*bref
;
465 struct state_validate
*validate
;
467 if (nv30
->screen
->cur_ctx
!= nv30
)
468 nv30_state_context_switch(nv30
);
471 nv30
->draw_dirty
|= nv30
->dirty
;
472 if (nv30
->draw_flags
) {
473 nv30
->draw_flags
&= ~nv30
->dirty
;
474 if (!nv30
->draw_flags
)
475 nv30
->dirty
|= NV30_SWTNL_MASK
;
479 if (!nv30
->draw_flags
)
480 validate
= hwtnl_validate_list
;
482 validate
= swtnl_validate_list
;
485 while (validate
->func
) {
486 if (nv30
->dirty
& validate
->mask
)
487 validate
->func(nv30
);
494 nouveau_pushbuf_bufctx(push
, bctx
);
495 if (nouveau_pushbuf_validate(push
)) {
496 nouveau_pushbuf_bufctx(push
, NULL
);
501 BEGIN_NV04(push
, NV30_3D(VTX_CACHE_INVALIDATE_1710
), 1);
503 if (nv30
->screen
->eng3d
->oclass
>= NV40_3D_CLASS
) {
504 BEGIN_NV04(push
, NV40_3D(TEX_CACHE_CTL
), 1);
506 BEGIN_NV04(push
, NV40_3D(TEX_CACHE_CTL
), 1);
508 BEGIN_NV04(push
, NV30_3D(R1718
), 1);
510 BEGIN_NV04(push
, NV30_3D(R1718
), 1);
512 BEGIN_NV04(push
, NV30_3D(R1718
), 1);
516 LIST_FOR_EACH_ENTRY(bref
, &bctx
->current
, thead
) {
517 struct nv04_resource
*res
= bref
->priv
;
518 if (res
&& res
->mm
) {
519 nouveau_fence_ref(screen
->fence
.current
, &res
->fence
);
521 if (bref
->flags
& NOUVEAU_BO_RD
)
522 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
524 if (bref
->flags
& NOUVEAU_BO_WR
) {
525 nouveau_fence_ref(screen
->fence
.current
, &res
->fence_wr
);
526 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
535 nv30_state_release(struct nv30_context
*nv30
)
537 nouveau_pushbuf_bufctx(nv30
->base
.pushbuf
, NULL
);