1 #include "pipe/p_context.h"
2 #include "pipe/p_state.h"
3 #include "pipe/p_inlines.h"
5 #include "nv30_context.h"
6 #include "nv30_state.h"
8 #include "nouveau/nouveau_channel.h"
9 #include "nouveau/nouveau_pushbuf.h"
10 #include "nouveau/nouveau_util.h"
15 nv30_vbo_format_to_hw(enum pipe_format pipe
, unsigned *fmt
, unsigned *ncomp
)
18 case PIPE_FORMAT_R32_FLOAT
:
19 case PIPE_FORMAT_R32G32_FLOAT
:
20 case PIPE_FORMAT_R32G32B32_FLOAT
:
21 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
22 *fmt
= NV34TCL_VTXFMT_TYPE_FLOAT
;
24 case PIPE_FORMAT_R8_UNORM
:
25 case PIPE_FORMAT_R8G8_UNORM
:
26 case PIPE_FORMAT_R8G8B8_UNORM
:
27 case PIPE_FORMAT_R8G8B8A8_UNORM
:
28 *fmt
= NV34TCL_VTXFMT_TYPE_UBYTE
;
30 case PIPE_FORMAT_R16_SSCALED
:
31 case PIPE_FORMAT_R16G16_SSCALED
:
32 case PIPE_FORMAT_R16G16B16_SSCALED
:
33 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
34 *fmt
= NV34TCL_VTXFMT_TYPE_USHORT
;
37 NOUVEAU_ERR("Unknown format %s\n", pf_name(pipe
));
42 case PIPE_FORMAT_R8_UNORM
:
43 case PIPE_FORMAT_R32_FLOAT
:
44 case PIPE_FORMAT_R16_SSCALED
:
47 case PIPE_FORMAT_R8G8_UNORM
:
48 case PIPE_FORMAT_R32G32_FLOAT
:
49 case PIPE_FORMAT_R16G16_SSCALED
:
52 case PIPE_FORMAT_R8G8B8_UNORM
:
53 case PIPE_FORMAT_R32G32B32_FLOAT
:
54 case PIPE_FORMAT_R16G16B16_SSCALED
:
57 case PIPE_FORMAT_R8G8B8A8_UNORM
:
58 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
59 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
63 NOUVEAU_ERR("Unknown format %s\n", pf_name(pipe
));
71 nv30_vbo_set_idxbuf(struct nv30_context
*nv30
, struct pipe_buffer
*ib
,
74 struct pipe_screen
*pscreen
= &nv30
->screen
->base
.base
;
79 nv30
->idxbuf_format
= 0xdeadbeef;
83 if (!pscreen
->get_param(pscreen
, NOUVEAU_CAP_HW_IDXBUF
) || ib_size
== 1)
88 type
= NV34TCL_IDXBUF_FORMAT_TYPE_U16
;
91 type
= NV34TCL_IDXBUF_FORMAT_TYPE_U32
;
97 if (ib
!= nv30
->idxbuf
||
98 type
!= nv30
->idxbuf_format
) {
99 nv30
->dirty
|= NV30_NEW_ARRAYS
;
101 nv30
->idxbuf_format
= type
;
108 nv30_vbo_static_attrib(struct nv30_context
*nv30
, struct nouveau_stateobj
*so
,
109 int attrib
, struct pipe_vertex_element
*ve
,
110 struct pipe_vertex_buffer
*vb
)
112 struct pipe_screen
*pscreen
= nv30
->pipe
.screen
;
113 struct nouveau_grobj
*rankine
= nv30
->screen
->rankine
;
114 unsigned type
, ncomp
;
117 if (nv30_vbo_format_to_hw(ve
->src_format
, &type
, &ncomp
))
120 map
= pipe_buffer_map(pscreen
, vb
->buffer
, PIPE_BUFFER_USAGE_CPU_READ
);
121 map
+= vb
->buffer_offset
+ ve
->src_offset
;
124 case NV34TCL_VTXFMT_TYPE_FLOAT
:
130 so_method(so
, rankine
, NV34TCL_VTX_ATTR_4F_X(attrib
), 4);
131 so_data (so
, fui(v
[0]));
132 so_data (so
, fui(v
[1]));
133 so_data (so
, fui(v
[2]));
134 so_data (so
, fui(v
[3]));
137 so_method(so
, rankine
, NV34TCL_VTX_ATTR_3F_X(attrib
), 3);
138 so_data (so
, fui(v
[0]));
139 so_data (so
, fui(v
[1]));
140 so_data (so
, fui(v
[2]));
143 so_method(so
, rankine
, NV34TCL_VTX_ATTR_2F_X(attrib
), 2);
144 so_data (so
, fui(v
[0]));
145 so_data (so
, fui(v
[1]));
148 so_method(so
, rankine
, NV34TCL_VTX_ATTR_1F(attrib
), 1);
149 so_data (so
, fui(v
[0]));
152 pipe_buffer_unmap(pscreen
, vb
->buffer
);
158 pipe_buffer_unmap(pscreen
, vb
->buffer
);
162 pipe_buffer_unmap(pscreen
, vb
->buffer
);
167 nv30_draw_arrays(struct pipe_context
*pipe
,
168 unsigned mode
, unsigned start
, unsigned count
)
170 struct nv30_context
*nv30
= nv30_context(pipe
);
171 struct nouveau_channel
*chan
= nv30
->screen
->base
.channel
;
172 unsigned restart
= 0;
174 nv30_vbo_set_idxbuf(nv30
, NULL
, 0);
175 if (FORCE_SWTNL
|| !nv30_state_validate(nv30
)) {
176 /*return nv30_draw_elements_swtnl(pipe, NULL, 0,
177 mode, start, count);*/
184 nv30_state_emit(nv30
);
186 vc
= nouveau_vbuf_split(chan
->pushbuf
->remaining
, 6, 256,
187 mode
, start
, count
, &restart
);
193 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
194 OUT_RING (nvgl_primitive(mode
));
198 BEGIN_RING(rankine
, NV34TCL_VB_VERTEX_BATCH
, 1);
199 OUT_RING (((nr
- 1) << 24) | start
);
205 unsigned push
= nr
> 2047 ? 2047 : nr
;
209 BEGIN_RING_NI(rankine
, NV34TCL_VB_VERTEX_BATCH
, push
);
211 OUT_RING(((0x100 - 1) << 24) | start
);
216 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
223 pipe
->flush(pipe
, 0, NULL
);
228 nv30_draw_elements_u08(struct nv30_context
*nv30
, void *ib
,
229 unsigned mode
, unsigned start
, unsigned count
)
231 struct nouveau_channel
*chan
= nv30
->screen
->base
.channel
;
234 uint8_t *elts
= (uint8_t *)ib
+ start
;
235 unsigned vc
, push
, restart
= 0;
237 nv30_state_emit(nv30
);
239 vc
= nouveau_vbuf_split(chan
->pushbuf
->remaining
, 6, 2,
240 mode
, start
, count
, &restart
);
247 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
248 OUT_RING (nvgl_primitive(mode
));
251 BEGIN_RING(rankine
, NV34TCL_VB_ELEMENT_U32
, 1);
259 push
= MIN2(vc
, 2047 * 2);
261 BEGIN_RING_NI(rankine
, NV34TCL_VB_ELEMENT_U16
, push
>> 1);
262 for (i
= 0; i
< push
; i
+=2)
263 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
269 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
277 nv30_draw_elements_u16(struct nv30_context
*nv30
, void *ib
,
278 unsigned mode
, unsigned start
, unsigned count
)
280 struct nouveau_channel
*chan
= nv30
->screen
->base
.channel
;
283 uint16_t *elts
= (uint16_t *)ib
+ start
;
284 unsigned vc
, push
, restart
= 0;
286 nv30_state_emit(nv30
);
288 vc
= nouveau_vbuf_split(chan
->pushbuf
->remaining
, 6, 2,
289 mode
, start
, count
, &restart
);
296 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
297 OUT_RING (nvgl_primitive(mode
));
300 BEGIN_RING(rankine
, NV34TCL_VB_ELEMENT_U32
, 1);
308 push
= MIN2(vc
, 2047 * 2);
310 BEGIN_RING_NI(rankine
, NV34TCL_VB_ELEMENT_U16
, push
>> 1);
311 for (i
= 0; i
< push
; i
+=2)
312 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
318 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
326 nv30_draw_elements_u32(struct nv30_context
*nv30
, void *ib
,
327 unsigned mode
, unsigned start
, unsigned count
)
329 struct nouveau_channel
*chan
= nv30
->screen
->base
.channel
;
332 uint32_t *elts
= (uint32_t *)ib
+ start
;
333 unsigned vc
, push
, restart
= 0;
335 nv30_state_emit(nv30
);
337 vc
= nouveau_vbuf_split(chan
->pushbuf
->remaining
, 5, 1,
338 mode
, start
, count
, &restart
);
345 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
346 OUT_RING (nvgl_primitive(mode
));
349 push
= MIN2(vc
, 2047);
351 BEGIN_RING_NI(rankine
, NV34TCL_VB_ELEMENT_U32
, push
);
352 OUT_RINGp (elts
, push
);
358 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
366 nv30_draw_elements_inline(struct pipe_context
*pipe
,
367 struct pipe_buffer
*ib
, unsigned ib_size
,
368 unsigned mode
, unsigned start
, unsigned count
)
370 struct nv30_context
*nv30
= nv30_context(pipe
);
371 struct pipe_screen
*pscreen
= pipe
->screen
;
374 map
= pipe_buffer_map(pscreen
, ib
, PIPE_BUFFER_USAGE_CPU_READ
);
376 NOUVEAU_ERR("failed mapping ib\n");
382 nv30_draw_elements_u08(nv30
, map
, mode
, start
, count
);
385 nv30_draw_elements_u16(nv30
, map
, mode
, start
, count
);
388 nv30_draw_elements_u32(nv30
, map
, mode
, start
, count
);
391 NOUVEAU_ERR("invalid idxbuf fmt %d\n", ib_size
);
395 pipe_buffer_unmap(pscreen
, ib
);
400 nv30_draw_elements_vbo(struct pipe_context
*pipe
,
401 unsigned mode
, unsigned start
, unsigned count
)
403 struct nv30_context
*nv30
= nv30_context(pipe
);
404 struct nouveau_channel
*chan
= nv30
->screen
->base
.channel
;
405 unsigned restart
= 0;
410 nv30_state_emit(nv30
);
412 vc
= nouveau_vbuf_split(chan
->pushbuf
->remaining
, 6, 256,
413 mode
, start
, count
, &restart
);
419 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
420 OUT_RING (nvgl_primitive(mode
));
424 BEGIN_RING(rankine
, NV34TCL_VB_INDEX_BATCH
, 1);
425 OUT_RING (((nr
- 1) << 24) | start
);
431 unsigned push
= nr
> 2047 ? 2047 : nr
;
435 BEGIN_RING_NI(rankine
, NV34TCL_VB_INDEX_BATCH
, push
);
437 OUT_RING(((0x100 - 1) << 24) | start
);
442 BEGIN_RING(rankine
, NV34TCL_VERTEX_BEGIN_END
, 1);
453 nv30_draw_elements(struct pipe_context
*pipe
,
454 struct pipe_buffer
*indexBuffer
, unsigned indexSize
,
455 unsigned mode
, unsigned start
, unsigned count
)
457 struct nv30_context
*nv30
= nv30_context(pipe
);
460 idxbuf
= nv30_vbo_set_idxbuf(nv30
, indexBuffer
, indexSize
);
461 if (FORCE_SWTNL
|| !nv30_state_validate(nv30
)) {
462 /*return nv30_draw_elements_swtnl(pipe, NULL, 0,
463 mode, start, count);*/
468 nv30_draw_elements_vbo(pipe
, mode
, start
, count
);
470 nv30_draw_elements_inline(pipe
, indexBuffer
, indexSize
,
474 pipe
->flush(pipe
, 0, NULL
);
479 nv30_vbo_validate(struct nv30_context
*nv30
)
481 struct nouveau_stateobj
*vtxbuf
, *vtxfmt
, *sattr
= NULL
;
482 struct nouveau_grobj
*rankine
= nv30
->screen
->rankine
;
483 struct pipe_buffer
*ib
= nv30
->idxbuf
;
484 unsigned ib_format
= nv30
->idxbuf_format
;
485 unsigned vb_flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
;
488 if (nv30
->edgeflags
) {
489 /*nv30->fallback_swtnl |= NV30_NEW_ARRAYS;*/
493 vtxbuf
= so_new(20, 18);
494 so_method(vtxbuf
, rankine
, NV34TCL_VTXBUF_ADDRESS(0), nv30
->vtxelt_nr
);
495 vtxfmt
= so_new(17, 0);
496 so_method(vtxfmt
, rankine
, NV34TCL_VTXFMT(0), nv30
->vtxelt_nr
);
498 for (hw
= 0; hw
< nv30
->vtxelt_nr
; hw
++) {
499 struct pipe_vertex_element
*ve
;
500 struct pipe_vertex_buffer
*vb
;
501 unsigned type
, ncomp
;
503 ve
= &nv30
->vtxelt
[hw
];
504 vb
= &nv30
->vtxbuf
[ve
->vertex_buffer_index
];
508 sattr
= so_new(16 * 5, 0);
510 if (nv30_vbo_static_attrib(nv30
, sattr
, hw
, ve
, vb
)) {
512 so_data(vtxfmt
, NV34TCL_VTXFMT_TYPE_FLOAT
);
517 if (nv30_vbo_format_to_hw(ve
->src_format
, &type
, &ncomp
)) {
518 /*nv30->fallback_swtnl |= NV30_NEW_ARRAYS;*/
519 so_ref(NULL
, &vtxbuf
);
520 so_ref(NULL
, &vtxfmt
);
524 so_reloc(vtxbuf
, nouveau_bo(vb
->buffer
), vb
->buffer_offset
+
525 ve
->src_offset
, vb_flags
| NOUVEAU_BO_LOW
|
526 NOUVEAU_BO_OR
, 0, NV34TCL_VTXBUF_ADDRESS_DMA1
);
527 so_data (vtxfmt
, ((vb
->stride
<< NV34TCL_VTXFMT_STRIDE_SHIFT
) |
528 (ncomp
<< NV34TCL_VTXFMT_SIZE_SHIFT
) | type
));
532 struct nouveau_bo
*bo
= nouveau_bo(ib
);
534 so_method(vtxbuf
, rankine
, NV34TCL_IDXBUF_ADDRESS
, 2);
535 so_reloc (vtxbuf
, bo
, 0, vb_flags
| NOUVEAU_BO_LOW
, 0, 0);
536 so_reloc (vtxbuf
, bo
, ib_format
, vb_flags
| NOUVEAU_BO_OR
,
537 0, NV34TCL_IDXBUF_FORMAT_DMA1
);
540 so_method(vtxbuf
, rankine
, 0x1710, 1);
543 so_ref(vtxbuf
, &nv30
->state
.hw
[NV30_STATE_VTXBUF
]);
544 so_ref(NULL
, &vtxbuf
);
545 nv30
->state
.dirty
|= (1ULL << NV30_STATE_VTXBUF
);
546 so_ref(vtxfmt
, &nv30
->state
.hw
[NV30_STATE_VTXFMT
]);
547 so_ref(NULL
, &vtxfmt
);
548 nv30
->state
.dirty
|= (1ULL << NV30_STATE_VTXFMT
);
549 so_ref(sattr
, &nv30
->state
.hw
[NV30_STATE_VTXATTR
]);
550 so_ref(NULL
, &sattr
);
551 nv30
->state
.dirty
|= (1ULL << NV30_STATE_VTXATTR
);
555 struct nv30_state_entry nv30_state_vbo
= {
556 .validate
= nv30_vbo_validate
,
558 .pipe
= NV30_NEW_ARRAYS
,