1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_inlines.h"
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
10 #include "nv40_context.h"
20 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
21 #define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
22 #define DEF_CTEST NV40_FP_OP_COND_TR
23 #include "nv40_shader.h"
25 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
26 #define neg(s) nv40_sr_neg((s))
27 #define abs(s) nv40_sr_abs((s))
28 #define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
30 #define MAX_CONSTS 128
33 struct nv40_fragment_program
*fp
;
35 uint attrib_map
[PIPE_MAX_SHADER_INPUTS
];
38 unsigned r_temps_discard
;
39 struct nv40_sreg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
40 struct nv40_sreg
*r_temp
;
53 struct nv40_sreg imm
[MAX_IMM
];
57 static INLINE
struct nv40_sreg
58 temp(struct nv40_fpc
*fpc
)
60 int idx
= ffs(~fpc
->r_temps
) - 1;
63 NOUVEAU_ERR("out of temps!!\n");
65 return nv40_sr(NV40SR_TEMP
, 0);
68 fpc
->r_temps
|= (1 << idx
);
69 fpc
->r_temps_discard
|= (1 << idx
);
70 return nv40_sr(NV40SR_TEMP
, idx
);
74 release_temps(struct nv40_fpc
*fpc
)
76 fpc
->r_temps
&= ~fpc
->r_temps_discard
;
77 fpc
->r_temps_discard
= 0;
80 static INLINE
struct nv40_sreg
81 constant(struct nv40_fpc
*fpc
, int pipe
, float vals
[4])
85 if (fpc
->nr_consts
== MAX_CONSTS
)
87 idx
= fpc
->nr_consts
++;
89 fpc
->consts
[idx
].pipe
= pipe
;
91 memcpy(fpc
->consts
[idx
].vals
, vals
, 4 * sizeof(float));
92 return nv40_sr(NV40SR_CONST
, idx
);
95 #define arith(cc,s,o,d,m,s0,s1,s2) \
96 nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
97 (d), (m), (s0), (s1), (s2))
98 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
99 nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
100 (d), (m), (s0), none, none)
103 grow_insns(struct nv40_fpc
*fpc
, int size
)
105 struct nv40_fragment_program
*fp
= fpc
->fp
;
107 fp
->insn_len
+= size
;
108 fp
->insn
= realloc(fp
->insn
, sizeof(uint32_t) * fp
->insn_len
);
112 emit_src(struct nv40_fpc
*fpc
, int pos
, struct nv40_sreg src
)
114 struct nv40_fragment_program
*fp
= fpc
->fp
;
115 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
120 sr
|= (NV40_FP_REG_TYPE_INPUT
<< NV40_FP_REG_TYPE_SHIFT
);
121 hw
[0] |= (src
.index
<< NV40_FP_OP_INPUT_SRC_SHIFT
);
124 sr
|= NV40_FP_REG_SRC_HALF
;
127 sr
|= (NV40_FP_REG_TYPE_TEMP
<< NV40_FP_REG_TYPE_SHIFT
);
128 sr
|= (src
.index
<< NV40_FP_REG_SRC_SHIFT
);
131 if (!fpc
->have_const
) {
136 hw
= &fp
->insn
[fpc
->inst_offset
];
137 if (fpc
->consts
[src
.index
].pipe
>= 0) {
138 struct nv40_fragment_program_data
*fpd
;
140 fp
->consts
= realloc(fp
->consts
, ++fp
->nr_consts
*
142 fpd
= &fp
->consts
[fp
->nr_consts
- 1];
143 fpd
->offset
= fpc
->inst_offset
+ 4;
144 fpd
->index
= fpc
->consts
[src
.index
].pipe
;
145 memset(&fp
->insn
[fpd
->offset
], 0, sizeof(uint32_t) * 4);
147 memcpy(&fp
->insn
[fpc
->inst_offset
+ 4],
148 fpc
->consts
[src
.index
].vals
,
149 sizeof(uint32_t) * 4);
152 sr
|= (NV40_FP_REG_TYPE_CONST
<< NV40_FP_REG_TYPE_SHIFT
);
155 sr
|= (NV40_FP_REG_TYPE_INPUT
<< NV40_FP_REG_TYPE_SHIFT
);
162 sr
|= NV40_FP_REG_NEGATE
;
165 hw
[1] |= (1 << (29 + pos
));
167 sr
|= ((src
.swz
[0] << NV40_FP_REG_SWZ_X_SHIFT
) |
168 (src
.swz
[1] << NV40_FP_REG_SWZ_Y_SHIFT
) |
169 (src
.swz
[2] << NV40_FP_REG_SWZ_Z_SHIFT
) |
170 (src
.swz
[3] << NV40_FP_REG_SWZ_W_SHIFT
));
176 emit_dst(struct nv40_fpc
*fpc
, struct nv40_sreg dst
)
178 struct nv40_fragment_program
*fp
= fpc
->fp
;
179 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
183 if (fpc
->num_regs
< (dst
.index
+ 1))
184 fpc
->num_regs
= dst
.index
+ 1;
187 if (dst
.index
== 1) {
188 fp
->fp_control
|= 0xe;
190 hw
[0] |= NV40_FP_OP_OUT_REG_HALF
;
200 hw
[0] |= (dst
.index
<< NV40_FP_OP_OUT_REG_SHIFT
);
204 nv40_fp_arith(struct nv40_fpc
*fpc
, int sat
, int op
,
205 struct nv40_sreg dst
, int mask
,
206 struct nv40_sreg s0
, struct nv40_sreg s1
, struct nv40_sreg s2
)
208 struct nv40_fragment_program
*fp
= fpc
->fp
;
211 fpc
->inst_offset
= fp
->insn_len
;
214 hw
= &fp
->insn
[fpc
->inst_offset
];
215 memset(hw
, 0, sizeof(uint32_t) * 4);
217 if (op
== NV40_FP_OP_OPCODE_KIL
)
218 fp
->fp_control
|= NV40TCL_FP_CONTROL_KIL
;
219 hw
[0] |= (op
<< NV40_FP_OP_OPCODE_SHIFT
);
220 hw
[0] |= (mask
<< NV40_FP_OP_OUTMASK_SHIFT
);
221 hw
[2] |= (dst
.dst_scale
<< NV40_FP_OP_DST_SCALE_SHIFT
);
224 hw
[0] |= NV40_FP_OP_OUT_SAT
;
227 hw
[0] |= NV40_FP_OP_COND_WRITE_ENABLE
;
228 hw
[1] |= (dst
.cc_test
<< NV40_FP_OP_COND_SHIFT
);
229 hw
[1] |= ((dst
.cc_swz
[0] << NV40_FP_OP_COND_SWZ_X_SHIFT
) |
230 (dst
.cc_swz
[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT
) |
231 (dst
.cc_swz
[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT
) |
232 (dst
.cc_swz
[3] << NV40_FP_OP_COND_SWZ_W_SHIFT
));
235 emit_src(fpc
, 0, s0
);
236 emit_src(fpc
, 1, s1
);
237 emit_src(fpc
, 2, s2
);
241 nv40_fp_tex(struct nv40_fpc
*fpc
, int sat
, int op
, int unit
,
242 struct nv40_sreg dst
, int mask
,
243 struct nv40_sreg s0
, struct nv40_sreg s1
, struct nv40_sreg s2
)
245 struct nv40_fragment_program
*fp
= fpc
->fp
;
247 nv40_fp_arith(fpc
, sat
, op
, dst
, mask
, s0
, s1
, s2
);
249 fp
->insn
[fpc
->inst_offset
] |= (unit
<< NV40_FP_OP_TEX_UNIT_SHIFT
);
250 fp
->samplers
|= (1 << unit
);
253 static INLINE
struct nv40_sreg
254 tgsi_src(struct nv40_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
)
256 struct nv40_sreg src
;
258 switch (fsrc
->Register
.File
) {
259 case TGSI_FILE_INPUT
:
260 src
= nv40_sr(NV40SR_INPUT
,
261 fpc
->attrib_map
[fsrc
->Register
.Index
]);
263 case TGSI_FILE_CONSTANT
:
264 src
= constant(fpc
, fsrc
->Register
.Index
, NULL
);
266 case TGSI_FILE_IMMEDIATE
:
267 assert(fsrc
->Register
.Index
< fpc
->nr_imm
);
268 src
= fpc
->imm
[fsrc
->Register
.Index
];
270 case TGSI_FILE_TEMPORARY
:
271 src
= fpc
->r_temp
[fsrc
->Register
.Index
];
273 /* NV40 fragprog result regs are just temps, so this is simple */
274 case TGSI_FILE_OUTPUT
:
275 src
= fpc
->r_result
[fsrc
->Register
.Index
];
278 NOUVEAU_ERR("bad src file\n");
282 src
.abs
= fsrc
->Register
.Absolute
;
283 src
.negate
= fsrc
->Register
.Negate
;
284 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
285 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
286 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
287 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
291 static INLINE
struct nv40_sreg
292 tgsi_dst(struct nv40_fpc
*fpc
, const struct tgsi_full_dst_register
*fdst
) {
293 switch (fdst
->Register
.File
) {
294 case TGSI_FILE_OUTPUT
:
295 return fpc
->r_result
[fdst
->Register
.Index
];
296 case TGSI_FILE_TEMPORARY
:
297 return fpc
->r_temp
[fdst
->Register
.Index
];
299 return nv40_sr(NV40SR_NONE
, 0);
301 NOUVEAU_ERR("bad dst file %d\n", fdst
->Register
.File
);
302 return nv40_sr(NV40SR_NONE
, 0);
311 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= MASK_X
;
312 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= MASK_Y
;
313 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= MASK_Z
;
314 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= MASK_W
;
319 src_native_swz(struct nv40_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
,
320 struct nv40_sreg
*src
)
322 const struct nv40_sreg none
= nv40_sr(NV40SR_NONE
, 0);
323 struct nv40_sreg tgsi
= tgsi_src(fpc
, fsrc
);
327 for (c
= 0; c
< 4; c
++) {
328 switch (tgsi_util_get_full_src_register_swizzle(fsrc
, c
)) {
340 if (mask
== MASK_ALL
)
346 arith(fpc
, 0, MOV
, *src
, mask
, tgsi
, none
, none
);
352 nv40_fragprog_parse_instruction(struct nv40_fpc
*fpc
,
353 const struct tgsi_full_instruction
*finst
)
355 const struct nv40_sreg none
= nv40_sr(NV40SR_NONE
, 0);
356 struct nv40_sreg src
[3], dst
, tmp
;
358 int ai
= -1, ci
= -1, ii
= -1;
361 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
364 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
365 const struct tgsi_full_src_register
*fsrc
;
367 fsrc
= &finst
->Src
[i
];
368 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
369 src
[i
] = tgsi_src(fpc
, fsrc
);
373 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
374 const struct tgsi_full_src_register
*fsrc
;
376 fsrc
= &finst
->Src
[i
];
378 switch (fsrc
->Register
.File
) {
379 case TGSI_FILE_INPUT
:
380 case TGSI_FILE_CONSTANT
:
381 case TGSI_FILE_TEMPORARY
:
382 if (!src_native_swz(fpc
, fsrc
, &src
[i
]))
389 switch (fsrc
->Register
.File
) {
390 case TGSI_FILE_INPUT
:
391 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
392 ai
= fsrc
->Register
.Index
;
393 src
[i
] = tgsi_src(fpc
, fsrc
);
396 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
397 tgsi_src(fpc
, fsrc
), none
, none
);
400 case TGSI_FILE_CONSTANT
:
401 if ((ci
== -1 && ii
== -1) ||
402 ci
== fsrc
->Register
.Index
) {
403 ci
= fsrc
->Register
.Index
;
404 src
[i
] = tgsi_src(fpc
, fsrc
);
407 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
408 tgsi_src(fpc
, fsrc
), none
, none
);
411 case TGSI_FILE_IMMEDIATE
:
412 if ((ci
== -1 && ii
== -1) ||
413 ii
== fsrc
->Register
.Index
) {
414 ii
= fsrc
->Register
.Index
;
415 src
[i
] = tgsi_src(fpc
, fsrc
);
418 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
419 tgsi_src(fpc
, fsrc
), none
, none
);
422 case TGSI_FILE_TEMPORARY
:
425 case TGSI_FILE_SAMPLER
:
426 unit
= fsrc
->Register
.Index
;
428 case TGSI_FILE_OUTPUT
:
431 NOUVEAU_ERR("bad src file\n");
436 dst
= tgsi_dst(fpc
, &finst
->Dst
[0]);
437 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
438 sat
= (finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
440 switch (finst
->Instruction
.Opcode
) {
441 case TGSI_OPCODE_ABS
:
442 arith(fpc
, sat
, MOV
, dst
, mask
, abs(src
[0]), none
, none
);
444 case TGSI_OPCODE_ADD
:
445 arith(fpc
, sat
, ADD
, dst
, mask
, src
[0], src
[1], none
);
447 case TGSI_OPCODE_CMP
:
449 arith(fpc
, sat
, MOV
, dst
, mask
, src
[2], none
, none
);
451 arith(fpc
, 0, MOV
, tmp
, 0xf, src
[0], none
, none
);
452 dst
.cc_test
= NV40_VP_INST_COND_LT
;
453 arith(fpc
, sat
, MOV
, dst
, mask
, src
[1], none
, none
);
455 case TGSI_OPCODE_COS
:
456 arith(fpc
, sat
, COS
, dst
, mask
, src
[0], none
, none
);
458 case TGSI_OPCODE_DDX
:
459 if (mask
& (MASK_Z
| MASK_W
)) {
461 arith(fpc
, sat
, DDX
, tmp
, MASK_X
| MASK_Y
,
462 swz(src
[0], Z
, W
, Z
, W
), none
, none
);
463 arith(fpc
, 0, MOV
, tmp
, MASK_Z
| MASK_W
,
464 swz(tmp
, X
, Y
, X
, Y
), none
, none
);
465 arith(fpc
, sat
, DDX
, tmp
, MASK_X
| MASK_Y
, src
[0],
467 arith(fpc
, 0, MOV
, dst
, mask
, tmp
, none
, none
);
469 arith(fpc
, sat
, DDX
, dst
, mask
, src
[0], none
, none
);
472 case TGSI_OPCODE_DDY
:
473 if (mask
& (MASK_Z
| MASK_W
)) {
475 arith(fpc
, sat
, DDY
, tmp
, MASK_X
| MASK_Y
,
476 swz(src
[0], Z
, W
, Z
, W
), none
, none
);
477 arith(fpc
, 0, MOV
, tmp
, MASK_Z
| MASK_W
,
478 swz(tmp
, X
, Y
, X
, Y
), none
, none
);
479 arith(fpc
, sat
, DDY
, tmp
, MASK_X
| MASK_Y
, src
[0],
481 arith(fpc
, 0, MOV
, dst
, mask
, tmp
, none
, none
);
483 arith(fpc
, sat
, DDY
, dst
, mask
, src
[0], none
, none
);
486 case TGSI_OPCODE_DP3
:
487 arith(fpc
, sat
, DP3
, dst
, mask
, src
[0], src
[1], none
);
489 case TGSI_OPCODE_DP4
:
490 arith(fpc
, sat
, DP4
, dst
, mask
, src
[0], src
[1], none
);
492 case TGSI_OPCODE_DPH
:
494 arith(fpc
, 0, DP3
, tmp
, MASK_X
, src
[0], src
[1], none
);
495 arith(fpc
, sat
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
),
496 swz(src
[1], W
, W
, W
, W
), none
);
498 case TGSI_OPCODE_DST
:
499 arith(fpc
, sat
, DST
, dst
, mask
, src
[0], src
[1], none
);
501 case TGSI_OPCODE_EX2
:
502 arith(fpc
, sat
, EX2
, dst
, mask
, src
[0], none
, none
);
504 case TGSI_OPCODE_FLR
:
505 arith(fpc
, sat
, FLR
, dst
, mask
, src
[0], none
, none
);
507 case TGSI_OPCODE_FRC
:
508 arith(fpc
, sat
, FRC
, dst
, mask
, src
[0], none
, none
);
510 case TGSI_OPCODE_KILP
:
511 arith(fpc
, 0, KIL
, none
, 0, none
, none
, none
);
513 case TGSI_OPCODE_KIL
:
514 dst
= nv40_sr(NV40SR_NONE
, 0);
516 arith(fpc
, 0, MOV
, dst
, MASK_ALL
, src
[0], none
, none
);
517 dst
.cc_update
= 0; dst
.cc_test
= NV40_FP_OP_COND_LT
;
518 arith(fpc
, 0, KIL
, dst
, 0, none
, none
, none
);
520 case TGSI_OPCODE_LG2
:
521 arith(fpc
, sat
, LG2
, dst
, mask
, src
[0], none
, none
);
523 // case TGSI_OPCODE_LIT:
524 case TGSI_OPCODE_LRP
:
526 arith(fpc
, 0, MAD
, tmp
, mask
, neg(src
[0]), src
[2], src
[2]);
527 arith(fpc
, sat
, MAD
, dst
, mask
, src
[0], src
[1], tmp
);
529 case TGSI_OPCODE_MAD
:
530 arith(fpc
, sat
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]);
532 case TGSI_OPCODE_MAX
:
533 arith(fpc
, sat
, MAX
, dst
, mask
, src
[0], src
[1], none
);
535 case TGSI_OPCODE_MIN
:
536 arith(fpc
, sat
, MIN
, dst
, mask
, src
[0], src
[1], none
);
538 case TGSI_OPCODE_MOV
:
539 arith(fpc
, sat
, MOV
, dst
, mask
, src
[0], none
, none
);
541 case TGSI_OPCODE_MUL
:
542 arith(fpc
, sat
, MUL
, dst
, mask
, src
[0], src
[1], none
);
544 case TGSI_OPCODE_POW
:
546 arith(fpc
, 0, LG2
, tmp
, MASK_X
,
547 swz(src
[0], X
, X
, X
, X
), none
, none
);
548 arith(fpc
, 0, MUL
, tmp
, MASK_X
, swz(tmp
, X
, X
, X
, X
),
549 swz(src
[1], X
, X
, X
, X
), none
);
550 arith(fpc
, sat
, EX2
, dst
, mask
,
551 swz(tmp
, X
, X
, X
, X
), none
, none
);
553 case TGSI_OPCODE_RCP
:
554 arith(fpc
, sat
, RCP
, dst
, mask
, src
[0], none
, none
);
556 case TGSI_OPCODE_RET
:
559 case TGSI_OPCODE_RFL
:
561 arith(fpc
, 0, DP3
, tmp
, MASK_X
, src
[0], src
[0], none
);
562 arith(fpc
, 0, DP3
, tmp
, MASK_Y
, src
[0], src
[1], none
);
563 arith(fpc
, 0, DIV
, scale(tmp
, 2X
), MASK_Z
,
564 swz(tmp
, Y
, Y
, Y
, Y
), swz(tmp
, X
, X
, X
, X
), none
);
565 arith(fpc
, sat
, MAD
, dst
, mask
,
566 swz(tmp
, Z
, Z
, Z
, Z
), src
[0], neg(src
[1]));
568 case TGSI_OPCODE_RSQ
:
570 arith(fpc
, 0, LG2
, scale(tmp
, INV_2X
), MASK_X
,
571 abs(swz(src
[0], X
, X
, X
, X
)), none
, none
);
572 arith(fpc
, sat
, EX2
, dst
, mask
,
573 neg(swz(tmp
, X
, X
, X
, X
)), none
, none
);
575 case TGSI_OPCODE_SCS
:
577 arith(fpc
, sat
, COS
, dst
, MASK_X
,
578 swz(src
[0], X
, X
, X
, X
), none
, none
);
581 arith(fpc
, sat
, SIN
, dst
, MASK_Y
,
582 swz(src
[0], X
, X
, X
, X
), none
, none
);
585 case TGSI_OPCODE_SEQ
:
586 arith(fpc
, sat
, SEQ
, dst
, mask
, src
[0], src
[1], none
);
588 case TGSI_OPCODE_SFL
:
589 arith(fpc
, sat
, SFL
, dst
, mask
, src
[0], src
[1], none
);
591 case TGSI_OPCODE_SGE
:
592 arith(fpc
, sat
, SGE
, dst
, mask
, src
[0], src
[1], none
);
594 case TGSI_OPCODE_SGT
:
595 arith(fpc
, sat
, SGT
, dst
, mask
, src
[0], src
[1], none
);
597 case TGSI_OPCODE_SIN
:
598 arith(fpc
, sat
, SIN
, dst
, mask
, src
[0], none
, none
);
600 case TGSI_OPCODE_SLE
:
601 arith(fpc
, sat
, SLE
, dst
, mask
, src
[0], src
[1], none
);
603 case TGSI_OPCODE_SLT
:
604 arith(fpc
, sat
, SLT
, dst
, mask
, src
[0], src
[1], none
);
606 case TGSI_OPCODE_SNE
:
607 arith(fpc
, sat
, SNE
, dst
, mask
, src
[0], src
[1], none
);
609 case TGSI_OPCODE_STR
:
610 arith(fpc
, sat
, STR
, dst
, mask
, src
[0], src
[1], none
);
612 case TGSI_OPCODE_SUB
:
613 arith(fpc
, sat
, ADD
, dst
, mask
, src
[0], neg(src
[1]), none
);
615 case TGSI_OPCODE_TEX
:
616 tex(fpc
, sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
);
618 case TGSI_OPCODE_TXB
:
619 tex(fpc
, sat
, TXB
, unit
, dst
, mask
, src
[0], none
, none
);
621 case TGSI_OPCODE_TXP
:
622 tex(fpc
, sat
, TXP
, unit
, dst
, mask
, src
[0], none
, none
);
624 case TGSI_OPCODE_XPD
:
626 arith(fpc
, 0, MUL
, tmp
, mask
,
627 swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
);
628 arith(fpc
, sat
, MAD
, dst
, (mask
& ~MASK_W
),
629 swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
),
633 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
642 nv40_fragprog_parse_decl_attrib(struct nv40_fpc
*fpc
,
643 const struct tgsi_full_declaration
*fdec
)
647 switch (fdec
->Semantic
.Name
) {
648 case TGSI_SEMANTIC_POSITION
:
649 hw
= NV40_FP_OP_INPUT_SRC_POSITION
;
651 case TGSI_SEMANTIC_COLOR
:
652 if (fdec
->Semantic
.Index
== 0) {
653 hw
= NV40_FP_OP_INPUT_SRC_COL0
;
655 if (fdec
->Semantic
.Index
== 1) {
656 hw
= NV40_FP_OP_INPUT_SRC_COL1
;
658 NOUVEAU_ERR("bad colour semantic index\n");
662 case TGSI_SEMANTIC_FOG
:
663 hw
= NV40_FP_OP_INPUT_SRC_FOGC
;
665 case TGSI_SEMANTIC_GENERIC
:
666 if (fdec
->Semantic
.Index
<= 7) {
667 hw
= NV40_FP_OP_INPUT_SRC_TC(fdec
->Semantic
.
670 NOUVEAU_ERR("bad generic semantic index\n");
675 NOUVEAU_ERR("bad input semantic\n");
679 fpc
->attrib_map
[fdec
->Range
.First
] = hw
;
684 nv40_fragprog_parse_decl_output(struct nv40_fpc
*fpc
,
685 const struct tgsi_full_declaration
*fdec
)
687 unsigned idx
= fdec
->Range
.First
;
690 switch (fdec
->Semantic
.Name
) {
691 case TGSI_SEMANTIC_POSITION
:
694 case TGSI_SEMANTIC_COLOR
:
695 switch (fdec
->Semantic
.Index
) {
696 case 0: hw
= 0; break;
697 case 1: hw
= 2; break;
698 case 2: hw
= 3; break;
699 case 3: hw
= 4; break;
701 NOUVEAU_ERR("bad rcol index\n");
706 NOUVEAU_ERR("bad output semantic\n");
710 fpc
->r_result
[idx
] = nv40_sr(NV40SR_OUTPUT
, hw
);
711 fpc
->r_temps
|= (1 << hw
);
716 nv40_fragprog_prepare(struct nv40_fpc
*fpc
)
718 struct tgsi_parse_context p
;
719 int high_temp
= -1, i
;
721 tgsi_parse_init(&p
, fpc
->fp
->pipe
.tokens
);
722 while (!tgsi_parse_end_of_tokens(&p
)) {
723 const union tgsi_full_token
*tok
= &p
.FullToken
;
725 tgsi_parse_token(&p
);
726 switch(tok
->Token
.Type
) {
727 case TGSI_TOKEN_TYPE_DECLARATION
:
729 const struct tgsi_full_declaration
*fdec
;
730 fdec
= &p
.FullToken
.FullDeclaration
;
731 switch (fdec
->Declaration
.File
) {
732 case TGSI_FILE_INPUT
:
733 if (!nv40_fragprog_parse_decl_attrib(fpc
, fdec
))
736 case TGSI_FILE_OUTPUT
:
737 if (!nv40_fragprog_parse_decl_output(fpc
, fdec
))
740 case TGSI_FILE_TEMPORARY
:
741 if (fdec
->Range
.Last
> high_temp
) {
751 case TGSI_TOKEN_TYPE_IMMEDIATE
:
753 struct tgsi_full_immediate
*imm
;
756 imm
= &p
.FullToken
.FullImmediate
;
757 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
758 assert(fpc
->nr_imm
< MAX_IMM
);
760 vals
[0] = imm
->u
[0].Float
;
761 vals
[1] = imm
->u
[1].Float
;
762 vals
[2] = imm
->u
[2].Float
;
763 vals
[3] = imm
->u
[3].Float
;
764 fpc
->imm
[fpc
->nr_imm
++] = constant(fpc
, -1, vals
);
774 fpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nv40_sreg
));
775 for (i
= 0; i
< high_temp
; i
++)
776 fpc
->r_temp
[i
] = temp(fpc
);
777 fpc
->r_temps_discard
= 0;
790 nv40_fragprog_translate(struct nv40_context
*nv40
,
791 struct nv40_fragment_program
*fp
)
793 struct tgsi_parse_context parse
;
794 struct nv40_fpc
*fpc
= NULL
;
796 fpc
= CALLOC(1, sizeof(struct nv40_fpc
));
802 if (!nv40_fragprog_prepare(fpc
)) {
807 tgsi_parse_init(&parse
, fp
->pipe
.tokens
);
809 while (!tgsi_parse_end_of_tokens(&parse
)) {
810 tgsi_parse_token(&parse
);
812 switch (parse
.FullToken
.Token
.Type
) {
813 case TGSI_TOKEN_TYPE_INSTRUCTION
:
815 const struct tgsi_full_instruction
*finst
;
817 finst
= &parse
.FullToken
.FullInstruction
;
818 if (!nv40_fragprog_parse_instruction(fpc
, finst
))
827 fp
->fp_control
|= fpc
->num_regs
<< NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT
;
829 /* Terminate final instruction */
830 fp
->insn
[fpc
->inst_offset
] |= 0x00000001;
832 /* Append NOP + END instruction, may or may not be necessary. */
833 fpc
->inst_offset
= fp
->insn_len
;
835 fp
->insn
[fpc
->inst_offset
+ 0] = 0x00000001;
836 fp
->insn
[fpc
->inst_offset
+ 1] = 0x00000000;
837 fp
->insn
[fpc
->inst_offset
+ 2] = 0x00000000;
838 fp
->insn
[fpc
->inst_offset
+ 3] = 0x00000000;
840 fp
->translated
= TRUE
;
842 tgsi_parse_free(&parse
);
849 nv40_fragprog_upload(struct nv40_context
*nv40
,
850 struct nv40_fragment_program
*fp
)
852 struct pipe_screen
*pscreen
= nv40
->pipe
.screen
;
853 const uint32_t le
= 1;
857 map
= pipe_buffer_map(pscreen
, fp
->buffer
, PIPE_BUFFER_USAGE_CPU_WRITE
);
860 for (i
= 0; i
< fp
->insn_len
; i
++) {
861 fflush(stdout
); fflush(stderr
);
862 NOUVEAU_ERR("%d 0x%08x\n", i
, fp
->insn
[i
]);
863 fflush(stdout
); fflush(stderr
);
867 if ((*(const uint8_t *)&le
)) {
868 for (i
= 0; i
< fp
->insn_len
; i
++) {
869 map
[i
] = fp
->insn
[i
];
872 /* Weird swapping for big-endian chips */
873 for (i
= 0; i
< fp
->insn_len
; i
++) {
874 map
[i
] = ((fp
->insn
[i
] & 0xffff) << 16) |
875 ((fp
->insn
[i
] >> 16) & 0xffff);
879 pipe_buffer_unmap(pscreen
, fp
->buffer
);
883 nv40_fragprog_validate(struct nv40_context
*nv40
)
885 struct nv40_fragment_program
*fp
= nv40
->fragprog
;
886 struct pipe_buffer
*constbuf
=
887 nv40
->constbuf
[PIPE_SHADER_FRAGMENT
];
888 struct pipe_screen
*pscreen
= nv40
->pipe
.screen
;
889 struct nouveau_stateobj
*so
;
890 boolean new_consts
= FALSE
;
894 goto update_constants
;
896 nv40
->fallback_swrast
&= ~NV40_NEW_FRAGPROG
;
897 nv40_fragprog_translate(nv40
, fp
);
898 if (!fp
->translated
) {
899 nv40
->fallback_swrast
|= NV40_NEW_FRAGPROG
;
903 fp
->buffer
= pscreen
->buffer_create(pscreen
, 0x100, 0, fp
->insn_len
* 4);
904 nv40_fragprog_upload(nv40
, fp
);
907 so_method(so
, nv40
->screen
->curie
, NV40TCL_FP_ADDRESS
, 1);
908 so_reloc (so
, nouveau_bo(fp
->buffer
), 0, NOUVEAU_BO_VRAM
|
909 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
|
910 NOUVEAU_BO_OR
, NV40TCL_FP_ADDRESS_DMA0
,
911 NV40TCL_FP_ADDRESS_DMA1
);
912 so_method(so
, nv40
->screen
->curie
, NV40TCL_FP_CONTROL
, 1);
913 so_data (so
, fp
->fp_control
);
921 map
= pipe_buffer_map(pscreen
, constbuf
,
922 PIPE_BUFFER_USAGE_CPU_READ
);
923 for (i
= 0; i
< fp
->nr_consts
; i
++) {
924 struct nv40_fragment_program_data
*fpd
= &fp
->consts
[i
];
925 uint32_t *p
= &fp
->insn
[fpd
->offset
];
926 uint32_t *cb
= (uint32_t *)&map
[fpd
->index
* 4];
928 if (!memcmp(p
, cb
, 4 * sizeof(float)))
930 memcpy(p
, cb
, 4 * sizeof(float));
933 pipe_buffer_unmap(pscreen
, constbuf
);
936 nv40_fragprog_upload(nv40
, fp
);
939 if (new_consts
|| fp
->so
!= nv40
->state
.hw
[NV40_STATE_FRAGPROG
]) {
940 so_ref(fp
->so
, &nv40
->state
.hw
[NV40_STATE_FRAGPROG
]);
948 nv40_fragprog_destroy(struct nv40_context
*nv40
,
949 struct nv40_fragment_program
*fp
)
955 struct nv40_state_entry nv40_state_fragprog
= {
956 .validate
= nv40_fragprog_validate
,
958 .pipe
= NV40_NEW_FRAGPROG
,
959 .hw
= NV40_STATE_FRAGPROG