1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
5 #include "pipe/p_shader_tokens.h"
6 #include "tgsi/util/tgsi_parse.h"
7 #include "tgsi/util/tgsi_util.h"
9 #include "nv40_context.h"
19 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
20 #define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
21 #define DEF_CTEST NV40_FP_OP_COND_TR
22 #include "nv40_shader.h"
24 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
25 #define neg(s) nv40_sr_neg((s))
26 #define abs(s) nv40_sr_abs((s))
27 #define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
29 #define MAX_CONSTS 128
32 struct nv40_fragment_program
*fp
;
34 uint attrib_map
[PIPE_MAX_SHADER_INPUTS
];
37 unsigned r_temps_discard
;
38 struct nv40_sreg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
39 struct nv40_sreg
*r_temp
;
52 struct nv40_sreg imm
[MAX_IMM
];
56 static INLINE
struct nv40_sreg
57 temp(struct nv40_fpc
*fpc
)
59 int idx
= ffs(~fpc
->r_temps
) - 1;
62 NOUVEAU_ERR("out of temps!!\n");
64 return nv40_sr(NV40SR_TEMP
, 0);
67 fpc
->r_temps
|= (1 << idx
);
68 fpc
->r_temps_discard
|= (1 << idx
);
69 return nv40_sr(NV40SR_TEMP
, idx
);
73 release_temps(struct nv40_fpc
*fpc
)
75 fpc
->r_temps
&= ~fpc
->r_temps_discard
;
76 fpc
->r_temps_discard
= 0;
79 static INLINE
struct nv40_sreg
80 constant(struct nv40_fpc
*fpc
, int pipe
, float vals
[4])
84 if (fpc
->nr_consts
== MAX_CONSTS
)
86 idx
= fpc
->nr_consts
++;
88 fpc
->consts
[idx
].pipe
= pipe
;
90 memcpy(fpc
->consts
[idx
].vals
, vals
, 4 * sizeof(float));
91 return nv40_sr(NV40SR_CONST
, idx
);
94 #define arith(cc,s,o,d,m,s0,s1,s2) \
95 nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
96 (d), (m), (s0), (s1), (s2))
97 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
98 nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
99 (d), (m), (s0), none, none)
102 grow_insns(struct nv40_fpc
*fpc
, int size
)
104 struct nv40_fragment_program
*fp
= fpc
->fp
;
106 fp
->insn_len
+= size
;
107 fp
->insn
= realloc(fp
->insn
, sizeof(uint32_t) * fp
->insn_len
);
111 emit_src(struct nv40_fpc
*fpc
, int pos
, struct nv40_sreg src
)
113 struct nv40_fragment_program
*fp
= fpc
->fp
;
114 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
119 sr
|= (NV40_FP_REG_TYPE_INPUT
<< NV40_FP_REG_TYPE_SHIFT
);
120 hw
[0] |= (src
.index
<< NV40_FP_OP_INPUT_SRC_SHIFT
);
123 sr
|= NV40_FP_REG_SRC_HALF
;
126 sr
|= (NV40_FP_REG_TYPE_TEMP
<< NV40_FP_REG_TYPE_SHIFT
);
127 sr
|= (src
.index
<< NV40_FP_REG_SRC_SHIFT
);
130 if (!fpc
->have_const
) {
135 hw
= &fp
->insn
[fpc
->inst_offset
];
136 if (fpc
->consts
[src
.index
].pipe
>= 0) {
137 struct nv40_fragment_program_data
*fpd
;
139 fp
->consts
= realloc(fp
->consts
, ++fp
->nr_consts
*
141 fpd
= &fp
->consts
[fp
->nr_consts
- 1];
142 fpd
->offset
= fpc
->inst_offset
+ 4;
143 fpd
->index
= fpc
->consts
[src
.index
].pipe
;
144 memset(&fp
->insn
[fpd
->offset
], 0, sizeof(uint32_t) * 4);
146 memcpy(&fp
->insn
[fpc
->inst_offset
+ 4],
147 fpc
->consts
[src
.index
].vals
,
148 sizeof(uint32_t) * 4);
151 sr
|= (NV40_FP_REG_TYPE_CONST
<< NV40_FP_REG_TYPE_SHIFT
);
154 sr
|= (NV40_FP_REG_TYPE_INPUT
<< NV40_FP_REG_TYPE_SHIFT
);
161 sr
|= NV40_FP_REG_NEGATE
;
164 hw
[1] |= (1 << (29 + pos
));
166 sr
|= ((src
.swz
[0] << NV40_FP_REG_SWZ_X_SHIFT
) |
167 (src
.swz
[1] << NV40_FP_REG_SWZ_Y_SHIFT
) |
168 (src
.swz
[2] << NV40_FP_REG_SWZ_Z_SHIFT
) |
169 (src
.swz
[3] << NV40_FP_REG_SWZ_W_SHIFT
));
175 emit_dst(struct nv40_fpc
*fpc
, struct nv40_sreg dst
)
177 struct nv40_fragment_program
*fp
= fpc
->fp
;
178 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
182 if (fpc
->num_regs
< (dst
.index
+ 1))
183 fpc
->num_regs
= dst
.index
+ 1;
186 if (dst
.index
== 1) {
187 fp
->fp_control
|= 0xe;
189 hw
[0] |= NV40_FP_OP_OUT_REG_HALF
;
199 hw
[0] |= (dst
.index
<< NV40_FP_OP_OUT_REG_SHIFT
);
203 nv40_fp_arith(struct nv40_fpc
*fpc
, int sat
, int op
,
204 struct nv40_sreg dst
, int mask
,
205 struct nv40_sreg s0
, struct nv40_sreg s1
, struct nv40_sreg s2
)
207 struct nv40_fragment_program
*fp
= fpc
->fp
;
210 fpc
->inst_offset
= fp
->insn_len
;
213 hw
= &fp
->insn
[fpc
->inst_offset
];
214 memset(hw
, 0, sizeof(uint32_t) * 4);
216 if (op
== NV40_FP_OP_OPCODE_KIL
)
217 fp
->fp_control
|= NV40TCL_FP_CONTROL_KIL
;
218 hw
[0] |= (op
<< NV40_FP_OP_OPCODE_SHIFT
);
219 hw
[0] |= (mask
<< NV40_FP_OP_OUTMASK_SHIFT
);
220 hw
[2] |= (dst
.dst_scale
<< NV40_FP_OP_DST_SCALE_SHIFT
);
223 hw
[0] |= NV40_FP_OP_OUT_SAT
;
226 hw
[0] |= NV40_FP_OP_COND_WRITE_ENABLE
;
227 hw
[1] |= (dst
.cc_test
<< NV40_FP_OP_COND_SHIFT
);
228 hw
[1] |= ((dst
.cc_swz
[0] << NV40_FP_OP_COND_SWZ_X_SHIFT
) |
229 (dst
.cc_swz
[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT
) |
230 (dst
.cc_swz
[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT
) |
231 (dst
.cc_swz
[3] << NV40_FP_OP_COND_SWZ_W_SHIFT
));
234 emit_src(fpc
, 0, s0
);
235 emit_src(fpc
, 1, s1
);
236 emit_src(fpc
, 2, s2
);
240 nv40_fp_tex(struct nv40_fpc
*fpc
, int sat
, int op
, int unit
,
241 struct nv40_sreg dst
, int mask
,
242 struct nv40_sreg s0
, struct nv40_sreg s1
, struct nv40_sreg s2
)
244 struct nv40_fragment_program
*fp
= fpc
->fp
;
246 nv40_fp_arith(fpc
, sat
, op
, dst
, mask
, s0
, s1
, s2
);
248 fp
->insn
[fpc
->inst_offset
] |= (unit
<< NV40_FP_OP_TEX_UNIT_SHIFT
);
249 fp
->samplers
|= (1 << unit
);
252 static INLINE
struct nv40_sreg
253 tgsi_src(struct nv40_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
)
255 struct nv40_sreg src
;
257 switch (fsrc
->SrcRegister
.File
) {
258 case TGSI_FILE_INPUT
:
259 src
= nv40_sr(NV40SR_INPUT
,
260 fpc
->attrib_map
[fsrc
->SrcRegister
.Index
]);
262 case TGSI_FILE_CONSTANT
:
263 src
= constant(fpc
, fsrc
->SrcRegister
.Index
, NULL
);
265 case TGSI_FILE_IMMEDIATE
:
266 assert(fsrc
->SrcRegister
.Index
< fpc
->nr_imm
);
267 src
= fpc
->imm
[fsrc
->SrcRegister
.Index
];
269 case TGSI_FILE_TEMPORARY
:
270 src
= fpc
->r_temp
[fsrc
->SrcRegister
.Index
];
272 /* NV40 fragprog result regs are just temps, so this is simple */
273 case TGSI_FILE_OUTPUT
:
274 src
= fpc
->r_result
[fsrc
->SrcRegister
.Index
];
277 NOUVEAU_ERR("bad src file\n");
281 src
.abs
= fsrc
->SrcRegisterExtMod
.Absolute
;
282 src
.negate
= fsrc
->SrcRegister
.Negate
;
283 src
.swz
[0] = fsrc
->SrcRegister
.SwizzleX
;
284 src
.swz
[1] = fsrc
->SrcRegister
.SwizzleY
;
285 src
.swz
[2] = fsrc
->SrcRegister
.SwizzleZ
;
286 src
.swz
[3] = fsrc
->SrcRegister
.SwizzleW
;
290 static INLINE
struct nv40_sreg
291 tgsi_dst(struct nv40_fpc
*fpc
, const struct tgsi_full_dst_register
*fdst
) {
292 switch (fdst
->DstRegister
.File
) {
293 case TGSI_FILE_OUTPUT
:
294 return fpc
->r_result
[fdst
->DstRegister
.Index
];
295 case TGSI_FILE_TEMPORARY
:
296 return fpc
->r_temp
[fdst
->DstRegister
.Index
];
298 return nv40_sr(NV40SR_NONE
, 0);
300 NOUVEAU_ERR("bad dst file %d\n", fdst
->DstRegister
.File
);
301 return nv40_sr(NV40SR_NONE
, 0);
310 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= MASK_X
;
311 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= MASK_Y
;
312 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= MASK_Z
;
313 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= MASK_W
;
318 src_native_swz(struct nv40_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
,
319 struct nv40_sreg
*src
)
321 const struct nv40_sreg none
= nv40_sr(NV40SR_NONE
, 0);
322 struct nv40_sreg tgsi
= tgsi_src(fpc
, fsrc
);
323 uint mask
= 0, zero_mask
= 0, one_mask
= 0, neg_mask
= 0;
324 uint neg
[4] = { fsrc
->SrcRegisterExtSwz
.NegateX
,
325 fsrc
->SrcRegisterExtSwz
.NegateY
,
326 fsrc
->SrcRegisterExtSwz
.NegateZ
,
327 fsrc
->SrcRegisterExtSwz
.NegateW
};
330 for (c
= 0; c
< 4; c
++) {
331 switch (tgsi_util_get_full_src_register_extswizzle(fsrc
, c
)) {
332 case TGSI_EXTSWIZZLE_X
:
333 case TGSI_EXTSWIZZLE_Y
:
334 case TGSI_EXTSWIZZLE_Z
:
335 case TGSI_EXTSWIZZLE_W
:
338 case TGSI_EXTSWIZZLE_ZERO
:
339 zero_mask
|= (1 << c
);
342 case TGSI_EXTSWIZZLE_ONE
:
343 one_mask
|= (1 << c
);
350 if (!tgsi
.negate
&& neg
[c
])
351 neg_mask
|= (1 << c
);
354 if (mask
== MASK_ALL
&& !neg_mask
)
360 arith(fpc
, 0, MOV
, *src
, mask
, tgsi
, none
, none
);
363 arith(fpc
, 0, SFL
, *src
, zero_mask
, *src
, none
, none
);
366 arith(fpc
, 0, STR
, *src
, one_mask
, *src
, none
, none
);
369 struct nv40_sreg one
= temp(fpc
);
370 arith(fpc
, 0, STR
, one
, neg_mask
, one
, none
, none
);
371 arith(fpc
, 0, MUL
, *src
, neg_mask
, *src
, neg(one
), none
);
378 nv40_fragprog_parse_instruction(struct nv40_fpc
*fpc
,
379 const struct tgsi_full_instruction
*finst
)
381 const struct nv40_sreg none
= nv40_sr(NV40SR_NONE
, 0);
382 struct nv40_sreg src
[3], dst
, tmp
;
384 int ai
= -1, ci
= -1, ii
= -1;
387 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
390 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
391 const struct tgsi_full_src_register
*fsrc
;
393 fsrc
= &finst
->FullSrcRegisters
[i
];
394 if (fsrc
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
) {
395 src
[i
] = tgsi_src(fpc
, fsrc
);
399 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
400 const struct tgsi_full_src_register
*fsrc
;
402 fsrc
= &finst
->FullSrcRegisters
[i
];
404 switch (fsrc
->SrcRegister
.File
) {
405 case TGSI_FILE_INPUT
:
406 case TGSI_FILE_CONSTANT
:
407 case TGSI_FILE_TEMPORARY
:
408 if (!src_native_swz(fpc
, fsrc
, &src
[i
]))
415 switch (fsrc
->SrcRegister
.File
) {
416 case TGSI_FILE_INPUT
:
417 if (ai
== -1 || ai
== fsrc
->SrcRegister
.Index
) {
418 ai
= fsrc
->SrcRegister
.Index
;
419 src
[i
] = tgsi_src(fpc
, fsrc
);
422 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
423 tgsi_src(fpc
, fsrc
), none
, none
);
426 case TGSI_FILE_CONSTANT
:
427 if ((ci
== -1 && ii
== -1) ||
428 ci
== fsrc
->SrcRegister
.Index
) {
429 ci
= fsrc
->SrcRegister
.Index
;
430 src
[i
] = tgsi_src(fpc
, fsrc
);
433 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
434 tgsi_src(fpc
, fsrc
), none
, none
);
437 case TGSI_FILE_IMMEDIATE
:
438 if ((ci
== -1 && ii
== -1) ||
439 ii
== fsrc
->SrcRegister
.Index
) {
440 ii
= fsrc
->SrcRegister
.Index
;
441 src
[i
] = tgsi_src(fpc
, fsrc
);
444 arith(fpc
, 0, MOV
, src
[i
], MASK_ALL
,
445 tgsi_src(fpc
, fsrc
), none
, none
);
448 case TGSI_FILE_TEMPORARY
:
451 case TGSI_FILE_SAMPLER
:
452 unit
= fsrc
->SrcRegister
.Index
;
454 case TGSI_FILE_OUTPUT
:
457 NOUVEAU_ERR("bad src file\n");
462 dst
= tgsi_dst(fpc
, &finst
->FullDstRegisters
[0]);
463 mask
= tgsi_mask(finst
->FullDstRegisters
[0].DstRegister
.WriteMask
);
464 sat
= (finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
466 switch (finst
->Instruction
.Opcode
) {
467 case TGSI_OPCODE_ABS
:
468 arith(fpc
, sat
, MOV
, dst
, mask
, abs(src
[0]), none
, none
);
470 case TGSI_OPCODE_ADD
:
471 arith(fpc
, sat
, ADD
, dst
, mask
, src
[0], src
[1], none
);
473 case TGSI_OPCODE_CMP
:
475 arith(fpc
, sat
, MOV
, dst
, mask
, src
[2], none
, none
);
477 arith(fpc
, 0, MOV
, tmp
, 0xf, src
[0], none
, none
);
478 dst
.cc_test
= NV40_VP_INST_COND_LT
;
479 arith(fpc
, sat
, MOV
, dst
, mask
, src
[1], none
, none
);
481 case TGSI_OPCODE_COS
:
482 arith(fpc
, sat
, COS
, dst
, mask
, src
[0], none
, none
);
484 case TGSI_OPCODE_DDX
:
485 if (mask
& (MASK_Z
| MASK_W
)) {
487 arith(fpc
, sat
, DDX
, tmp
, MASK_X
| MASK_Y
,
488 swz(src
[0], Z
, W
, Z
, W
), none
, none
);
489 arith(fpc
, 0, MOV
, tmp
, MASK_Z
| MASK_W
,
490 swz(tmp
, X
, Y
, X
, Y
), none
, none
);
491 arith(fpc
, sat
, DDX
, tmp
, MASK_X
| MASK_Y
, src
[0],
493 arith(fpc
, 0, MOV
, dst
, mask
, tmp
, none
, none
);
495 arith(fpc
, sat
, DDX
, dst
, mask
, src
[0], none
, none
);
498 case TGSI_OPCODE_DDY
:
499 if (mask
& (MASK_Z
| MASK_W
)) {
501 arith(fpc
, sat
, DDY
, tmp
, MASK_X
| MASK_Y
,
502 swz(src
[0], Z
, W
, Z
, W
), none
, none
);
503 arith(fpc
, 0, MOV
, tmp
, MASK_Z
| MASK_W
,
504 swz(tmp
, X
, Y
, X
, Y
), none
, none
);
505 arith(fpc
, sat
, DDY
, tmp
, MASK_X
| MASK_Y
, src
[0],
507 arith(fpc
, 0, MOV
, dst
, mask
, tmp
, none
, none
);
509 arith(fpc
, sat
, DDY
, dst
, mask
, src
[0], none
, none
);
512 case TGSI_OPCODE_DP3
:
513 arith(fpc
, sat
, DP3
, dst
, mask
, src
[0], src
[1], none
);
515 case TGSI_OPCODE_DP4
:
516 arith(fpc
, sat
, DP4
, dst
, mask
, src
[0], src
[1], none
);
518 case TGSI_OPCODE_DPH
:
520 arith(fpc
, 0, DP3
, tmp
, MASK_X
, src
[0], src
[1], none
);
521 arith(fpc
, sat
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
),
522 swz(src
[1], W
, W
, W
, W
), none
);
524 case TGSI_OPCODE_DST
:
525 arith(fpc
, sat
, DST
, dst
, mask
, src
[0], src
[1], none
);
527 case TGSI_OPCODE_EX2
:
528 arith(fpc
, sat
, EX2
, dst
, mask
, src
[0], none
, none
);
530 case TGSI_OPCODE_FLR
:
531 arith(fpc
, sat
, FLR
, dst
, mask
, src
[0], none
, none
);
533 case TGSI_OPCODE_FRC
:
534 arith(fpc
, sat
, FRC
, dst
, mask
, src
[0], none
, none
);
536 case TGSI_OPCODE_KIL
:
537 arith(fpc
, 0, KIL
, none
, 0, none
, none
, none
);
539 case TGSI_OPCODE_KILP
:
540 dst
= nv40_sr(NV40SR_NONE
, 0);
542 arith(fpc
, 0, MOV
, dst
, MASK_ALL
, src
[0], none
, none
);
543 dst
.cc_update
= 0; dst
.cc_test
= NV40_FP_OP_COND_LT
;
544 arith(fpc
, 0, KIL
, dst
, 0, none
, none
, none
);
546 case TGSI_OPCODE_LG2
:
547 arith(fpc
, sat
, LG2
, dst
, mask
, src
[0], none
, none
);
549 // case TGSI_OPCODE_LIT:
550 case TGSI_OPCODE_LRP
:
552 arith(fpc
, 0, MAD
, tmp
, mask
, neg(src
[0]), src
[2], src
[2]);
553 arith(fpc
, sat
, MAD
, dst
, mask
, src
[0], src
[1], tmp
);
555 case TGSI_OPCODE_MAD
:
556 arith(fpc
, sat
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]);
558 case TGSI_OPCODE_MAX
:
559 arith(fpc
, sat
, MAX
, dst
, mask
, src
[0], src
[1], none
);
561 case TGSI_OPCODE_MIN
:
562 arith(fpc
, sat
, MIN
, dst
, mask
, src
[0], src
[1], none
);
564 case TGSI_OPCODE_MOV
:
565 arith(fpc
, sat
, MOV
, dst
, mask
, src
[0], none
, none
);
567 case TGSI_OPCODE_MUL
:
568 arith(fpc
, sat
, MUL
, dst
, mask
, src
[0], src
[1], none
);
570 case TGSI_OPCODE_NOISE1
:
571 case TGSI_OPCODE_NOISE2
:
572 case TGSI_OPCODE_NOISE3
:
573 case TGSI_OPCODE_NOISE4
:
574 arith(fpc
, sat
, SFL
, dst
, mask
, none
, none
, none
);
576 case TGSI_OPCODE_POW
:
578 arith(fpc
, 0, LG2
, tmp
, MASK_X
,
579 swz(src
[0], X
, X
, X
, X
), none
, none
);
580 arith(fpc
, 0, MUL
, tmp
, MASK_X
, swz(tmp
, X
, X
, X
, X
),
581 swz(src
[1], X
, X
, X
, X
), none
);
582 arith(fpc
, sat
, EX2
, dst
, mask
,
583 swz(tmp
, X
, X
, X
, X
), none
, none
);
585 case TGSI_OPCODE_RCP
:
586 arith(fpc
, sat
, RCP
, dst
, mask
, src
[0], none
, none
);
588 case TGSI_OPCODE_RET
:
591 case TGSI_OPCODE_RFL
:
593 arith(fpc
, 0, DP3
, tmp
, MASK_X
, src
[0], src
[0], none
);
594 arith(fpc
, 0, DP3
, tmp
, MASK_Y
, src
[0], src
[1], none
);
595 arith(fpc
, 0, DIV
, scale(tmp
, 2X
), MASK_Z
,
596 swz(tmp
, Y
, Y
, Y
, Y
), swz(tmp
, X
, X
, X
, X
), none
);
597 arith(fpc
, sat
, MAD
, dst
, mask
,
598 swz(tmp
, Z
, Z
, Z
, Z
), src
[0], neg(src
[1]));
600 case TGSI_OPCODE_RSQ
:
602 arith(fpc
, 0, LG2
, scale(tmp
, INV_2X
), MASK_X
,
603 abs(swz(src
[0], X
, X
, X
, X
)), none
, none
);
604 arith(fpc
, sat
, EX2
, dst
, mask
,
605 neg(swz(tmp
, X
, X
, X
, X
)), none
, none
);
607 case TGSI_OPCODE_SCS
:
609 arith(fpc
, sat
, COS
, dst
, MASK_X
,
610 swz(src
[0], X
, X
, X
, X
), none
, none
);
613 arith(fpc
, sat
, SIN
, dst
, MASK_Y
,
614 swz(src
[0], X
, X
, X
, X
), none
, none
);
617 case TGSI_OPCODE_SEQ
:
618 arith(fpc
, sat
, SEQ
, dst
, mask
, src
[0], src
[1], none
);
620 case TGSI_OPCODE_SFL
:
621 arith(fpc
, sat
, SFL
, dst
, mask
, src
[0], src
[1], none
);
623 case TGSI_OPCODE_SGE
:
624 arith(fpc
, sat
, SGE
, dst
, mask
, src
[0], src
[1], none
);
626 case TGSI_OPCODE_SGT
:
627 arith(fpc
, sat
, SGT
, dst
, mask
, src
[0], src
[1], none
);
629 case TGSI_OPCODE_SIN
:
630 arith(fpc
, sat
, SIN
, dst
, mask
, src
[0], none
, none
);
632 case TGSI_OPCODE_SLE
:
633 arith(fpc
, sat
, SLE
, dst
, mask
, src
[0], src
[1], none
);
635 case TGSI_OPCODE_SLT
:
636 arith(fpc
, sat
, SLT
, dst
, mask
, src
[0], src
[1], none
);
638 case TGSI_OPCODE_SNE
:
639 arith(fpc
, sat
, SNE
, dst
, mask
, src
[0], src
[1], none
);
641 case TGSI_OPCODE_STR
:
642 arith(fpc
, sat
, STR
, dst
, mask
, src
[0], src
[1], none
);
644 case TGSI_OPCODE_SUB
:
645 arith(fpc
, sat
, ADD
, dst
, mask
, src
[0], neg(src
[1]), none
);
647 case TGSI_OPCODE_TEX
:
648 tex(fpc
, sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
);
650 case TGSI_OPCODE_TXB
:
651 tex(fpc
, sat
, TXB
, unit
, dst
, mask
, src
[0], none
, none
);
653 case TGSI_OPCODE_TXP
:
654 tex(fpc
, sat
, TXP
, unit
, dst
, mask
, src
[0], none
, none
);
656 case TGSI_OPCODE_XPD
:
658 arith(fpc
, 0, MUL
, tmp
, mask
,
659 swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
);
660 arith(fpc
, sat
, MAD
, dst
, (mask
& ~MASK_W
),
661 swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
),
665 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
674 nv40_fragprog_parse_decl_attrib(struct nv40_fpc
*fpc
,
675 const struct tgsi_full_declaration
*fdec
)
679 switch (fdec
->Semantic
.SemanticName
) {
680 case TGSI_SEMANTIC_POSITION
:
681 hw
= NV40_FP_OP_INPUT_SRC_POSITION
;
683 case TGSI_SEMANTIC_COLOR
:
684 if (fdec
->Semantic
.SemanticIndex
== 0) {
685 hw
= NV40_FP_OP_INPUT_SRC_COL0
;
687 if (fdec
->Semantic
.SemanticIndex
== 1) {
688 hw
= NV40_FP_OP_INPUT_SRC_COL1
;
690 NOUVEAU_ERR("bad colour semantic index\n");
694 case TGSI_SEMANTIC_FOG
:
695 hw
= NV40_FP_OP_INPUT_SRC_FOGC
;
697 case TGSI_SEMANTIC_GENERIC
:
698 if (fdec
->Semantic
.SemanticIndex
<= 7) {
699 hw
= NV40_FP_OP_INPUT_SRC_TC(fdec
->Semantic
.
702 NOUVEAU_ERR("bad generic semantic index\n");
707 NOUVEAU_ERR("bad input semantic\n");
711 fpc
->attrib_map
[fdec
->u
.DeclarationRange
.First
] = hw
;
716 nv40_fragprog_parse_decl_output(struct nv40_fpc
*fpc
,
717 const struct tgsi_full_declaration
*fdec
)
719 unsigned idx
= fdec
->u
.DeclarationRange
.First
;
722 switch (fdec
->Semantic
.SemanticName
) {
723 case TGSI_SEMANTIC_POSITION
:
726 case TGSI_SEMANTIC_COLOR
:
727 switch (fdec
->Semantic
.SemanticIndex
) {
728 case 0: hw
= 0; break;
729 case 1: hw
= 2; break;
730 case 2: hw
= 3; break;
731 case 3: hw
= 4; break;
733 NOUVEAU_ERR("bad rcol index\n");
738 NOUVEAU_ERR("bad output semantic\n");
742 fpc
->r_result
[idx
] = nv40_sr(NV40SR_OUTPUT
, hw
);
743 fpc
->r_temps
|= (1 << hw
);
748 nv40_fragprog_prepare(struct nv40_fpc
*fpc
)
750 struct tgsi_parse_context p
;
751 int high_temp
= -1, i
;
753 tgsi_parse_init(&p
, fpc
->fp
->pipe
.tokens
);
754 while (!tgsi_parse_end_of_tokens(&p
)) {
755 const union tgsi_full_token
*tok
= &p
.FullToken
;
757 tgsi_parse_token(&p
);
758 switch(tok
->Token
.Type
) {
759 case TGSI_TOKEN_TYPE_DECLARATION
:
761 const struct tgsi_full_declaration
*fdec
;
762 fdec
= &p
.FullToken
.FullDeclaration
;
763 switch (fdec
->Declaration
.File
) {
764 case TGSI_FILE_INPUT
:
765 if (!nv40_fragprog_parse_decl_attrib(fpc
, fdec
))
768 case TGSI_FILE_OUTPUT
:
769 if (!nv40_fragprog_parse_decl_output(fpc
, fdec
))
772 case TGSI_FILE_TEMPORARY
:
773 if (fdec
->u
.DeclarationRange
.Last
> high_temp
) {
775 fdec
->u
.DeclarationRange
.Last
;
783 case TGSI_TOKEN_TYPE_IMMEDIATE
:
785 struct tgsi_full_immediate
*imm
;
788 imm
= &p
.FullToken
.FullImmediate
;
789 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
790 assert(fpc
->nr_imm
< MAX_IMM
);
792 vals
[0] = imm
->u
.ImmediateFloat32
[0].Float
;
793 vals
[1] = imm
->u
.ImmediateFloat32
[1].Float
;
794 vals
[2] = imm
->u
.ImmediateFloat32
[2].Float
;
795 vals
[3] = imm
->u
.ImmediateFloat32
[3].Float
;
796 fpc
->imm
[fpc
->nr_imm
++] = constant(fpc
, -1, vals
);
806 fpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nv40_sreg
));
807 for (i
= 0; i
< high_temp
; i
++)
808 fpc
->r_temp
[i
] = temp(fpc
);
809 fpc
->r_temps_discard
= 0;
822 nv40_fragprog_translate(struct nv40_context
*nv40
,
823 struct nv40_fragment_program
*fp
)
825 struct tgsi_parse_context parse
;
826 struct nv40_fpc
*fpc
= NULL
;
828 fpc
= CALLOC(1, sizeof(struct nv40_fpc
));
834 if (!nv40_fragprog_prepare(fpc
)) {
839 tgsi_parse_init(&parse
, fp
->pipe
.tokens
);
841 while (!tgsi_parse_end_of_tokens(&parse
)) {
842 tgsi_parse_token(&parse
);
844 switch (parse
.FullToken
.Token
.Type
) {
845 case TGSI_TOKEN_TYPE_INSTRUCTION
:
847 const struct tgsi_full_instruction
*finst
;
849 finst
= &parse
.FullToken
.FullInstruction
;
850 if (!nv40_fragprog_parse_instruction(fpc
, finst
))
859 fp
->fp_control
|= fpc
->num_regs
<< NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT
;
861 /* Terminate final instruction */
862 fp
->insn
[fpc
->inst_offset
] |= 0x00000001;
864 /* Append NOP + END instruction, may or may not be necessary. */
865 fpc
->inst_offset
= fp
->insn_len
;
867 fp
->insn
[fpc
->inst_offset
+ 0] = 0x00000001;
868 fp
->insn
[fpc
->inst_offset
+ 1] = 0x00000000;
869 fp
->insn
[fpc
->inst_offset
+ 2] = 0x00000000;
870 fp
->insn
[fpc
->inst_offset
+ 3] = 0x00000000;
872 fp
->translated
= TRUE
;
874 tgsi_parse_free(&parse
);
881 nv40_fragprog_upload(struct nv40_context
*nv40
,
882 struct nv40_fragment_program
*fp
)
884 struct pipe_winsys
*ws
= nv40
->pipe
.winsys
;
885 const uint32_t le
= 1;
889 map
= ws
->buffer_map(ws
, fp
->buffer
, PIPE_BUFFER_USAGE_CPU_WRITE
);
892 for (i
= 0; i
< fp
->insn_len
; i
++) {
893 fflush(stdout
); fflush(stderr
);
894 NOUVEAU_ERR("%d 0x%08x\n", i
, fp
->insn
[i
]);
895 fflush(stdout
); fflush(stderr
);
899 if ((*(const uint8_t *)&le
)) {
900 for (i
= 0; i
< fp
->insn_len
; i
++) {
901 map
[i
] = fp
->insn
[i
];
904 /* Weird swapping for big-endian chips */
905 for (i
= 0; i
< fp
->insn_len
; i
++) {
906 map
[i
] = ((fp
->insn
[i
] & 0xffff) << 16) |
907 ((fp
->insn
[i
] >> 16) & 0xffff);
911 ws
->buffer_unmap(ws
, fp
->buffer
);
915 nv40_fragprog_validate(struct nv40_context
*nv40
)
917 struct nv40_fragment_program
*fp
= nv40
->fragprog
;
918 struct pipe_buffer
*constbuf
=
919 nv40
->constbuf
[PIPE_SHADER_FRAGMENT
];
920 struct pipe_winsys
*ws
= nv40
->pipe
.winsys
;
921 struct nouveau_stateobj
*so
;
922 boolean new_consts
= FALSE
;
926 goto update_constants
;
928 nv40
->fallback_swrast
&= ~NV40_NEW_FRAGPROG
;
929 nv40_fragprog_translate(nv40
, fp
);
930 if (!fp
->translated
) {
931 nv40
->fallback_swrast
|= NV40_NEW_FRAGPROG
;
935 fp
->buffer
= ws
->buffer_create(ws
, 0x100, 0, fp
->insn_len
* 4);
936 nv40_fragprog_upload(nv40
, fp
);
939 so_method(so
, nv40
->screen
->curie
, NV40TCL_FP_ADDRESS
, 1);
940 so_reloc (so
, fp
->buffer
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
|
941 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
| NOUVEAU_BO_OR
,
942 NV40TCL_FP_ADDRESS_DMA0
, NV40TCL_FP_ADDRESS_DMA1
);
943 so_method(so
, nv40
->screen
->curie
, NV40TCL_FP_CONTROL
, 1);
944 so_data (so
, fp
->fp_control
);
951 map
= ws
->buffer_map(ws
, constbuf
, PIPE_BUFFER_USAGE_CPU_READ
);
952 for (i
= 0; i
< fp
->nr_consts
; i
++) {
953 struct nv40_fragment_program_data
*fpd
= &fp
->consts
[i
];
954 uint32_t *p
= &fp
->insn
[fpd
->offset
];
955 uint32_t *cb
= (uint32_t *)&map
[fpd
->index
* 4];
957 if (!memcmp(p
, cb
, 4 * sizeof(float)))
959 memcpy(p
, cb
, 4 * sizeof(float));
962 ws
->buffer_unmap(ws
, constbuf
);
965 nv40_fragprog_upload(nv40
, fp
);
968 if (new_consts
|| fp
->so
!= nv40
->state
.hw
[NV40_STATE_FRAGPROG
]) {
969 so_ref(fp
->so
, &nv40
->state
.hw
[NV40_STATE_FRAGPROG
]);
977 nv40_fragprog_destroy(struct nv40_context
*nv40
,
978 struct nv40_fragment_program
*fp
)
984 struct nv40_state_entry nv40_state_fragprog
= {
985 .validate
= nv40_fragprog_validate
,
987 .pipe
= NV40_NEW_FRAGPROG
,
988 .hw
= NV40_STATE_FRAGPROG