src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static const char *
  11 nv40_screen_get_name(struct pipe_screen *pscreen)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14         struct nouveau_device *dev = screen->nvws->channel->device;
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         struct nv40_screen *screen = nv40_screen(pscreen);
  31
  32         switch (param) {
  33         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  34                 return 16;
  35         case PIPE_CAP_NPOT_TEXTURES:
  36                 return 1;
  37         case PIPE_CAP_TWO_SIDED_STENCIL:
  38                 return 1;
  39         case PIPE_CAP_GLSL:
  40                 return 0;
  41         case PIPE_CAP_S3TC:
  42                 return 1;
  43         case PIPE_CAP_ANISOTROPIC_FILTER:
  44                 return 1;
  45         case PIPE_CAP_POINT_SPRITE:
  46                 return 1;
  47         case PIPE_CAP_MAX_RENDER_TARGETS:
  48                 return 4;
  49         case PIPE_CAP_OCCLUSION_QUERY:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  61                 return 1;
  62         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  63                 return 0; /* We have 4 - but unsupported currently */
  64         case NOUVEAU_CAP_HW_VTXBUF:
  65                 return 1;
  66         case NOUVEAU_CAP_HW_IDXBUF:
  67                 if (screen->curie->grclass == NV40TCL)
  68                         return 1;
  69                 return 0;
  70         default:
  71                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  72                 return 0;
  73         }
  74 }
  75
  76 static float
  77 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  78 {
  79         switch (param) {
  80         case PIPE_CAP_MAX_LINE_WIDTH:
  81         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  82                 return 10.0;
  83         case PIPE_CAP_MAX_POINT_WIDTH:
  84         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  85                 return 64.0;
  86         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  87                 return 16.0;
  88         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  89                 return 16.0;
  90         default:
  91                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  92                 return 0.0;
  93         }
  94 }
  95
  96 static boolean
  97 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  98                                      enum pipe_format format,
  99                                      enum pipe_texture_target target,
 100                                      unsigned tex_usage, unsigned geom_flags)
 101 {
 102         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 103                 switch (format) {
 104                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 105                 case PIPE_FORMAT_R5G6B5_UNORM:
 106                 case PIPE_FORMAT_Z24S8_UNORM:
 107                 case PIPE_FORMAT_Z16_UNORM:
 108                         return TRUE;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (format) {
 114                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 115                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 116                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 117                 case PIPE_FORMAT_R5G6B5_UNORM:
 118                 case PIPE_FORMAT_R16_SNORM:
 119                 case PIPE_FORMAT_L8_UNORM:
 120                 case PIPE_FORMAT_A8_UNORM:
 121                 case PIPE_FORMAT_I8_UNORM:
 122                 case PIPE_FORMAT_A8L8_UNORM:
 123                 case PIPE_FORMAT_Z16_UNORM:
 124                 case PIPE_FORMAT_Z24S8_UNORM:
 125                 case PIPE_FORMAT_DXT1_RGB:
 126                 case PIPE_FORMAT_DXT1_RGBA:
 127                 case PIPE_FORMAT_DXT3_RGBA:
 128                 case PIPE_FORMAT_DXT5_RGBA:
 129                         return TRUE;
 130                 default:
 131                         break;
 132                 }
 133         }
 134
 135         return FALSE;
 136 }
 137
 138 static void *
 139 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 140                  unsigned flags )
 141 {
 142         struct pipe_winsys      *ws = screen->winsys;
 143         struct pipe_surface     *surface_to_map;
 144         void                    *map;
 145
 146         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 147                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 148
 149                 if (!mt->shadow_tex) {
 150                         unsigned old_tex_usage = surface->texture->tex_usage;
 151                         surface->texture->tex_usage = NOUVEAU_TEXTURE_USAGE_LINEAR |
 152                                                       PIPE_TEXTURE_USAGE_DYNAMIC;
 153                         mt->shadow_tex = screen->texture_create(screen, surface->texture);
 154                         surface->texture->tex_usage = old_tex_usage;
 155
 156                         assert(mt->shadow_tex->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR);
 157                 }
 158
 159                 mt->shadow_surface = screen->get_tex_surface
 160                 (
 161                         screen, mt->shadow_tex,
 162                         surface->face, surface->level, surface->zslice,
 163                         surface->usage
 164                 );
 165
 166                 surface_to_map = mt->shadow_surface;
 167         }
 168         else
 169                 surface_to_map = surface;
 170
 171         assert(surface_to_map);
 172
 173         map = ws->_buffer_map(ws, surface_to_map->buffer, flags);
 174         if (!map)
 175                 return NULL;
 176
 177         return map + surface_to_map->offset;
 178 }
 179
 180 static void
 181 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 182 {
 183         struct pipe_winsys      *ws = screen->winsys;
 184         struct pipe_surface     *surface_to_unmap;
 185
 186         /* TODO: Copy from shadow just before push buffer is flushed instead.
 187                  There are probably some programs that map/unmap excessively
 188                  before rendering. */
 189         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 190                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 191
 192                 assert(mt->shadow_tex);
 193
 194                 surface_to_unmap = mt->shadow_surface;
 195         }
 196         else
 197                 surface_to_unmap = surface;
 198
 199         assert(surface_to_unmap);
 200
 201         ws->_buffer_unmap(ws, surface_to_unmap->buffer);
 202
 203         if (surface_to_unmap != surface) {
 204                 struct nv40_screen *nvscreen = nv40_screen(screen);
 205
 206                 nvscreen->nvws->surface_copy(nvscreen->nvws,
 207                                              surface, 0, 0,
 208                                              surface_to_unmap, 0, 0,
 209                                              surface->width, surface->height);
 210         }
 211 }
 212
 213 static void
 214 nv40_screen_destroy(struct pipe_screen *pscreen)
 215 {
 216         struct nv40_screen *screen = nv40_screen(pscreen);
 217         struct nouveau_winsys *nvws = screen->nvws;
 218
 219         nvws->res_free(&screen->vp_exec_heap);
 220         nvws->res_free(&screen->vp_data_heap);
 221         nvws->res_free(&screen->query_heap);
 222         nvws->notifier_free(&screen->query);
 223         nvws->notifier_free(&screen->sync);
 224         nvws->grobj_free(&screen->curie);
 225
 226         FREE(pscreen);
 227 }
 228
 229 struct pipe_screen *
 230 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 231 {
 232         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 233         struct nouveau_stateobj *so;
 234         unsigned curie_class;
 235         unsigned chipset = nvws->channel->device->chipset;
 236         int ret;
 237
 238         if (!screen)
 239                 return NULL;
 240         screen->nvws = nvws;
 241
 242         /* 3D object */
 243         switch (chipset & 0xf0) {
 244         case 0x40:
 245                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 246                         curie_class = NV40TCL;
 247                 else
 248                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 249                         curie_class = NV44TCL;
 250                 break;
 251         case 0x60:
 252                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 253                         curie_class = NV44TCL;
 254                 break;
 255         default:
 256                 break;
 257         }
 258
 259         if (!curie_class) {
 260                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 261                 return NULL;
 262         }
 263
 264         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 265         if (ret) {
 266                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 267                 return FALSE;
 268         }
 269
 270         /* Notifier for sync purposes */
 271         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 272         if (ret) {
 273                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 274                 nv40_screen_destroy(&screen->pipe);
 275                 return NULL;
 276         }
 277
 278         /* Query objects */
 279         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 280         if (ret) {
 281                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 282                 nv40_screen_destroy(&screen->pipe);
 283                 return NULL;
 284         }
 285
 286         ret = nvws->res_init(&screen->query_heap, 0, 32);
 287         if (ret) {
 288                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 289                 nv40_screen_destroy(&screen->pipe);
 290                 return NULL;
 291         }
 292
 293         /* Vtxprog resources */
 294         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 295             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 296                 nv40_screen_destroy(&screen->pipe);
 297                 return NULL;
 298         }
 299
 300         /* Static curie initialisation */
 301         so = so_new(128, 0);
 302         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 303         so_data  (so, screen->sync->handle);
 304         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 305         so_data  (so, nvws->channel->vram->handle);
 306         so_data  (so, nvws->channel->gart->handle);
 307         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 308         so_data  (so, nvws->channel->vram->handle);
 309         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 310         so_data  (so, nvws->channel->vram->handle);
 311         so_data  (so, nvws->channel->vram->handle);
 312         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 313         so_data  (so, nvws->channel->vram->handle);
 314         so_data  (so, nvws->channel->gart->handle);
 315         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 316         so_data  (so, 0);
 317         so_data  (so, screen->query->handle);
 318         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 319         so_data  (so, nvws->channel->vram->handle);
 320         so_data  (so, nvws->channel->vram->handle);
 321         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 322         so_data  (so, nvws->channel->vram->handle);
 323         so_data  (so, nvws->channel->vram->handle);
 324
 325         so_method(so, screen->curie, 0x1ea4, 3);
 326         so_data  (so, 0x00000010);
 327         so_data  (so, 0x01000100);
 328         so_data  (so, 0xff800006);
 329
 330         /* vtxprog output routing */
 331         so_method(so, screen->curie, 0x1fc4, 1);
 332         so_data  (so, 0x06144321);
 333         so_method(so, screen->curie, 0x1fc8, 2);
 334         so_data  (so, 0xedcba987);
 335         so_data  (so, 0x00000021);
 336         so_method(so, screen->curie, 0x1fd0, 1);
 337         so_data  (so, 0x00171615);
 338         so_method(so, screen->curie, 0x1fd4, 1);
 339         so_data  (so, 0x001b1a19);
 340
 341         so_method(so, screen->curie, 0x1ef8, 1);
 342         so_data  (so, 0x0020ffff);
 343         so_method(so, screen->curie, 0x1d64, 1);
 344         so_data  (so, 0x00d30000);
 345         so_method(so, screen->curie, 0x1e94, 1);
 346         so_data  (so, 0x00000001);
 347
 348         so_emit(nvws, so);
 349         so_ref(NULL, &so);
 350         nvws->push_flush(nvws, 0, NULL);
 351
 352         screen->pipe.winsys = ws;
 353         screen->pipe.destroy = nv40_screen_destroy;
 354
 355         screen->pipe.get_name = nv40_screen_get_name;
 356         screen->pipe.get_vendor = nv40_screen_get_vendor;
 357         screen->pipe.get_param = nv40_screen_get_param;
 358         screen->pipe.get_paramf = nv40_screen_get_paramf;
 359
 360         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 361
 362         screen->pipe.surface_map = nv40_surface_map;
 363         screen->pipe.surface_unmap = nv40_surface_unmap;
 364
 365         nv40_screen_init_miptree_functions(&screen->pipe);
 366
 367         return &screen->pipe;
 368 }
 369