src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static int
  11 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14
  15         switch (param) {
  16         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  17                 return 16;
  18         case PIPE_CAP_NPOT_TEXTURES:
  19                 return 1;
  20         case PIPE_CAP_TWO_SIDED_STENCIL:
  21                 return 1;
  22         case PIPE_CAP_GLSL:
  23                 return 0;
  24         case PIPE_CAP_S3TC:
  25                 return 1;
  26         case PIPE_CAP_ANISOTROPIC_FILTER:
  27                 return 1;
  28         case PIPE_CAP_POINT_SPRITE:
  29                 return 1;
  30         case PIPE_CAP_MAX_RENDER_TARGETS:
  31                 return 4;
  32         case PIPE_CAP_OCCLUSION_QUERY:
  33                 return 1;
  34         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  35                 return 1;
  36         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  37                 return 13;
  38         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  39                 return 10;
  40         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  41                 return 13;
  42         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  43         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  44                 return 1;
  45         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  46                 return 0; /* We have 4 - but unsupported currently */
  47         case NOUVEAU_CAP_HW_VTXBUF:
  48                 return 1;
  49         case NOUVEAU_CAP_HW_IDXBUF:
  50                 if (screen->curie->grclass == NV40TCL)
  51                         return 1;
  52                 return 0;
  53         default:
  54                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  55                 return 0;
  56         }
  57 }
  58
  59 static float
  60 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  61 {
  62         switch (param) {
  63         case PIPE_CAP_MAX_LINE_WIDTH:
  64         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  65                 return 10.0;
  66         case PIPE_CAP_MAX_POINT_WIDTH:
  67         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  68                 return 64.0;
  69         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  70                 return 16.0;
  71         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  72                 return 16.0;
  73         default:
  74                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  75                 return 0.0;
  76         }
  77 }
  78
  79 static boolean
  80 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  81                                      enum pipe_format format,
  82                                      enum pipe_texture_target target,
  83                                      unsigned tex_usage, unsigned geom_flags)
  84 {
  85         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  86                 switch (format) {
  87                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  88                 case PIPE_FORMAT_R5G6B5_UNORM:
  89                 case PIPE_FORMAT_Z24S8_UNORM:
  90                 case PIPE_FORMAT_Z16_UNORM:
  91                         return TRUE;
  92                 default:
  93                         break;
  94                 }
  95         } else {
  96                 switch (format) {
  97                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  98                 case PIPE_FORMAT_A1R5G5B5_UNORM:
  99                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 100                 case PIPE_FORMAT_R5G6B5_UNORM:
 101                 case PIPE_FORMAT_R16_SNORM:
 102                 case PIPE_FORMAT_L8_UNORM:
 103                 case PIPE_FORMAT_A8_UNORM:
 104                 case PIPE_FORMAT_I8_UNORM:
 105                 case PIPE_FORMAT_A8L8_UNORM:
 106                 case PIPE_FORMAT_Z16_UNORM:
 107                 case PIPE_FORMAT_Z24S8_UNORM:
 108                 case PIPE_FORMAT_DXT1_RGB:
 109                 case PIPE_FORMAT_DXT1_RGBA:
 110                 case PIPE_FORMAT_DXT3_RGBA:
 111                 case PIPE_FORMAT_DXT5_RGBA:
 112                         return TRUE;
 113                 default:
 114                         break;
 115                 }
 116         }
 117
 118         return FALSE;
 119 }
 120
 121 static struct pipe_buffer *
 122 nv40_surface_buffer(struct pipe_surface *surf)
 123 {
 124         struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
 125
 126         return mt->buffer;
 127 }
 128
 129 static void
 130 nv40_screen_destroy(struct pipe_screen *pscreen)
 131 {
 132         struct nv40_screen *screen = nv40_screen(pscreen);
 133
 134         nouveau_resource_free(&screen->vp_exec_heap);
 135         nouveau_resource_free(&screen->vp_data_heap);
 136         nouveau_resource_free(&screen->query_heap);
 137         nouveau_notifier_free(&screen->query);
 138         nouveau_notifier_free(&screen->sync);
 139         nouveau_grobj_free(&screen->curie);
 140
 141         nouveau_screen_fini(&screen->base);
 142
 143         FREE(pscreen);
 144 }
 145
 146 struct pipe_screen *
 147 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 148 {
 149         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 150         struct nouveau_device *dev = nvws->channel->device;
 151         struct nouveau_channel *chan;
 152         struct pipe_screen *pscreen;
 153         struct nouveau_stateobj *so;
 154         unsigned curie_class = 0;
 155         int ret;
 156
 157         if (!screen)
 158                 return NULL;
 159         pscreen = &screen->base.base;
 160
 161         ret = nouveau_screen_init(&screen->base, dev);
 162         if (ret) {
 163                 nv40_screen_destroy(pscreen);
 164                 return NULL;
 165         }
 166         screen->base.channel = chan = nvws->channel;
 167
 168         screen->nvws = nvws;
 169
 170         pscreen->winsys = ws;
 171         pscreen->destroy = nv40_screen_destroy;
 172         pscreen->get_param = nv40_screen_get_param;
 173         pscreen->get_paramf = nv40_screen_get_paramf;
 174         pscreen->is_format_supported = nv40_screen_surface_format_supported;
 175
 176         nv40_screen_init_miptree_functions(pscreen);
 177         nv40_screen_init_transfer_functions(pscreen);
 178
 179         /* 3D object */
 180         switch (dev->chipset & 0xf0) {
 181         case 0x40:
 182                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 183                         curie_class = NV40TCL;
 184                 else
 185                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 186                         curie_class = NV44TCL;
 187                 break;
 188         case 0x60:
 189                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 190                         curie_class = NV44TCL;
 191                 break;
 192         }
 193
 194         if (!curie_class) {
 195                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
 196                 return NULL;
 197         }
 198
 199         ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
 200         if (ret) {
 201                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 202                 return FALSE;
 203         }
 204         BIND_RING(chan, screen->curie, 7);
 205
 206         /* 2D engine setup */
 207         screen->eng2d = nv04_surface_2d_init(nvws);
 208         screen->eng2d->buf = nv40_surface_buffer;
 209
 210         /* Notifier for sync purposes */
 211         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 212         if (ret) {
 213                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 214                 nv40_screen_destroy(pscreen);
 215                 return NULL;
 216         }
 217
 218         /* Query objects */
 219         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 220         if (ret) {
 221                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 222                 nv40_screen_destroy(pscreen);
 223                 return NULL;
 224         }
 225
 226         nouveau_resource_init(&screen->query_heap, 0, 32);
 227         if (ret) {
 228                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 229                 nv40_screen_destroy(pscreen);
 230                 return NULL;
 231         }
 232
 233         /* Vtxprog resources */
 234         if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
 235             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 236                 nv40_screen_destroy(pscreen);
 237                 return NULL;
 238         }
 239
 240         /* Static curie initialisation */
 241         so = so_new(128, 0);
 242         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 243         so_data  (so, screen->sync->handle);
 244         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 245         so_data  (so, nvws->channel->vram->handle);
 246         so_data  (so, nvws->channel->gart->handle);
 247         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 248         so_data  (so, nvws->channel->vram->handle);
 249         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 250         so_data  (so, nvws->channel->vram->handle);
 251         so_data  (so, nvws->channel->vram->handle);
 252         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 253         so_data  (so, nvws->channel->vram->handle);
 254         so_data  (so, nvws->channel->gart->handle);
 255         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 256         so_data  (so, 0);
 257         so_data  (so, screen->query->handle);
 258         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 259         so_data  (so, nvws->channel->vram->handle);
 260         so_data  (so, nvws->channel->vram->handle);
 261         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 262         so_data  (so, nvws->channel->vram->handle);
 263         so_data  (so, nvws->channel->vram->handle);
 264
 265         so_method(so, screen->curie, 0x1ea4, 3);
 266         so_data  (so, 0x00000010);
 267         so_data  (so, 0x01000100);
 268         so_data  (so, 0xff800006);
 269
 270         /* vtxprog output routing */
 271         so_method(so, screen->curie, 0x1fc4, 1);
 272         so_data  (so, 0x06144321);
 273         so_method(so, screen->curie, 0x1fc8, 2);
 274         so_data  (so, 0xedcba987);
 275         so_data  (so, 0x00000021);
 276         so_method(so, screen->curie, 0x1fd0, 1);
 277         so_data  (so, 0x00171615);
 278         so_method(so, screen->curie, 0x1fd4, 1);
 279         so_data  (so, 0x001b1a19);
 280
 281         so_method(so, screen->curie, 0x1ef8, 1);
 282         so_data  (so, 0x0020ffff);
 283         so_method(so, screen->curie, 0x1d64, 1);
 284         so_data  (so, 0x00d30000);
 285         so_method(so, screen->curie, 0x1e94, 1);
 286         so_data  (so, 0x00000001);
 287
 288         so_emit(nvws, so);
 289         so_ref(NULL, &so);
 290         nouveau_pushbuf_flush(nvws->channel, 0);
 291
 292         return pscreen;
 293 }
 294