src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_util.h"
   3
   4 #include "nv40_context.h"
   5 #include "nv40_screen.h"
   6
   7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  10
  11 static const char *
  12 nv40_screen_get_name(struct pipe_screen *pscreen)
  13 {
  14         struct nv40_screen *screen = nv40_screen(pscreen);
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", screen->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         switch (param) {
  31         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  32                 return 16;
  33         case PIPE_CAP_NPOT_TEXTURES:
  34                 return 1;
  35         case PIPE_CAP_TWO_SIDED_STENCIL:
  36                 return 1;
  37         case PIPE_CAP_GLSL:
  38                 return 0;
  39         case PIPE_CAP_S3TC:
  40                 return 0;
  41         case PIPE_CAP_ANISOTROPIC_FILTER:
  42                 return 1;
  43         case PIPE_CAP_POINT_SPRITE:
  44                 return 1;
  45         case PIPE_CAP_MAX_RENDER_TARGETS:
  46                 return 4;
  47         case PIPE_CAP_OCCLUSION_QUERY:
  48                 return 1;
  49         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  50                 return 1;
  51         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  52                 return 13;
  53         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  54                 return 10;
  55         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  56                 return 13;
  57         default:
  58                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  59                 return 0;
  60         }
  61 }
  62
  63 static float
  64 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  65 {
  66         switch (param) {
  67         case PIPE_CAP_MAX_LINE_WIDTH:
  68         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  69                 return 10.0;
  70         case PIPE_CAP_MAX_POINT_WIDTH:
  71         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  72                 return 64.0;
  73         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  74                 return 16.0;
  75         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  76                 return 16.0;
  77         case PIPE_CAP_BITMAP_TEXCOORD_BIAS:
  78                 return 0.0;
  79         default:
  80                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  81                 return 0.0;
  82         }
  83 }
  84
  85 static boolean
  86 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  87                                      enum pipe_format format, uint type)
  88 {
  89         switch (type) {
  90         case PIPE_SURFACE:
  91                 switch (format) {
  92                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  93                 case PIPE_FORMAT_R5G6B5_UNORM:
  94                 case PIPE_FORMAT_Z24S8_UNORM:
  95                 case PIPE_FORMAT_Z16_UNORM:
  96                         return TRUE;
  97                 default:
  98                         break;
  99                 }
 100                 break;
 101         case PIPE_TEXTURE:
 102                 switch (format) {
 103                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 104                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 105                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 106                 case PIPE_FORMAT_R5G6B5_UNORM:
 107                 case PIPE_FORMAT_U_L8:
 108                 case PIPE_FORMAT_U_A8:
 109                 case PIPE_FORMAT_U_I8:
 110                 case PIPE_FORMAT_U_A8_L8:
 111                 case PIPE_FORMAT_Z16_UNORM:
 112                 case PIPE_FORMAT_Z24S8_UNORM:
 113                         return TRUE;
 114                 default:
 115                         break;
 116                 }
 117                 break;
 118         default:
 119                 assert(0);
 120         };
 121
 122         return FALSE;
 123 }
 124
 125 static void
 126 nv40_screen_destroy(struct pipe_screen *pscreen)
 127 {
 128         struct nv40_screen *screen = nv40_screen(pscreen);
 129         struct nouveau_winsys *nvws = screen->nvws;
 130
 131         nvws->res_free(&screen->vp_exec_heap);
 132         nvws->res_free(&screen->vp_data_heap);
 133         nvws->res_free(&screen->query_heap);
 134         nvws->notifier_free(&screen->query);
 135         nvws->notifier_free(&screen->sync);
 136         nvws->grobj_free(&screen->curie);
 137
 138         FREE(pscreen);
 139 }
 140
 141 struct pipe_screen *
 142 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws,
 143                    unsigned chipset)
 144 {
 145         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 146         struct nouveau_stateobj *so;
 147         unsigned curie_class;
 148         int ret;
 149
 150         if (!screen)
 151                 return NULL;
 152         screen->chipset = chipset;
 153         screen->nvws = nvws;
 154
 155         /* 3D object */
 156         switch (chipset & 0xf0) {
 157         case 0x40:
 158                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 159                         curie_class = NV40TCL;
 160                 else
 161                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 162                         curie_class = NV44TCL;
 163                 break;
 164         case 0x60:
 165                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 166                         curie_class = NV44TCL;
 167                 break;
 168         default:
 169                 break;
 170         }
 171
 172         if (!curie_class) {
 173                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 174                 return NULL;
 175         }
 176
 177         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 178         if (ret) {
 179                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 180                 return FALSE;
 181         }
 182
 183         /* Notifier for sync purposes */
 184         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 185         if (ret) {
 186                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 187                 nv40_screen_destroy(&screen->pipe);
 188                 return NULL;
 189         }
 190
 191         /* Query objects */
 192         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 193         if (ret) {
 194                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 195                 nv40_screen_destroy(&screen->pipe);
 196                 return NULL;
 197         }
 198
 199         ret = nvws->res_init(&screen->query_heap, 0, 32);
 200         if (ret) {
 201                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 202                 nv40_screen_destroy(&screen->pipe);
 203                 return NULL;
 204         }
 205
 206         /* Vtxprog resources */
 207         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 208             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 209                 nv40_screen_destroy(&screen->pipe);
 210                 return NULL;
 211         }
 212
 213         /* Static curie initialisation */
 214         so = so_new(128, 0);
 215         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 216         so_data  (so, screen->sync->handle);
 217         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 218         so_data  (so, nvws->channel->vram->handle);
 219         so_data  (so, nvws->channel->gart->handle);
 220         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 221         so_data  (so, nvws->channel->vram->handle);
 222         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 223         so_data  (so, nvws->channel->vram->handle);
 224         so_data  (so, nvws->channel->vram->handle);
 225         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 226         so_data  (so, nvws->channel->vram->handle);
 227         so_data  (so, nvws->channel->gart->handle);
 228         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 229         so_data  (so, 0);
 230         so_data  (so, screen->query->handle);
 231         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 232         so_data  (so, nvws->channel->vram->handle);
 233         so_data  (so, nvws->channel->vram->handle);
 234         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 235         so_data  (so, nvws->channel->vram->handle);
 236         so_data  (so, nvws->channel->vram->handle);
 237
 238         so_method(so, screen->curie, 0x1ea4, 3);
 239         so_data  (so, 0x00000010);
 240         so_data  (so, 0x01000100);
 241         so_data  (so, 0xff800006);
 242
 243         /* vtxprog output routing */
 244         so_method(so, screen->curie, 0x1fc4, 1);
 245         so_data  (so, 0x06144321);
 246         so_method(so, screen->curie, 0x1fc8, 2);
 247         so_data  (so, 0xedcba987);
 248         so_data  (so, 0x00000021);
 249         so_method(so, screen->curie, 0x1fd0, 1);
 250         so_data  (so, 0x00171615);
 251         so_method(so, screen->curie, 0x1fd4, 1);
 252         so_data  (so, 0x001b1a19);
 253
 254         so_method(so, screen->curie, 0x1ef8, 1);
 255         so_data  (so, 0x0020ffff);
 256         so_method(so, screen->curie, 0x1d64, 1);
 257         so_data  (so, 0x00d30000);
 258         so_method(so, screen->curie, 0x1e94, 1);
 259         so_data  (so, 0x00000001);
 260
 261         so_emit(nvws, so);
 262         so_ref(NULL, &so);
 263         nvws->push_flush(nvws->channel, 0);
 264
 265         screen->pipe.winsys = ws;
 266         screen->pipe.destroy = nv40_screen_destroy;
 267
 268         screen->pipe.get_name = nv40_screen_get_name;
 269         screen->pipe.get_vendor = nv40_screen_get_vendor;
 270         screen->pipe.get_param = nv40_screen_get_param;
 271         screen->pipe.get_paramf = nv40_screen_get_paramf;
 272
 273         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 274
 275         nv40_screen_init_miptree_functions(&screen->pipe);
 276
 277         return &screen->pipe;
 278 }
 279