1 #include "pipe/p_screen.h"
3 #include "nv40_context.h"
4 #include "nv40_screen.h"
6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
11 nv40_screen_get_param(struct pipe_screen
*pscreen
, int param
)
13 struct nv40_screen
*screen
= nv40_screen(pscreen
);
16 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
18 case PIPE_CAP_NPOT_TEXTURES
:
20 case PIPE_CAP_TWO_SIDED_STENCIL
:
24 case PIPE_CAP_ANISOTROPIC_FILTER
:
26 case PIPE_CAP_POINT_SPRITE
:
28 case PIPE_CAP_MAX_RENDER_TARGETS
:
30 case PIPE_CAP_OCCLUSION_QUERY
:
32 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
34 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
36 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
38 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
40 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
41 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
43 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
44 return 0; /* We have 4 - but unsupported currently */
45 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
47 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
49 case NOUVEAU_CAP_HW_VTXBUF
:
51 case NOUVEAU_CAP_HW_IDXBUF
:
52 if (screen
->eng3d
->grclass
== NV40TCL
)
55 case PIPE_CAP_INDEP_BLEND_ENABLE
:
57 case PIPE_CAP_INDEP_BLEND_FUNC
:
59 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
60 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
62 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
63 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
65 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
68 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
74 nv40_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
77 case PIPE_CAP_MAX_LINE_WIDTH
:
78 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
80 case PIPE_CAP_MAX_POINT_WIDTH
:
81 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
83 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
85 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
88 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
94 nv40_screen_surface_format_supported(struct pipe_screen
*pscreen
,
95 enum pipe_format format
,
96 enum pipe_texture_target target
,
97 unsigned tex_usage
, unsigned geom_flags
)
99 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
101 case PIPE_FORMAT_B8G8R8A8_UNORM
:
102 case PIPE_FORMAT_B5G6R5_UNORM
:
108 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
110 case PIPE_FORMAT_S8Z24_UNORM
:
111 case PIPE_FORMAT_X8Z24_UNORM
:
112 case PIPE_FORMAT_Z16_UNORM
:
119 case PIPE_FORMAT_B8G8R8A8_UNORM
:
120 case PIPE_FORMAT_B5G5R5A1_UNORM
:
121 case PIPE_FORMAT_B4G4R4A4_UNORM
:
122 case PIPE_FORMAT_B5G6R5_UNORM
:
123 case PIPE_FORMAT_R16_SNORM
:
124 case PIPE_FORMAT_L8_UNORM
:
125 case PIPE_FORMAT_A8_UNORM
:
126 case PIPE_FORMAT_I8_UNORM
:
127 case PIPE_FORMAT_L8A8_UNORM
:
128 case PIPE_FORMAT_Z16_UNORM
:
129 case PIPE_FORMAT_S8Z24_UNORM
:
130 case PIPE_FORMAT_DXT1_RGB
:
131 case PIPE_FORMAT_DXT1_RGBA
:
132 case PIPE_FORMAT_DXT3_RGBA
:
133 case PIPE_FORMAT_DXT5_RGBA
:
143 static struct pipe_buffer
*
144 nv40_surface_buffer(struct pipe_surface
*surf
)
146 struct nv40_miptree
*mt
= (struct nv40_miptree
*)surf
->texture
;
152 nv40_screen_destroy(struct pipe_screen
*pscreen
)
154 struct nv40_screen
*screen
= nv40_screen(pscreen
);
157 for (i
= 0; i
< NV40_STATE_MAX
; i
++) {
158 if (screen
->state
[i
])
159 so_ref(NULL
, &screen
->state
[i
]);
162 nouveau_resource_destroy(&screen
->vp_exec_heap
);
163 nouveau_resource_destroy(&screen
->vp_data_heap
);
164 nouveau_resource_destroy(&screen
->query_heap
);
165 nouveau_notifier_free(&screen
->query
);
166 nouveau_notifier_free(&screen
->sync
);
167 nouveau_grobj_free(&screen
->eng3d
);
168 nv04_surface_2d_takedown(&screen
->eng2d
);
170 nouveau_screen_fini(&screen
->base
);
176 nv40_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
178 struct nv40_screen
*screen
= CALLOC_STRUCT(nv40_screen
);
179 struct nouveau_channel
*chan
;
180 struct pipe_screen
*pscreen
;
181 struct nouveau_stateobj
*so
;
182 unsigned eng3d_class
= 0;
187 pscreen
= &screen
->base
.base
;
189 ret
= nouveau_screen_init(&screen
->base
, dev
);
191 nv40_screen_destroy(pscreen
);
194 chan
= screen
->base
.channel
;
196 pscreen
->winsys
= ws
;
197 pscreen
->destroy
= nv40_screen_destroy
;
198 pscreen
->get_param
= nv40_screen_get_param
;
199 pscreen
->get_paramf
= nv40_screen_get_paramf
;
200 pscreen
->is_format_supported
= nv40_screen_surface_format_supported
;
201 pscreen
->context_create
= nv40_create
;
203 nv40_screen_init_miptree_functions(pscreen
);
206 switch (dev
->chipset
& 0xf0) {
208 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
209 eng3d_class
= NV40TCL
;
211 if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
212 eng3d_class
= NV44TCL
;
215 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
216 eng3d_class
= NV44TCL
;
221 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev
->chipset
);
225 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
227 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
231 /* 2D engine setup */
232 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
233 screen
->eng2d
->buf
= nv40_surface_buffer
;
235 /* Notifier for sync purposes */
236 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
238 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
239 nv40_screen_destroy(pscreen
);
244 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, 32, &screen
->query
);
246 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
247 nv40_screen_destroy(pscreen
);
251 nouveau_resource_init(&screen
->query_heap
, 0, 32);
253 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
254 nv40_screen_destroy(pscreen
);
258 /* Vtxprog resources */
259 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, 512) ||
260 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
261 nv40_screen_destroy(pscreen
);
265 /* Static eng3d initialisation */
266 so
= so_new(16, 25, 0);
267 so_method(so
, screen
->eng3d
, NV34TCL_DMA_NOTIFY
, 1);
268 so_data (so
, screen
->sync
->handle
);
269 so_method(so
, screen
->eng3d
, NV34TCL_DMA_TEXTURE0
, 2);
270 so_data (so
, chan
->vram
->handle
);
271 so_data (so
, chan
->gart
->handle
);
272 so_method(so
, screen
->eng3d
, NV34TCL_DMA_COLOR1
, 1);
273 so_data (so
, chan
->vram
->handle
);
274 so_method(so
, screen
->eng3d
, NV34TCL_DMA_COLOR0
, 2);
275 so_data (so
, chan
->vram
->handle
);
276 so_data (so
, chan
->vram
->handle
);
277 so_method(so
, screen
->eng3d
, NV34TCL_DMA_VTXBUF0
, 2);
278 so_data (so
, chan
->vram
->handle
);
279 so_data (so
, chan
->gart
->handle
);
280 so_method(so
, screen
->eng3d
, NV34TCL_DMA_FENCE
, 2);
282 so_data (so
, screen
->query
->handle
);
283 so_method(so
, screen
->eng3d
, NV34TCL_DMA_IN_MEMORY7
, 2);
284 so_data (so
, chan
->vram
->handle
);
285 so_data (so
, chan
->vram
->handle
);
286 so_method(so
, screen
->eng3d
, NV40TCL_DMA_COLOR2
, 2);
287 so_data (so
, chan
->vram
->handle
);
288 so_data (so
, chan
->vram
->handle
);
290 so_method(so
, screen
->eng3d
, 0x1ea4, 3);
291 so_data (so
, 0x00000010);
292 so_data (so
, 0x01000100);
293 so_data (so
, 0xff800006);
295 /* vtxprog output routing */
296 so_method(so
, screen
->eng3d
, 0x1fc4, 1);
297 so_data (so
, 0x06144321);
298 so_method(so
, screen
->eng3d
, 0x1fc8, 2);
299 so_data (so
, 0xedcba987);
300 so_data (so
, 0x00000021);
301 so_method(so
, screen
->eng3d
, 0x1fd0, 1);
302 so_data (so
, 0x00171615);
303 so_method(so
, screen
->eng3d
, 0x1fd4, 1);
304 so_data (so
, 0x001b1a19);
306 so_method(so
, screen
->eng3d
, 0x1ef8, 1);
307 so_data (so
, 0x0020ffff);
308 so_method(so
, screen
->eng3d
, 0x1d64, 1);
309 so_data (so
, 0x00d30000);
310 so_method(so
, screen
->eng3d
, 0x1e94, 1);
311 so_data (so
, 0x00000001);
315 nouveau_pushbuf_flush(chan
, 0);