src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static int
  11 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14
  15         switch (param) {
  16         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  17                 return 16;
  18         case PIPE_CAP_NPOT_TEXTURES:
  19                 return 1;
  20         case PIPE_CAP_TWO_SIDED_STENCIL:
  21                 return 1;
  22         case PIPE_CAP_GLSL:
  23                 return 0;
  24         case PIPE_CAP_ANISOTROPIC_FILTER:
  25                 return 1;
  26         case PIPE_CAP_POINT_SPRITE:
  27                 return 1;
  28         case PIPE_CAP_MAX_RENDER_TARGETS:
  29                 return 4;
  30         case PIPE_CAP_OCCLUSION_QUERY:
  31                 return 1;
  32         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  33                 return 1;
  34         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  35                 return 13;
  36         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  37                 return 10;
  38         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  39                 return 13;
  40         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  41         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  42                 return 1;
  43         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  44                 return 0; /* We have 4 - but unsupported currently */
  45         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  46                 return 0;
  47         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  48                 return 1;
  49         case NOUVEAU_CAP_HW_VTXBUF:
  50                 return 1;
  51         case NOUVEAU_CAP_HW_IDXBUF:
  52                 if (screen->curie->grclass == NV40TCL)
  53                         return 1;
  54                 return 0;
  55         case PIPE_CAP_INDEP_BLEND_ENABLE:
  56                 return 0;
  57         case PIPE_CAP_INDEP_BLEND_FUNC:
  58                 return 0;
  59         default:
  60                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  61                 return 0;
  62         }
  63 }
  64
  65 static float
  66 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  67 {
  68         switch (param) {
  69         case PIPE_CAP_MAX_LINE_WIDTH:
  70         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  71                 return 10.0;
  72         case PIPE_CAP_MAX_POINT_WIDTH:
  73         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  74                 return 64.0;
  75         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  76                 return 16.0;
  77         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  78                 return 16.0;
  79         default:
  80                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  81                 return 0.0;
  82         }
  83 }
  84
  85 static boolean
  86 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  87                                      enum pipe_format format,
  88                                      enum pipe_texture_target target,
  89                                      unsigned tex_usage, unsigned geom_flags)
  90 {
  91         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  92                 switch (format) {
  93                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  94                 case PIPE_FORMAT_R5G6B5_UNORM:
  95                         return TRUE;
  96                 default:
  97                         break;
  98                 }
  99         } else
 100         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
 101                 switch (format) {
 102                 case PIPE_FORMAT_Z24S8_UNORM:
 103                 case PIPE_FORMAT_Z24X8_UNORM:
 104                 case PIPE_FORMAT_Z16_UNORM:
 105                         return TRUE;
 106                 default:
 107                         break;
 108                 }
 109         } else {
 110                 switch (format) {
 111                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 112                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 113                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 114                 case PIPE_FORMAT_R5G6B5_UNORM:
 115                 case PIPE_FORMAT_R16_SNORM:
 116                 case PIPE_FORMAT_L8_UNORM:
 117                 case PIPE_FORMAT_A8_UNORM:
 118                 case PIPE_FORMAT_I8_UNORM:
 119                 case PIPE_FORMAT_A8L8_UNORM:
 120                 case PIPE_FORMAT_Z16_UNORM:
 121                 case PIPE_FORMAT_Z24S8_UNORM:
 122                 case PIPE_FORMAT_DXT1_RGB:
 123                 case PIPE_FORMAT_DXT1_RGBA:
 124                 case PIPE_FORMAT_DXT3_RGBA:
 125                 case PIPE_FORMAT_DXT5_RGBA:
 126                         return TRUE;
 127                 default:
 128                         break;
 129                 }
 130         }
 131
 132         return FALSE;
 133 }
 134
 135 static struct pipe_buffer *
 136 nv40_surface_buffer(struct pipe_surface *surf)
 137 {
 138         struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
 139
 140         return mt->buffer;
 141 }
 142
 143 static void
 144 nv40_screen_destroy(struct pipe_screen *pscreen)
 145 {
 146         struct nv40_screen *screen = nv40_screen(pscreen);
 147         unsigned i;
 148
 149         for (i = 0; i < NV40_STATE_MAX; i++) {
 150                 if (screen->state[i])
 151                         so_ref(NULL, &screen->state[i]);
 152         }
 153
 154         nouveau_resource_free(&screen->vp_exec_heap);
 155         nouveau_resource_free(&screen->vp_data_heap);
 156         nouveau_resource_free(&screen->query_heap);
 157         nouveau_notifier_free(&screen->query);
 158         nouveau_notifier_free(&screen->sync);
 159         nouveau_grobj_free(&screen->curie);
 160         nv04_surface_2d_takedown(&screen->eng2d);
 161
 162         nouveau_screen_fini(&screen->base);
 163
 164         FREE(pscreen);
 165 }
 166
 167 struct pipe_screen *
 168 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 169 {
 170         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 171         struct nouveau_channel *chan;
 172         struct pipe_screen *pscreen;
 173         struct nouveau_stateobj *so;
 174         unsigned curie_class = 0;
 175         int ret;
 176
 177         if (!screen)
 178                 return NULL;
 179         pscreen = &screen->base.base;
 180
 181         ret = nouveau_screen_init(&screen->base, dev);
 182         if (ret) {
 183                 nv40_screen_destroy(pscreen);
 184                 return NULL;
 185         }
 186         chan = screen->base.channel;
 187
 188         pscreen->winsys = ws;
 189         pscreen->destroy = nv40_screen_destroy;
 190         pscreen->get_param = nv40_screen_get_param;
 191         pscreen->get_paramf = nv40_screen_get_paramf;
 192         pscreen->is_format_supported = nv40_screen_surface_format_supported;
 193
 194         nv40_screen_init_miptree_functions(pscreen);
 195         nv40_screen_init_transfer_functions(pscreen);
 196
 197         /* 3D object */
 198         switch (dev->chipset & 0xf0) {
 199         case 0x40:
 200                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 201                         curie_class = NV40TCL;
 202                 else
 203                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 204                         curie_class = NV44TCL;
 205                 break;
 206         case 0x60:
 207                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 208                         curie_class = NV44TCL;
 209                 break;
 210         }
 211
 212         if (!curie_class) {
 213                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
 214                 return NULL;
 215         }
 216
 217         ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
 218         if (ret) {
 219                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 220                 return FALSE;
 221         }
 222
 223         /* 2D engine setup */
 224         screen->eng2d = nv04_surface_2d_init(&screen->base);
 225         screen->eng2d->buf = nv40_surface_buffer;
 226
 227         /* Notifier for sync purposes */
 228         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 229         if (ret) {
 230                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 231                 nv40_screen_destroy(pscreen);
 232                 return NULL;
 233         }
 234
 235         /* Query objects */
 236         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 237         if (ret) {
 238                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 239                 nv40_screen_destroy(pscreen);
 240                 return NULL;
 241         }
 242
 243         nouveau_resource_init(&screen->query_heap, 0, 32);
 244         if (ret) {
 245                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 246                 nv40_screen_destroy(pscreen);
 247                 return NULL;
 248         }
 249
 250         /* Vtxprog resources */
 251         if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
 252             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 253                 nv40_screen_destroy(pscreen);
 254                 return NULL;
 255         }
 256
 257         /* Static curie initialisation */
 258         so = so_new(16, 25, 0);
 259         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 260         so_data  (so, screen->sync->handle);
 261         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 262         so_data  (so, chan->vram->handle);
 263         so_data  (so, chan->gart->handle);
 264         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 265         so_data  (so, chan->vram->handle);
 266         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 267         so_data  (so, chan->vram->handle);
 268         so_data  (so, chan->vram->handle);
 269         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 270         so_data  (so, chan->vram->handle);
 271         so_data  (so, chan->gart->handle);
 272         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 273         so_data  (so, 0);
 274         so_data  (so, screen->query->handle);
 275         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 276         so_data  (so, chan->vram->handle);
 277         so_data  (so, chan->vram->handle);
 278         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 279         so_data  (so, chan->vram->handle);
 280         so_data  (so, chan->vram->handle);
 281
 282         so_method(so, screen->curie, 0x1ea4, 3);
 283         so_data  (so, 0x00000010);
 284         so_data  (so, 0x01000100);
 285         so_data  (so, 0xff800006);
 286
 287         /* vtxprog output routing */
 288         so_method(so, screen->curie, 0x1fc4, 1);
 289         so_data  (so, 0x06144321);
 290         so_method(so, screen->curie, 0x1fc8, 2);
 291         so_data  (so, 0xedcba987);
 292         so_data  (so, 0x00000021);
 293         so_method(so, screen->curie, 0x1fd0, 1);
 294         so_data  (so, 0x00171615);
 295         so_method(so, screen->curie, 0x1fd4, 1);
 296         so_data  (so, 0x001b1a19);
 297
 298         so_method(so, screen->curie, 0x1ef8, 1);
 299         so_data  (so, 0x0020ffff);
 300         so_method(so, screen->curie, 0x1d64, 1);
 301         so_data  (so, 0x00d30000);
 302         so_method(so, screen->curie, 0x1e94, 1);
 303         so_data  (so, 0x00000001);
 304
 305         so_emit(chan, so);
 306         so_ref(NULL, &so);
 307         nouveau_pushbuf_flush(chan, 0);
 308
 309         return pscreen;
 310 }
 311