vl: Adapt to dri changes.
[mesa.git] / src / gallium / drivers / nv40 / nv40_screen.c
1 #include "pipe/p_screen.h"
2
3 #include "nv40_context.h"
4 #include "nv40_video_context.h"
5 #include "nv40_screen.h"
6
7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
10
11 static int
12 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
13 {
14 struct nv40_screen *screen = nv40_screen(pscreen);
15
16 switch (param) {
17 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
18 return 16;
19 case PIPE_CAP_NPOT_TEXTURES:
20 return 1;
21 case PIPE_CAP_TWO_SIDED_STENCIL:
22 return 1;
23 case PIPE_CAP_GLSL:
24 return 0;
25 case PIPE_CAP_ANISOTROPIC_FILTER:
26 return 1;
27 case PIPE_CAP_POINT_SPRITE:
28 return 1;
29 case PIPE_CAP_MAX_RENDER_TARGETS:
30 return 4;
31 case PIPE_CAP_OCCLUSION_QUERY:
32 return 1;
33 case PIPE_CAP_TEXTURE_SHADOW_MAP:
34 return 1;
35 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
36 return 13;
37 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
38 return 10;
39 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
40 return 13;
41 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
42 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
43 return 1;
44 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
45 return 0; /* We have 4 - but unsupported currently */
46 case PIPE_CAP_TGSI_CONT_SUPPORTED:
47 return 0;
48 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
49 return 1;
50 case NOUVEAU_CAP_HW_VTXBUF:
51 return 1;
52 case NOUVEAU_CAP_HW_IDXBUF:
53 if (screen->curie->grclass == NV40TCL)
54 return 1;
55 return 0;
56 case PIPE_CAP_INDEP_BLEND_ENABLE:
57 return 0;
58 case PIPE_CAP_INDEP_BLEND_FUNC:
59 return 0;
60 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
61 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
62 return 1;
63 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
64 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
65 return 0;
66 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
67 return 16;
68 default:
69 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
70 return 0;
71 }
72 }
73
74 static float
75 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
76 {
77 switch (param) {
78 case PIPE_CAP_MAX_LINE_WIDTH:
79 case PIPE_CAP_MAX_LINE_WIDTH_AA:
80 return 10.0;
81 case PIPE_CAP_MAX_POINT_WIDTH:
82 case PIPE_CAP_MAX_POINT_WIDTH_AA:
83 return 64.0;
84 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
85 return 16.0;
86 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
87 return 16.0;
88 default:
89 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
90 return 0.0;
91 }
92 }
93
94 static boolean
95 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
96 enum pipe_format format,
97 enum pipe_texture_target target,
98 unsigned tex_usage, unsigned geom_flags)
99 {
100 if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
101 switch (format) {
102 case PIPE_FORMAT_B8G8R8A8_UNORM:
103 case PIPE_FORMAT_B5G6R5_UNORM:
104 return TRUE;
105 default:
106 break;
107 }
108 } else
109 if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
110 switch (format) {
111 case PIPE_FORMAT_S8Z24_UNORM:
112 case PIPE_FORMAT_X8Z24_UNORM:
113 case PIPE_FORMAT_Z16_UNORM:
114 return TRUE;
115 default:
116 break;
117 }
118 } else {
119 switch (format) {
120 case PIPE_FORMAT_B8G8R8A8_UNORM:
121 case PIPE_FORMAT_B5G5R5A1_UNORM:
122 case PIPE_FORMAT_B4G4R4A4_UNORM:
123 case PIPE_FORMAT_B5G6R5_UNORM:
124 case PIPE_FORMAT_R16_SNORM:
125 case PIPE_FORMAT_L8_UNORM:
126 case PIPE_FORMAT_A8_UNORM:
127 case PIPE_FORMAT_I8_UNORM:
128 case PIPE_FORMAT_L8A8_UNORM:
129 case PIPE_FORMAT_Z16_UNORM:
130 case PIPE_FORMAT_S8Z24_UNORM:
131 case PIPE_FORMAT_DXT1_RGB:
132 case PIPE_FORMAT_DXT1_RGBA:
133 case PIPE_FORMAT_DXT3_RGBA:
134 case PIPE_FORMAT_DXT5_RGBA:
135 return TRUE;
136 default:
137 break;
138 }
139 }
140
141 return FALSE;
142 }
143
144 static struct pipe_buffer *
145 nv40_surface_buffer(struct pipe_surface *surf)
146 {
147 struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
148
149 return mt->buffer;
150 }
151
152 static void
153 nv40_screen_destroy(struct pipe_screen *pscreen)
154 {
155 struct nv40_screen *screen = nv40_screen(pscreen);
156 unsigned i;
157
158 for (i = 0; i < NV40_STATE_MAX; i++) {
159 if (screen->state[i])
160 so_ref(NULL, &screen->state[i]);
161 }
162
163 nouveau_resource_destroy(&screen->vp_exec_heap);
164 nouveau_resource_destroy(&screen->vp_data_heap);
165 nouveau_resource_destroy(&screen->query_heap);
166 nouveau_notifier_free(&screen->query);
167 nouveau_notifier_free(&screen->sync);
168 nouveau_grobj_free(&screen->curie);
169 nv04_surface_2d_takedown(&screen->eng2d);
170
171 nouveau_screen_fini(&screen->base);
172
173 FREE(pscreen);
174 }
175
176 struct pipe_screen *
177 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
178 {
179 struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
180 struct nouveau_channel *chan;
181 struct pipe_screen *pscreen;
182 struct nouveau_stateobj *so;
183 unsigned curie_class = 0;
184 int ret;
185
186 if (!screen)
187 return NULL;
188 pscreen = &screen->base.base;
189
190 ret = nouveau_screen_init(&screen->base, dev);
191 if (ret) {
192 nv40_screen_destroy(pscreen);
193 return NULL;
194 }
195 chan = screen->base.channel;
196
197 pscreen->winsys = ws;
198 pscreen->destroy = nv40_screen_destroy;
199 pscreen->get_param = nv40_screen_get_param;
200 pscreen->get_paramf = nv40_screen_get_paramf;
201 pscreen->is_format_supported = nv40_screen_surface_format_supported;
202 pscreen->context_create = nv40_create;
203 pscreen->video_context_create = nv40_video_create;
204
205 nv40_screen_init_miptree_functions(pscreen);
206 nv40_screen_init_transfer_functions(pscreen);
207
208 /* 3D object */
209 switch (dev->chipset & 0xf0) {
210 case 0x40:
211 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
212 curie_class = NV40TCL;
213 else
214 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
215 curie_class = NV44TCL;
216 break;
217 case 0x60:
218 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
219 curie_class = NV44TCL;
220 break;
221 }
222
223 if (!curie_class) {
224 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
225 return NULL;
226 }
227
228 ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
229 if (ret) {
230 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
231 return FALSE;
232 }
233
234 /* 2D engine setup */
235 screen->eng2d = nv04_surface_2d_init(&screen->base);
236 screen->eng2d->buf = nv40_surface_buffer;
237
238 /* Notifier for sync purposes */
239 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
240 if (ret) {
241 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
242 nv40_screen_destroy(pscreen);
243 return NULL;
244 }
245
246 /* Query objects */
247 ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
248 if (ret) {
249 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
250 nv40_screen_destroy(pscreen);
251 return NULL;
252 }
253
254 nouveau_resource_init(&screen->query_heap, 0, 32);
255 if (ret) {
256 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
257 nv40_screen_destroy(pscreen);
258 return NULL;
259 }
260
261 /* Vtxprog resources */
262 if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
263 nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
264 nv40_screen_destroy(pscreen);
265 return NULL;
266 }
267
268 /* Static curie initialisation */
269 so = so_new(16, 25, 0);
270 so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
271 so_data (so, screen->sync->handle);
272 so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
273 so_data (so, chan->vram->handle);
274 so_data (so, chan->gart->handle);
275 so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
276 so_data (so, chan->vram->handle);
277 so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
278 so_data (so, chan->vram->handle);
279 so_data (so, chan->vram->handle);
280 so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
281 so_data (so, chan->vram->handle);
282 so_data (so, chan->gart->handle);
283 so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
284 so_data (so, 0);
285 so_data (so, screen->query->handle);
286 so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
287 so_data (so, chan->vram->handle);
288 so_data (so, chan->vram->handle);
289 so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
290 so_data (so, chan->vram->handle);
291 so_data (so, chan->vram->handle);
292
293 so_method(so, screen->curie, 0x1ea4, 3);
294 so_data (so, 0x00000010);
295 so_data (so, 0x01000100);
296 so_data (so, 0xff800006);
297
298 /* vtxprog output routing */
299 so_method(so, screen->curie, 0x1fc4, 1);
300 so_data (so, 0x06144321);
301 so_method(so, screen->curie, 0x1fc8, 2);
302 so_data (so, 0xedcba987);
303 so_data (so, 0x00000021);
304 so_method(so, screen->curie, 0x1fd0, 1);
305 so_data (so, 0x00171615);
306 so_method(so, screen->curie, 0x1fd4, 1);
307 so_data (so, 0x001b1a19);
308
309 so_method(so, screen->curie, 0x1ef8, 1);
310 so_data (so, 0x0020ffff);
311 so_method(so, screen->curie, 0x1d64, 1);
312 so_data (so, 0x00d30000);
313 so_method(so, screen->curie, 0x1e94, 1);
314 so_data (so, 0x00000001);
315
316 so_emit(chan, so);
317 so_ref(NULL, &so);
318 nouveau_pushbuf_flush(chan, 0);
319
320 return pscreen;
321 }
322