1 #include "pipe/p_screen.h"
3 #include "nv40_context.h"
4 #include "nv40_screen.h"
6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
11 nv40_screen_get_param(struct pipe_screen
*pscreen
, int param
)
13 struct nv40_screen
*screen
= nv40_screen(pscreen
);
16 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
18 case PIPE_CAP_NPOT_TEXTURES
:
20 case PIPE_CAP_TWO_SIDED_STENCIL
:
24 case PIPE_CAP_ANISOTROPIC_FILTER
:
26 case PIPE_CAP_POINT_SPRITE
:
28 case PIPE_CAP_MAX_RENDER_TARGETS
:
30 case PIPE_CAP_OCCLUSION_QUERY
:
32 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
34 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
36 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
38 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
40 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
41 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
43 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
44 return 0; /* We have 4 - but unsupported currently */
45 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
47 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
49 case NOUVEAU_CAP_HW_VTXBUF
:
51 case NOUVEAU_CAP_HW_IDXBUF
:
52 if (screen
->curie
->grclass
== NV40TCL
)
56 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
62 nv40_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
65 case PIPE_CAP_MAX_LINE_WIDTH
:
66 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
68 case PIPE_CAP_MAX_POINT_WIDTH
:
69 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
71 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
73 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
76 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
82 nv40_screen_surface_format_supported(struct pipe_screen
*pscreen
,
83 enum pipe_format format
,
84 enum pipe_texture_target target
,
85 unsigned tex_usage
, unsigned geom_flags
)
87 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
89 case PIPE_FORMAT_A8R8G8B8_UNORM
:
90 case PIPE_FORMAT_R5G6B5_UNORM
:
96 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
98 case PIPE_FORMAT_Z24S8_UNORM
:
99 case PIPE_FORMAT_Z24X8_UNORM
:
100 case PIPE_FORMAT_Z16_UNORM
:
107 case PIPE_FORMAT_A8R8G8B8_UNORM
:
108 case PIPE_FORMAT_A1R5G5B5_UNORM
:
109 case PIPE_FORMAT_A4R4G4B4_UNORM
:
110 case PIPE_FORMAT_R5G6B5_UNORM
:
111 case PIPE_FORMAT_R16_SNORM
:
112 case PIPE_FORMAT_L8_UNORM
:
113 case PIPE_FORMAT_A8_UNORM
:
114 case PIPE_FORMAT_I8_UNORM
:
115 case PIPE_FORMAT_A8L8_UNORM
:
116 case PIPE_FORMAT_Z16_UNORM
:
117 case PIPE_FORMAT_Z24S8_UNORM
:
118 case PIPE_FORMAT_DXT1_RGB
:
119 case PIPE_FORMAT_DXT1_RGBA
:
120 case PIPE_FORMAT_DXT3_RGBA
:
121 case PIPE_FORMAT_DXT5_RGBA
:
131 static struct pipe_buffer
*
132 nv40_surface_buffer(struct pipe_surface
*surf
)
134 struct nv40_miptree
*mt
= (struct nv40_miptree
*)surf
->texture
;
140 nv40_screen_destroy(struct pipe_screen
*pscreen
)
142 struct nv40_screen
*screen
= nv40_screen(pscreen
);
145 for (i
= 0; i
< NV40_STATE_MAX
; i
++) {
146 if (screen
->state
[i
])
147 so_ref(NULL
, &screen
->state
[i
]);
150 nouveau_resource_free(&screen
->vp_exec_heap
);
151 nouveau_resource_free(&screen
->vp_data_heap
);
152 nouveau_resource_free(&screen
->query_heap
);
153 nouveau_notifier_free(&screen
->query
);
154 nouveau_notifier_free(&screen
->sync
);
155 nouveau_grobj_free(&screen
->curie
);
156 nv04_surface_2d_takedown(&screen
->eng2d
);
158 nouveau_screen_fini(&screen
->base
);
164 nv40_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
166 struct nv40_screen
*screen
= CALLOC_STRUCT(nv40_screen
);
167 struct nouveau_channel
*chan
;
168 struct pipe_screen
*pscreen
;
169 struct nouveau_stateobj
*so
;
170 unsigned curie_class
= 0;
175 pscreen
= &screen
->base
.base
;
177 ret
= nouveau_screen_init(&screen
->base
, dev
);
179 nv40_screen_destroy(pscreen
);
182 chan
= screen
->base
.channel
;
184 pscreen
->winsys
= ws
;
185 pscreen
->destroy
= nv40_screen_destroy
;
186 pscreen
->get_param
= nv40_screen_get_param
;
187 pscreen
->get_paramf
= nv40_screen_get_paramf
;
188 pscreen
->is_format_supported
= nv40_screen_surface_format_supported
;
190 nv40_screen_init_miptree_functions(pscreen
);
191 nv40_screen_init_transfer_functions(pscreen
);
194 switch (dev
->chipset
& 0xf0) {
196 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
197 curie_class
= NV40TCL
;
199 if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
200 curie_class
= NV44TCL
;
203 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
204 curie_class
= NV44TCL
;
209 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev
->chipset
);
213 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, curie_class
, &screen
->curie
);
215 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
218 BIND_RING(chan
, screen
->curie
, 7);
220 /* 2D engine setup */
221 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
222 screen
->eng2d
->buf
= nv40_surface_buffer
;
224 /* Notifier for sync purposes */
225 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
227 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
228 nv40_screen_destroy(pscreen
);
233 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, 32, &screen
->query
);
235 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
236 nv40_screen_destroy(pscreen
);
240 nouveau_resource_init(&screen
->query_heap
, 0, 32);
242 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
243 nv40_screen_destroy(pscreen
);
247 /* Vtxprog resources */
248 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, 512) ||
249 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
250 nv40_screen_destroy(pscreen
);
254 /* Static curie initialisation */
256 so_method(so
, screen
->curie
, NV40TCL_DMA_NOTIFY
, 1);
257 so_data (so
, screen
->sync
->handle
);
258 so_method(so
, screen
->curie
, NV40TCL_DMA_TEXTURE0
, 2);
259 so_data (so
, chan
->vram
->handle
);
260 so_data (so
, chan
->gart
->handle
);
261 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR1
, 1);
262 so_data (so
, chan
->vram
->handle
);
263 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR0
, 2);
264 so_data (so
, chan
->vram
->handle
);
265 so_data (so
, chan
->vram
->handle
);
266 so_method(so
, screen
->curie
, NV40TCL_DMA_VTXBUF0
, 2);
267 so_data (so
, chan
->vram
->handle
);
268 so_data (so
, chan
->gart
->handle
);
269 so_method(so
, screen
->curie
, NV40TCL_DMA_FENCE
, 2);
271 so_data (so
, screen
->query
->handle
);
272 so_method(so
, screen
->curie
, NV40TCL_DMA_UNK01AC
, 2);
273 so_data (so
, chan
->vram
->handle
);
274 so_data (so
, chan
->vram
->handle
);
275 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR2
, 2);
276 so_data (so
, chan
->vram
->handle
);
277 so_data (so
, chan
->vram
->handle
);
279 so_method(so
, screen
->curie
, 0x1ea4, 3);
280 so_data (so
, 0x00000010);
281 so_data (so
, 0x01000100);
282 so_data (so
, 0xff800006);
284 /* vtxprog output routing */
285 so_method(so
, screen
->curie
, 0x1fc4, 1);
286 so_data (so
, 0x06144321);
287 so_method(so
, screen
->curie
, 0x1fc8, 2);
288 so_data (so
, 0xedcba987);
289 so_data (so
, 0x00000021);
290 so_method(so
, screen
->curie
, 0x1fd0, 1);
291 so_data (so
, 0x00171615);
292 so_method(so
, screen
->curie
, 0x1fd4, 1);
293 so_data (so
, 0x001b1a19);
295 so_method(so
, screen
->curie
, 0x1ef8, 1);
296 so_data (so
, 0x0020ffff);
297 so_method(so
, screen
->curie
, 0x1d64, 1);
298 so_data (so
, 0x00d30000);
299 so_method(so
, screen
->curie
, 0x1e94, 1);
300 so_data (so
, 0x00000001);
304 nouveau_pushbuf_flush(chan
, 0);