1 #include "pipe/p_screen.h"
3 #include "nv40_context.h"
4 #include "nv40_screen.h"
6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
11 nv40_screen_get_param(struct pipe_screen
*pscreen
, int param
)
13 struct nv40_screen
*screen
= nv40_screen(pscreen
);
16 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
18 case PIPE_CAP_NPOT_TEXTURES
:
20 case PIPE_CAP_TWO_SIDED_STENCIL
:
26 case PIPE_CAP_ANISOTROPIC_FILTER
:
28 case PIPE_CAP_POINT_SPRITE
:
30 case PIPE_CAP_MAX_RENDER_TARGETS
:
32 case PIPE_CAP_OCCLUSION_QUERY
:
34 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
36 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
38 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
40 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
42 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
43 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
45 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
46 return 0; /* We have 4 - but unsupported currently */
47 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
49 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
51 case NOUVEAU_CAP_HW_VTXBUF
:
53 case NOUVEAU_CAP_HW_IDXBUF
:
54 if (screen
->curie
->grclass
== NV40TCL
)
58 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
64 nv40_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
67 case PIPE_CAP_MAX_LINE_WIDTH
:
68 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
70 case PIPE_CAP_MAX_POINT_WIDTH
:
71 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
73 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
75 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
78 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
84 nv40_screen_surface_format_supported(struct pipe_screen
*pscreen
,
85 enum pipe_format format
,
86 enum pipe_texture_target target
,
87 unsigned tex_usage
, unsigned geom_flags
)
89 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
91 case PIPE_FORMAT_A8R8G8B8_UNORM
:
92 case PIPE_FORMAT_R5G6B5_UNORM
:
98 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
100 case PIPE_FORMAT_Z24S8_UNORM
:
101 case PIPE_FORMAT_Z24X8_UNORM
:
102 case PIPE_FORMAT_Z16_UNORM
:
109 case PIPE_FORMAT_A8R8G8B8_UNORM
:
110 case PIPE_FORMAT_A1R5G5B5_UNORM
:
111 case PIPE_FORMAT_A4R4G4B4_UNORM
:
112 case PIPE_FORMAT_R5G6B5_UNORM
:
113 case PIPE_FORMAT_R16_SNORM
:
114 case PIPE_FORMAT_L8_UNORM
:
115 case PIPE_FORMAT_A8_UNORM
:
116 case PIPE_FORMAT_I8_UNORM
:
117 case PIPE_FORMAT_A8L8_UNORM
:
118 case PIPE_FORMAT_Z16_UNORM
:
119 case PIPE_FORMAT_Z24S8_UNORM
:
120 case PIPE_FORMAT_DXT1_RGB
:
121 case PIPE_FORMAT_DXT1_RGBA
:
122 case PIPE_FORMAT_DXT3_RGBA
:
123 case PIPE_FORMAT_DXT5_RGBA
:
133 static struct pipe_buffer
*
134 nv40_surface_buffer(struct pipe_surface
*surf
)
136 struct nv40_miptree
*mt
= (struct nv40_miptree
*)surf
->texture
;
142 nv40_screen_destroy(struct pipe_screen
*pscreen
)
144 struct nv40_screen
*screen
= nv40_screen(pscreen
);
146 nouveau_resource_free(&screen
->vp_exec_heap
);
147 nouveau_resource_free(&screen
->vp_data_heap
);
148 nouveau_resource_free(&screen
->query_heap
);
149 nouveau_notifier_free(&screen
->query
);
150 nouveau_notifier_free(&screen
->sync
);
151 nouveau_grobj_free(&screen
->curie
);
153 nouveau_screen_fini(&screen
->base
);
159 nv40_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
161 struct nv40_screen
*screen
= CALLOC_STRUCT(nv40_screen
);
162 struct nouveau_channel
*chan
;
163 struct pipe_screen
*pscreen
;
164 struct nouveau_stateobj
*so
;
165 unsigned curie_class
= 0;
170 pscreen
= &screen
->base
.base
;
172 ret
= nouveau_screen_init(&screen
->base
, dev
);
174 nv40_screen_destroy(pscreen
);
177 chan
= screen
->base
.channel
;
179 pscreen
->winsys
= ws
;
180 pscreen
->destroy
= nv40_screen_destroy
;
181 pscreen
->get_param
= nv40_screen_get_param
;
182 pscreen
->get_paramf
= nv40_screen_get_paramf
;
183 pscreen
->is_format_supported
= nv40_screen_surface_format_supported
;
185 nv40_screen_init_miptree_functions(pscreen
);
186 nv40_screen_init_transfer_functions(pscreen
);
189 switch (dev
->chipset
& 0xf0) {
191 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
192 curie_class
= NV40TCL
;
194 if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
195 curie_class
= NV44TCL
;
198 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
199 curie_class
= NV44TCL
;
204 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev
->chipset
);
208 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, curie_class
, &screen
->curie
);
210 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
213 BIND_RING(chan
, screen
->curie
, 7);
215 /* 2D engine setup */
216 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
217 screen
->eng2d
->buf
= nv40_surface_buffer
;
219 /* Notifier for sync purposes */
220 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
222 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
223 nv40_screen_destroy(pscreen
);
228 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, 32, &screen
->query
);
230 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
231 nv40_screen_destroy(pscreen
);
235 nouveau_resource_init(&screen
->query_heap
, 0, 32);
237 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
238 nv40_screen_destroy(pscreen
);
242 /* Vtxprog resources */
243 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, 512) ||
244 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
245 nv40_screen_destroy(pscreen
);
249 /* Static curie initialisation */
251 so_method(so
, screen
->curie
, NV40TCL_DMA_NOTIFY
, 1);
252 so_data (so
, screen
->sync
->handle
);
253 so_method(so
, screen
->curie
, NV40TCL_DMA_TEXTURE0
, 2);
254 so_data (so
, chan
->vram
->handle
);
255 so_data (so
, chan
->gart
->handle
);
256 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR1
, 1);
257 so_data (so
, chan
->vram
->handle
);
258 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR0
, 2);
259 so_data (so
, chan
->vram
->handle
);
260 so_data (so
, chan
->vram
->handle
);
261 so_method(so
, screen
->curie
, NV40TCL_DMA_VTXBUF0
, 2);
262 so_data (so
, chan
->vram
->handle
);
263 so_data (so
, chan
->gart
->handle
);
264 so_method(so
, screen
->curie
, NV40TCL_DMA_FENCE
, 2);
266 so_data (so
, screen
->query
->handle
);
267 so_method(so
, screen
->curie
, NV40TCL_DMA_UNK01AC
, 2);
268 so_data (so
, chan
->vram
->handle
);
269 so_data (so
, chan
->vram
->handle
);
270 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR2
, 2);
271 so_data (so
, chan
->vram
->handle
);
272 so_data (so
, chan
->vram
->handle
);
274 so_method(so
, screen
->curie
, 0x1ea4, 3);
275 so_data (so
, 0x00000010);
276 so_data (so
, 0x01000100);
277 so_data (so
, 0xff800006);
279 /* vtxprog output routing */
280 so_method(so
, screen
->curie
, 0x1fc4, 1);
281 so_data (so
, 0x06144321);
282 so_method(so
, screen
->curie
, 0x1fc8, 2);
283 so_data (so
, 0xedcba987);
284 so_data (so
, 0x00000021);
285 so_method(so
, screen
->curie
, 0x1fd0, 1);
286 so_data (so
, 0x00171615);
287 so_method(so
, screen
->curie
, 0x1fd4, 1);
288 so_data (so
, 0x001b1a19);
290 so_method(so
, screen
->curie
, 0x1ef8, 1);
291 so_data (so
, 0x0020ffff);
292 so_method(so
, screen
->curie
, 0x1d64, 1);
293 so_data (so
, 0x00d30000);
294 so_method(so
, screen
->curie
, 0x1e94, 1);
295 so_data (so
, 0x00000001);
299 nouveau_pushbuf_flush(chan
, 0);