src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "util/u_simple_screen.h"
   3
   4 #include "nv40_context.h"
   5 #include "nv40_screen.h"
   6
   7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  10
  11 static const char *
  12 nv40_screen_get_name(struct pipe_screen *pscreen)
  13 {
  14         struct nv40_screen *screen = nv40_screen(pscreen);
  15         struct nouveau_device *dev = screen->nvws->channel->device;
  16         static char buffer[128];
  17
  18         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  19         return buffer;
  20 }
  21
  22 static const char *
  23 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  24 {
  25         return "nouveau";
  26 }
  27
  28 static int
  29 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  30 {
  31         struct nv40_screen *screen = nv40_screen(pscreen);
  32
  33         switch (param) {
  34         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  35                 return 16;
  36         case PIPE_CAP_NPOT_TEXTURES:
  37                 return 1;
  38         case PIPE_CAP_TWO_SIDED_STENCIL:
  39                 return 1;
  40         case PIPE_CAP_GLSL:
  41                 return 0;
  42         case PIPE_CAP_S3TC:
  43                 return 1;
  44         case PIPE_CAP_ANISOTROPIC_FILTER:
  45                 return 1;
  46         case PIPE_CAP_POINT_SPRITE:
  47                 return 1;
  48         case PIPE_CAP_MAX_RENDER_TARGETS:
  49                 return 4;
  50         case PIPE_CAP_OCCLUSION_QUERY:
  51                 return 1;
  52         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  53                 return 1;
  54         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  57                 return 10;
  58         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  59                 return 13;
  60         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  62                 return 1;
  63         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  64                 return 0; /* We have 4 - but unsupported currently */
  65         case NOUVEAU_CAP_HW_VTXBUF:
  66                 return 1;
  67         case NOUVEAU_CAP_HW_IDXBUF:
  68                 if (screen->curie->grclass == NV40TCL)
  69                         return 1;
  70                 return 0;
  71         default:
  72                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  73                 return 0;
  74         }
  75 }
  76
  77 static float
  78 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  79 {
  80         switch (param) {
  81         case PIPE_CAP_MAX_LINE_WIDTH:
  82         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  83                 return 10.0;
  84         case PIPE_CAP_MAX_POINT_WIDTH:
  85         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  86                 return 64.0;
  87         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  88                 return 16.0;
  89         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  90                 return 16.0;
  91         default:
  92                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  93                 return 0.0;
  94         }
  95 }
  96
  97 static boolean
  98 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  99                                      enum pipe_format format,
 100                                      enum pipe_texture_target target,
 101                                      unsigned tex_usage, unsigned geom_flags)
 102 {
 103         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 104                 switch (format) {
 105                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 106                 case PIPE_FORMAT_R5G6B5_UNORM:
 107                 case PIPE_FORMAT_Z24S8_UNORM:
 108                 case PIPE_FORMAT_Z16_UNORM:
 109                         return TRUE;
 110                 default:
 111                         break;
 112                 }
 113         } else {
 114                 switch (format) {
 115                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 116                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 117                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 118                 case PIPE_FORMAT_R5G6B5_UNORM:
 119                 case PIPE_FORMAT_R16_SNORM:
 120                 case PIPE_FORMAT_L8_UNORM:
 121                 case PIPE_FORMAT_A8_UNORM:
 122                 case PIPE_FORMAT_I8_UNORM:
 123                 case PIPE_FORMAT_A8L8_UNORM:
 124                 case PIPE_FORMAT_Z16_UNORM:
 125                 case PIPE_FORMAT_Z24S8_UNORM:
 126                 case PIPE_FORMAT_DXT1_RGB:
 127                 case PIPE_FORMAT_DXT1_RGBA:
 128                 case PIPE_FORMAT_DXT3_RGBA:
 129                 case PIPE_FORMAT_DXT5_RGBA:
 130                         return TRUE;
 131                 default:
 132                         break;
 133                 }
 134         }
 135
 136         return FALSE;
 137 }
 138
 139 static void *
 140 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 141                  unsigned flags )
 142 {
 143         struct pipe_winsys      *ws = screen->winsys;
 144         struct pipe_surface     *surface_to_map;
 145         void                    *map;
 146
 147         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 148                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 149
 150                 if (!mt->shadow_tex) {
 151                         unsigned old_tex_usage = surface->texture->tex_usage;
 152                         surface->texture->tex_usage = NOUVEAU_TEXTURE_USAGE_LINEAR |
 153                                                       PIPE_TEXTURE_USAGE_DYNAMIC;
 154                         mt->shadow_tex = screen->texture_create(screen, surface->texture);
 155                         surface->texture->tex_usage = old_tex_usage;
 156
 157                         assert(mt->shadow_tex->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR);
 158                 }
 159
 160                 mt->shadow_surface = screen->get_tex_surface
 161                 (
 162                         screen, mt->shadow_tex,
 163                         surface->face, surface->level, surface->zslice,
 164                         surface->usage
 165                 );
 166
 167                 surface_to_map = mt->shadow_surface;
 168         }
 169         else
 170                 surface_to_map = surface;
 171
 172         assert(surface_to_map);
 173
 174         map = ws->buffer_map(ws, surface_to_map->buffer, flags);
 175         if (!map)
 176                 return NULL;
 177
 178         return map + surface_to_map->offset;
 179 }
 180
 181 static void
 182 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 183 {
 184         struct pipe_winsys      *ws = screen->winsys;
 185         struct pipe_surface     *surface_to_unmap;
 186
 187         /* TODO: Copy from shadow just before push buffer is flushed instead.
 188                  There are probably some programs that map/unmap excessively
 189                  before rendering. */
 190         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 191                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 192
 193                 assert(mt->shadow_tex);
 194
 195                 surface_to_unmap = mt->shadow_surface;
 196         }
 197         else
 198                 surface_to_unmap = surface;
 199
 200         assert(surface_to_unmap);
 201
 202         ws->buffer_unmap(ws, surface_to_unmap->buffer);
 203
 204         if (surface_to_unmap != surface) {
 205                 struct nv40_screen *nvscreen = nv40_screen(screen);
 206
 207                 nvscreen->nvws->surface_copy(nvscreen->nvws,
 208                                              surface, 0, 0,
 209                                              surface_to_unmap, 0, 0,
 210                                              surface->width, surface->height);
 211         }
 212 }
 213
 214 static void
 215 nv40_screen_destroy(struct pipe_screen *pscreen)
 216 {
 217         struct nv40_screen *screen = nv40_screen(pscreen);
 218         struct nouveau_winsys *nvws = screen->nvws;
 219
 220         nvws->res_free(&screen->vp_exec_heap);
 221         nvws->res_free(&screen->vp_data_heap);
 222         nvws->res_free(&screen->query_heap);
 223         nvws->notifier_free(&screen->query);
 224         nvws->notifier_free(&screen->sync);
 225         nvws->grobj_free(&screen->curie);
 226
 227         FREE(pscreen);
 228 }
 229
 230 struct pipe_screen *
 231 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 232 {
 233         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 234         struct nouveau_stateobj *so;
 235         unsigned curie_class;
 236         unsigned chipset = nvws->channel->device->chipset;
 237         int ret;
 238
 239         if (!screen)
 240                 return NULL;
 241         screen->nvws = nvws;
 242
 243         /* 3D object */
 244         switch (chipset & 0xf0) {
 245         case 0x40:
 246                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 247                         curie_class = NV40TCL;
 248                 else
 249                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 250                         curie_class = NV44TCL;
 251                 break;
 252         case 0x60:
 253                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 254                         curie_class = NV44TCL;
 255                 break;
 256         default:
 257                 break;
 258         }
 259
 260         if (!curie_class) {
 261                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 262                 return NULL;
 263         }
 264
 265         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 266         if (ret) {
 267                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 268                 return FALSE;
 269         }
 270
 271         /* Notifier for sync purposes */
 272         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 273         if (ret) {
 274                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 275                 nv40_screen_destroy(&screen->pipe);
 276                 return NULL;
 277         }
 278
 279         /* Query objects */
 280         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 281         if (ret) {
 282                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 283                 nv40_screen_destroy(&screen->pipe);
 284                 return NULL;
 285         }
 286
 287         ret = nvws->res_init(&screen->query_heap, 0, 32);
 288         if (ret) {
 289                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 290                 nv40_screen_destroy(&screen->pipe);
 291                 return NULL;
 292         }
 293
 294         /* Vtxprog resources */
 295         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 296             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 297                 nv40_screen_destroy(&screen->pipe);
 298                 return NULL;
 299         }
 300
 301         /* Static curie initialisation */
 302         so = so_new(128, 0);
 303         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 304         so_data  (so, screen->sync->handle);
 305         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 306         so_data  (so, nvws->channel->vram->handle);
 307         so_data  (so, nvws->channel->gart->handle);
 308         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 309         so_data  (so, nvws->channel->vram->handle);
 310         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 311         so_data  (so, nvws->channel->vram->handle);
 312         so_data  (so, nvws->channel->vram->handle);
 313         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 314         so_data  (so, nvws->channel->vram->handle);
 315         so_data  (so, nvws->channel->gart->handle);
 316         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 317         so_data  (so, 0);
 318         so_data  (so, screen->query->handle);
 319         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 320         so_data  (so, nvws->channel->vram->handle);
 321         so_data  (so, nvws->channel->vram->handle);
 322         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 323         so_data  (so, nvws->channel->vram->handle);
 324         so_data  (so, nvws->channel->vram->handle);
 325
 326         so_method(so, screen->curie, 0x1ea4, 3);
 327         so_data  (so, 0x00000010);
 328         so_data  (so, 0x01000100);
 329         so_data  (so, 0xff800006);
 330
 331         /* vtxprog output routing */
 332         so_method(so, screen->curie, 0x1fc4, 1);
 333         so_data  (so, 0x06144321);
 334         so_method(so, screen->curie, 0x1fc8, 2);
 335         so_data  (so, 0xedcba987);
 336         so_data  (so, 0x00000021);
 337         so_method(so, screen->curie, 0x1fd0, 1);
 338         so_data  (so, 0x00171615);
 339         so_method(so, screen->curie, 0x1fd4, 1);
 340         so_data  (so, 0x001b1a19);
 341
 342         so_method(so, screen->curie, 0x1ef8, 1);
 343         so_data  (so, 0x0020ffff);
 344         so_method(so, screen->curie, 0x1d64, 1);
 345         so_data  (so, 0x00d30000);
 346         so_method(so, screen->curie, 0x1e94, 1);
 347         so_data  (so, 0x00000001);
 348
 349         so_emit(nvws, so);
 350         so_ref(NULL, &so);
 351         nvws->push_flush(nvws, 0, NULL);
 352
 353         screen->pipe.winsys = ws;
 354         screen->pipe.destroy = nv40_screen_destroy;
 355
 356         screen->pipe.get_name = nv40_screen_get_name;
 357         screen->pipe.get_vendor = nv40_screen_get_vendor;
 358         screen->pipe.get_param = nv40_screen_get_param;
 359         screen->pipe.get_paramf = nv40_screen_get_paramf;
 360
 361         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 362
 363         screen->pipe.surface_map = nv40_surface_map;
 364         screen->pipe.surface_unmap = nv40_surface_unmap;
 365
 366         nv40_screen_init_miptree_functions(&screen->pipe);
 367         u_simple_screen_init(&screen->pipe);
 368
 369         return &screen->pipe;
 370 }
 371