1 #include "pipe/p_screen.h"
3 #include "nv40_context.h"
4 #include "nv40_screen.h"
6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
11 nv40_screen_get_param(struct pipe_screen
*pscreen
, int param
)
13 struct nv40_screen
*screen
= nv40_screen(pscreen
);
16 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
18 case PIPE_CAP_NPOT_TEXTURES
:
20 case PIPE_CAP_TWO_SIDED_STENCIL
:
24 case PIPE_CAP_ANISOTROPIC_FILTER
:
26 case PIPE_CAP_POINT_SPRITE
:
28 case PIPE_CAP_MAX_RENDER_TARGETS
:
30 case PIPE_CAP_OCCLUSION_QUERY
:
32 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
34 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
36 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
38 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
40 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
41 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
43 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
44 return 0; /* We have 4 - but unsupported currently */
45 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
47 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
49 case NOUVEAU_CAP_HW_VTXBUF
:
51 case NOUVEAU_CAP_HW_IDXBUF
:
52 if (screen
->curie
->grclass
== NV40TCL
)
56 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
62 nv40_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
65 case PIPE_CAP_MAX_LINE_WIDTH
:
66 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
68 case PIPE_CAP_MAX_POINT_WIDTH
:
69 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
71 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
73 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
76 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
82 nv40_screen_surface_format_supported(struct pipe_screen
*pscreen
,
83 enum pipe_format format
,
84 enum pipe_texture_target target
,
85 unsigned tex_usage
, unsigned geom_flags
)
87 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
89 case PIPE_FORMAT_A8R8G8B8_UNORM
:
90 case PIPE_FORMAT_R5G6B5_UNORM
:
96 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
98 case PIPE_FORMAT_Z24S8_UNORM
:
99 case PIPE_FORMAT_Z24X8_UNORM
:
100 case PIPE_FORMAT_Z16_UNORM
:
107 case PIPE_FORMAT_A8R8G8B8_UNORM
:
108 case PIPE_FORMAT_A1R5G5B5_UNORM
:
109 case PIPE_FORMAT_A4R4G4B4_UNORM
:
110 case PIPE_FORMAT_R5G6B5_UNORM
:
111 case PIPE_FORMAT_R16_SNORM
:
112 case PIPE_FORMAT_L8_UNORM
:
113 case PIPE_FORMAT_A8_UNORM
:
114 case PIPE_FORMAT_I8_UNORM
:
115 case PIPE_FORMAT_A8L8_UNORM
:
116 case PIPE_FORMAT_Z16_UNORM
:
117 case PIPE_FORMAT_Z24S8_UNORM
:
118 case PIPE_FORMAT_DXT1_RGB
:
119 case PIPE_FORMAT_DXT1_RGBA
:
120 case PIPE_FORMAT_DXT3_RGBA
:
121 case PIPE_FORMAT_DXT5_RGBA
:
131 static struct pipe_buffer
*
132 nv40_surface_buffer(struct pipe_surface
*surf
)
134 struct nv40_miptree
*mt
= (struct nv40_miptree
*)surf
->texture
;
140 nv40_screen_destroy(struct pipe_screen
*pscreen
)
142 struct nv40_screen
*screen
= nv40_screen(pscreen
);
144 nouveau_resource_free(&screen
->vp_exec_heap
);
145 nouveau_resource_free(&screen
->vp_data_heap
);
146 nouveau_resource_free(&screen
->query_heap
);
147 nouveau_notifier_free(&screen
->query
);
148 nouveau_notifier_free(&screen
->sync
);
149 nouveau_grobj_free(&screen
->curie
);
151 nouveau_screen_fini(&screen
->base
);
157 nv40_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
159 struct nv40_screen
*screen
= CALLOC_STRUCT(nv40_screen
);
160 struct nouveau_channel
*chan
;
161 struct pipe_screen
*pscreen
;
162 struct nouveau_stateobj
*so
;
163 unsigned curie_class
= 0;
168 pscreen
= &screen
->base
.base
;
170 ret
= nouveau_screen_init(&screen
->base
, dev
);
172 nv40_screen_destroy(pscreen
);
175 chan
= screen
->base
.channel
;
177 pscreen
->winsys
= ws
;
178 pscreen
->destroy
= nv40_screen_destroy
;
179 pscreen
->get_param
= nv40_screen_get_param
;
180 pscreen
->get_paramf
= nv40_screen_get_paramf
;
181 pscreen
->is_format_supported
= nv40_screen_surface_format_supported
;
183 nv40_screen_init_miptree_functions(pscreen
);
184 nv40_screen_init_transfer_functions(pscreen
);
187 switch (dev
->chipset
& 0xf0) {
189 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
190 curie_class
= NV40TCL
;
192 if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
193 curie_class
= NV44TCL
;
196 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
197 curie_class
= NV44TCL
;
202 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev
->chipset
);
206 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, curie_class
, &screen
->curie
);
208 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
211 BIND_RING(chan
, screen
->curie
, 7);
213 /* 2D engine setup */
214 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
215 screen
->eng2d
->buf
= nv40_surface_buffer
;
217 /* Notifier for sync purposes */
218 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
220 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
221 nv40_screen_destroy(pscreen
);
226 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, 32, &screen
->query
);
228 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
229 nv40_screen_destroy(pscreen
);
233 nouveau_resource_init(&screen
->query_heap
, 0, 32);
235 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
236 nv40_screen_destroy(pscreen
);
240 /* Vtxprog resources */
241 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, 512) ||
242 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
243 nv40_screen_destroy(pscreen
);
247 /* Static curie initialisation */
249 so_method(so
, screen
->curie
, NV40TCL_DMA_NOTIFY
, 1);
250 so_data (so
, screen
->sync
->handle
);
251 so_method(so
, screen
->curie
, NV40TCL_DMA_TEXTURE0
, 2);
252 so_data (so
, chan
->vram
->handle
);
253 so_data (so
, chan
->gart
->handle
);
254 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR1
, 1);
255 so_data (so
, chan
->vram
->handle
);
256 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR0
, 2);
257 so_data (so
, chan
->vram
->handle
);
258 so_data (so
, chan
->vram
->handle
);
259 so_method(so
, screen
->curie
, NV40TCL_DMA_VTXBUF0
, 2);
260 so_data (so
, chan
->vram
->handle
);
261 so_data (so
, chan
->gart
->handle
);
262 so_method(so
, screen
->curie
, NV40TCL_DMA_FENCE
, 2);
264 so_data (so
, screen
->query
->handle
);
265 so_method(so
, screen
->curie
, NV40TCL_DMA_UNK01AC
, 2);
266 so_data (so
, chan
->vram
->handle
);
267 so_data (so
, chan
->vram
->handle
);
268 so_method(so
, screen
->curie
, NV40TCL_DMA_COLOR2
, 2);
269 so_data (so
, chan
->vram
->handle
);
270 so_data (so
, chan
->vram
->handle
);
272 so_method(so
, screen
->curie
, 0x1ea4, 3);
273 so_data (so
, 0x00000010);
274 so_data (so
, 0x01000100);
275 so_data (so
, 0xff800006);
277 /* vtxprog output routing */
278 so_method(so
, screen
->curie
, 0x1fc4, 1);
279 so_data (so
, 0x06144321);
280 so_method(so
, screen
->curie
, 0x1fc8, 2);
281 so_data (so
, 0xedcba987);
282 so_data (so
, 0x00000021);
283 so_method(so
, screen
->curie
, 0x1fd0, 1);
284 so_data (so
, 0x00171615);
285 so_method(so
, screen
->curie
, 0x1fd4, 1);
286 so_data (so
, 0x001b1a19);
288 so_method(so
, screen
->curie
, 0x1ef8, 1);
289 so_data (so
, 0x0020ffff);
290 so_method(so
, screen
->curie
, 0x1d64, 1);
291 so_data (so
, 0x00d30000);
292 so_method(so
, screen
->curie
, 0x1e94, 1);
293 so_data (so
, 0x00000001);
297 nouveau_pushbuf_flush(chan
, 0);