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120dc42f7b1beebbefa8c2cfabaac0c438ec1320
[mesa.git] / src / gallium / drivers / nv40 / nv40_state.c
1 #include "pipe/p_state.h"
2 #include "pipe/p_defines.h"
3 #include "util/u_inlines.h"
4
5 #include "draw/draw_context.h"
6
7 #include "tgsi/tgsi_parse.h"
8
9 #include "nv40_context.h"
10 #include "nv40_state.h"
11
12 static void *
13 nv40_blend_state_create(struct pipe_context *pipe,
14 const struct pipe_blend_state *cso)
15 {
16 struct nv40_context *nv40 = nv40_context(pipe);
17 struct nouveau_grobj *curie = nv40->screen->curie;
18 struct nv40_blend_state *bso = CALLOC(1, sizeof(*bso));
19 struct nouveau_stateobj *so = so_new(5, 8, 0);
20
21 if (cso->rt[0].blend_enable) {
22 so_method(so, curie, NV40TCL_BLEND_ENABLE, 3);
23 so_data (so, 1);
24 so_data (so, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
25 nvgl_blend_func(cso->rt[0].rgb_src_factor));
26 so_data (so, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 |
27 nvgl_blend_func(cso->rt[0].rgb_dst_factor));
28 so_method(so, curie, NV40TCL_BLEND_EQUATION, 1);
29 so_data (so, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 |
30 nvgl_blend_eqn(cso->rt[0].rgb_func));
31 } else {
32 so_method(so, curie, NV40TCL_BLEND_ENABLE, 1);
33 so_data (so, 0);
34 }
35
36 so_method(so, curie, NV40TCL_COLOR_MASK, 1);
37 so_data (so, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
38 ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
39 ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) |
40 ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 << 0) : 0)));
41
42 if (cso->logicop_enable) {
43 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
44 so_data (so, 1);
45 so_data (so, nvgl_logicop_func(cso->logicop_func));
46 } else {
47 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
48 so_data (so, 0);
49 }
50
51 so_method(so, curie, NV40TCL_DITHER_ENABLE, 1);
52 so_data (so, cso->dither ? 1 : 0);
53
54 so_ref(so, &bso->so);
55 so_ref(NULL, &so);
56 bso->pipe = *cso;
57 return (void *)bso;
58 }
59
60 static void
61 nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
62 {
63 struct nv40_context *nv40 = nv40_context(pipe);
64
65 nv40->blend = hwcso;
66 nv40->dirty |= NV40_NEW_BLEND;
67 }
68
69 static void
70 nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
71 {
72 struct nv40_blend_state *bso = hwcso;
73
74 so_ref(NULL, &bso->so);
75 FREE(bso);
76 }
77
78
79 static INLINE unsigned
80 wrap_mode(unsigned wrap) {
81 unsigned ret;
82
83 switch (wrap) {
84 case PIPE_TEX_WRAP_REPEAT:
85 ret = NV40TCL_TEX_WRAP_S_REPEAT;
86 break;
87 case PIPE_TEX_WRAP_MIRROR_REPEAT:
88 ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
89 break;
90 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
91 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
92 break;
93 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
94 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
95 break;
96 case PIPE_TEX_WRAP_CLAMP:
97 ret = NV40TCL_TEX_WRAP_S_CLAMP;
98 break;
99 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
100 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
101 break;
102 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
103 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
104 break;
105 case PIPE_TEX_WRAP_MIRROR_CLAMP:
106 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
107 break;
108 default:
109 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
110 ret = NV40TCL_TEX_WRAP_S_REPEAT;
111 break;
112 }
113
114 return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
115 }
116
117 static void *
118 nv40_sampler_state_create(struct pipe_context *pipe,
119 const struct pipe_sampler_state *cso)
120 {
121 struct nv40_sampler_state *ps;
122 uint32_t filter = 0;
123
124 ps = MALLOC(sizeof(struct nv40_sampler_state));
125
126 ps->fmt = 0;
127 if (!cso->normalized_coords)
128 ps->fmt |= NV40TCL_TEX_FORMAT_RECT;
129
130 ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) |
131 (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
132 (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT));
133
134 ps->en = 0;
135 if (cso->max_anisotropy >= 2) {
136 /* no idea, binary driver sets it, works without it.. meh.. */
137 ps->wrap |= (1 << 5);
138
139 if (cso->max_anisotropy >= 16) {
140 ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
141 } else
142 if (cso->max_anisotropy >= 12) {
143 ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
144 } else
145 if (cso->max_anisotropy >= 10) {
146 ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
147 } else
148 if (cso->max_anisotropy >= 8) {
149 ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
150 } else
151 if (cso->max_anisotropy >= 6) {
152 ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
153 } else
154 if (cso->max_anisotropy >= 4) {
155 ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
156 } else {
157 ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
158 }
159 }
160
161 switch (cso->mag_img_filter) {
162 case PIPE_TEX_FILTER_LINEAR:
163 filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
164 break;
165 case PIPE_TEX_FILTER_NEAREST:
166 default:
167 filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
168 break;
169 }
170
171 switch (cso->min_img_filter) {
172 case PIPE_TEX_FILTER_LINEAR:
173 switch (cso->min_mip_filter) {
174 case PIPE_TEX_MIPFILTER_NEAREST:
175 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
176 break;
177 case PIPE_TEX_MIPFILTER_LINEAR:
178 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
179 break;
180 case PIPE_TEX_MIPFILTER_NONE:
181 default:
182 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
183 break;
184 }
185 break;
186 case PIPE_TEX_FILTER_NEAREST:
187 default:
188 switch (cso->min_mip_filter) {
189 case PIPE_TEX_MIPFILTER_NEAREST:
190 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
191 break;
192 case PIPE_TEX_MIPFILTER_LINEAR:
193 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
194 break;
195 case PIPE_TEX_MIPFILTER_NONE:
196 default:
197 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
198 break;
199 }
200 break;
201 }
202
203 ps->filt = filter;
204
205 {
206 float limit;
207
208 limit = CLAMP(cso->lod_bias, -16.0, 15.0);
209 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
210
211 limit = CLAMP(cso->max_lod, 0.0, 15.0);
212 ps->en |= (int)(limit * 256.0) << 7;
213
214 limit = CLAMP(cso->min_lod, 0.0, 15.0);
215 ps->en |= (int)(limit * 256.0) << 19;
216 }
217
218
219 if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
220 switch (cso->compare_func) {
221 case PIPE_FUNC_NEVER:
222 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NEVER;
223 break;
224 case PIPE_FUNC_GREATER:
225 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GREATER;
226 break;
227 case PIPE_FUNC_EQUAL:
228 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_EQUAL;
229 break;
230 case PIPE_FUNC_GEQUAL:
231 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GEQUAL;
232 break;
233 case PIPE_FUNC_LESS:
234 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LESS;
235 break;
236 case PIPE_FUNC_NOTEQUAL:
237 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL;
238 break;
239 case PIPE_FUNC_LEQUAL:
240 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LEQUAL;
241 break;
242 case PIPE_FUNC_ALWAYS:
243 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_ALWAYS;
244 break;
245 default:
246 break;
247 }
248 }
249
250 ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
251 (float_to_ubyte(cso->border_color[0]) << 16) |
252 (float_to_ubyte(cso->border_color[1]) << 8) |
253 (float_to_ubyte(cso->border_color[2]) << 0));
254
255 return (void *)ps;
256 }
257
258 static void
259 nv40_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
260 {
261 struct nv40_context *nv40 = nv40_context(pipe);
262 unsigned unit;
263
264 for (unit = 0; unit < nr; unit++) {
265 nv40->tex_sampler[unit] = sampler[unit];
266 nv40->dirty_samplers |= (1 << unit);
267 }
268
269 for (unit = nr; unit < nv40->nr_samplers; unit++) {
270 nv40->tex_sampler[unit] = NULL;
271 nv40->dirty_samplers |= (1 << unit);
272 }
273
274 nv40->nr_samplers = nr;
275 nv40->dirty |= NV40_NEW_SAMPLER;
276 }
277
278 static void
279 nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
280 {
281 FREE(hwcso);
282 }
283
284 static void
285 nv40_set_fragment_sampler_views(struct pipe_context *pipe,
286 unsigned nr,
287 struct pipe_sampler_view **views)
288 {
289 struct nv40_context *nv40 = nv40_context(pipe);
290 unsigned unit;
291
292 for (unit = 0; unit < nr; unit++) {
293 pipe_sampler_view_reference(&nv40->fragment_sampler_views[unit], views[unit]);
294 pipe_texture_reference((struct pipe_texture **)
295 &nv40->tex_miptree[unit], views[unit]->texture);
296 nv40->dirty_samplers |= (1 << unit);
297 }
298
299 for (unit = nr; unit < nv40->nr_textures; unit++) {
300 pipe_sampler_view_reference(&nv40->fragment_sampler_views[unit], NULL);
301 pipe_texture_reference((struct pipe_texture **)
302 &nv40->tex_miptree[unit], NULL);
303 nv40->dirty_samplers |= (1 << unit);
304 }
305
306 nv40->nr_textures = nr;
307 nv40->dirty |= NV40_NEW_SAMPLER;
308 }
309
310 static struct pipe_sampler_view *
311 nv40_create_sampler_view(struct pipe_context *pipe,
312 struct pipe_texture *texture,
313 const struct pipe_sampler_view *templ)
314 {
315 struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
316
317 *view = *templ;
318 view->reference.count = 1;
319 view->texture = NULL;
320 pipe_texture_reference(&view->texture, texture);
321 view->context = pipe;
322
323 return view;
324 }
325
326
327 static void
328 nv40_sampler_view_destroy(struct pipe_context *pipe,
329 struct pipe_sampler_view *view)
330 {
331 pipe_texture_reference(&view->texture, NULL);
332 FREE(view);
333 }
334
335 static void *
336 nv40_rasterizer_state_create(struct pipe_context *pipe,
337 const struct pipe_rasterizer_state *cso)
338 {
339 struct nv40_context *nv40 = nv40_context(pipe);
340 struct nv40_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
341 struct nouveau_stateobj *so = so_new(9, 19, 0);
342 struct nouveau_grobj *curie = nv40->screen->curie;
343
344 /*XXX: ignored:
345 * light_twoside
346 * point_smooth -nohw
347 * multisample
348 */
349
350 so_method(so, curie, NV40TCL_SHADE_MODEL, 1);
351 so_data (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT :
352 NV40TCL_SHADE_MODEL_SMOOTH);
353
354 so_method(so, curie, NV40TCL_LINE_WIDTH, 2);
355 so_data (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
356 so_data (so, cso->line_smooth ? 1 : 0);
357 so_method(so, curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
358 so_data (so, cso->line_stipple_enable ? 1 : 0);
359 so_data (so, (cso->line_stipple_pattern << 16) |
360 cso->line_stipple_factor);
361
362 so_method(so, curie, NV40TCL_POINT_SIZE, 1);
363 so_data (so, fui(cso->point_size));
364
365 so_method(so, curie, NV40TCL_POLYGON_MODE_FRONT, 6);
366 if (cso->front_winding == PIPE_WINDING_CCW) {
367 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
368 so_data(so, nvgl_polygon_mode(cso->fill_cw));
369 switch (cso->cull_mode) {
370 case PIPE_WINDING_CCW:
371 so_data(so, NV40TCL_CULL_FACE_FRONT);
372 break;
373 case PIPE_WINDING_CW:
374 so_data(so, NV40TCL_CULL_FACE_BACK);
375 break;
376 case PIPE_WINDING_BOTH:
377 so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
378 break;
379 default:
380 so_data(so, NV40TCL_CULL_FACE_BACK);
381 break;
382 }
383 so_data(so, NV40TCL_FRONT_FACE_CCW);
384 } else {
385 so_data(so, nvgl_polygon_mode(cso->fill_cw));
386 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
387 switch (cso->cull_mode) {
388 case PIPE_WINDING_CCW:
389 so_data(so, NV40TCL_CULL_FACE_BACK);
390 break;
391 case PIPE_WINDING_CW:
392 so_data(so, NV40TCL_CULL_FACE_FRONT);
393 break;
394 case PIPE_WINDING_BOTH:
395 so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
396 break;
397 default:
398 so_data(so, NV40TCL_CULL_FACE_BACK);
399 break;
400 }
401 so_data(so, NV40TCL_FRONT_FACE_CW);
402 }
403 so_data(so, cso->poly_smooth ? 1 : 0);
404 so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
405
406 so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
407 so_data (so, cso->poly_stipple_enable ? 1 : 0);
408
409 so_method(so, curie, NV40TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
410 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
411 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
412 so_data(so, 1);
413 else
414 so_data(so, 0);
415 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_LINE) ||
416 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_LINE))
417 so_data(so, 1);
418 else
419 so_data(so, 0);
420 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_FILL) ||
421 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_FILL))
422 so_data(so, 1);
423 else
424 so_data(so, 0);
425 if (cso->offset_cw || cso->offset_ccw) {
426 so_method(so, curie, NV40TCL_POLYGON_OFFSET_FACTOR, 2);
427 so_data (so, fui(cso->offset_scale));
428 so_data (so, fui(cso->offset_units * 2));
429 }
430
431 so_method(so, curie, NV40TCL_POINT_SPRITE, 1);
432 if (cso->point_quad_rasterization) {
433 unsigned psctl = (1 << 0), i;
434
435 for (i = 0; i < 8; i++) {
436 if ((cso->sprite_coord_enable >> i) & 1)
437 psctl |= (1 << (8 + i));
438 }
439
440 so_data(so, psctl);
441 } else {
442 so_data(so, 0);
443 }
444
445 so_ref(so, &rsso->so);
446 so_ref(NULL, &so);
447 rsso->pipe = *cso;
448 return (void *)rsso;
449 }
450
451 static void
452 nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
453 {
454 struct nv40_context *nv40 = nv40_context(pipe);
455
456 nv40->rasterizer = hwcso;
457 nv40->dirty |= NV40_NEW_RAST;
458 nv40->draw_dirty |= NV40_NEW_RAST;
459 }
460
461 static void
462 nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
463 {
464 struct nv40_rasterizer_state *rsso = hwcso;
465
466 so_ref(NULL, &rsso->so);
467 FREE(rsso);
468 }
469
470 static void *
471 nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe,
472 const struct pipe_depth_stencil_alpha_state *cso)
473 {
474 struct nv40_context *nv40 = nv40_context(pipe);
475 struct nv40_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
476 struct nouveau_stateobj *so = so_new(6, 20, 0);
477 struct nouveau_grobj *curie = nv40->screen->curie;
478
479 so_method(so, curie, NV40TCL_DEPTH_FUNC, 3);
480 so_data (so, nvgl_comparison_op(cso->depth.func));
481 so_data (so, cso->depth.writemask ? 1 : 0);
482 so_data (so, cso->depth.enabled ? 1 : 0);
483
484 so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
485 so_data (so, cso->alpha.enabled ? 1 : 0);
486 so_data (so, nvgl_comparison_op(cso->alpha.func));
487 so_data (so, float_to_ubyte(cso->alpha.ref_value));
488
489 if (cso->stencil[0].enabled) {
490 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 3);
491 so_data (so, cso->stencil[0].enabled ? 1 : 0);
492 so_data (so, cso->stencil[0].writemask);
493 so_data (so, nvgl_comparison_op(cso->stencil[0].func));
494 so_method(so, curie, NV40TCL_STENCIL_FRONT_FUNC_MASK, 4);
495 so_data (so, cso->stencil[0].valuemask);
496 so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op));
497 so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
498 so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
499 } else {
500 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 1);
501 so_data (so, 0);
502 }
503
504 if (cso->stencil[1].enabled) {
505 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 3);
506 so_data (so, cso->stencil[1].enabled ? 1 : 0);
507 so_data (so, cso->stencil[1].writemask);
508 so_data (so, nvgl_comparison_op(cso->stencil[1].func));
509 so_method(so, curie, NV40TCL_STENCIL_BACK_FUNC_MASK, 4);
510 so_data (so, cso->stencil[1].valuemask);
511 so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op));
512 so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
513 so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
514 } else {
515 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 1);
516 so_data (so, 0);
517 }
518
519 so_ref(so, &zsaso->so);
520 so_ref(NULL, &so);
521 zsaso->pipe = *cso;
522 return (void *)zsaso;
523 }
524
525 static void
526 nv40_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
527 {
528 struct nv40_context *nv40 = nv40_context(pipe);
529
530 nv40->zsa = hwcso;
531 nv40->dirty |= NV40_NEW_ZSA;
532 }
533
534 static void
535 nv40_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
536 {
537 struct nv40_zsa_state *zsaso = hwcso;
538
539 so_ref(NULL, &zsaso->so);
540 FREE(zsaso);
541 }
542
543 static void *
544 nv40_vp_state_create(struct pipe_context *pipe,
545 const struct pipe_shader_state *cso)
546 {
547 struct nv40_context *nv40 = nv40_context(pipe);
548 struct nv40_vertex_program *vp;
549
550 vp = CALLOC(1, sizeof(struct nv40_vertex_program));
551 vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
552 vp->draw = draw_create_vertex_shader(nv40->draw, &vp->pipe);
553
554 return (void *)vp;
555 }
556
557 static void
558 nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
559 {
560 struct nv40_context *nv40 = nv40_context(pipe);
561
562 nv40->vertprog = hwcso;
563 nv40->dirty |= NV40_NEW_VERTPROG;
564 nv40->draw_dirty |= NV40_NEW_VERTPROG;
565 }
566
567 static void
568 nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
569 {
570 struct nv40_context *nv40 = nv40_context(pipe);
571 struct nv40_vertex_program *vp = hwcso;
572
573 draw_delete_vertex_shader(nv40->draw, vp->draw);
574 nv40_vertprog_destroy(nv40, vp);
575 FREE((void*)vp->pipe.tokens);
576 FREE(vp);
577 }
578
579 static void *
580 nv40_fp_state_create(struct pipe_context *pipe,
581 const struct pipe_shader_state *cso)
582 {
583 struct nv40_fragment_program *fp;
584
585 fp = CALLOC(1, sizeof(struct nv40_fragment_program));
586 fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
587
588 tgsi_scan_shader(fp->pipe.tokens, &fp->info);
589
590 return (void *)fp;
591 }
592
593 static void
594 nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
595 {
596 struct nv40_context *nv40 = nv40_context(pipe);
597
598 nv40->fragprog = hwcso;
599 nv40->dirty |= NV40_NEW_FRAGPROG;
600 }
601
602 static void
603 nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
604 {
605 struct nv40_context *nv40 = nv40_context(pipe);
606 struct nv40_fragment_program *fp = hwcso;
607
608 nv40_fragprog_destroy(nv40, fp);
609 FREE((void*)fp->pipe.tokens);
610 FREE(fp);
611 }
612
613 static void
614 nv40_set_blend_color(struct pipe_context *pipe,
615 const struct pipe_blend_color *bcol)
616 {
617 struct nv40_context *nv40 = nv40_context(pipe);
618
619 nv40->blend_colour = *bcol;
620 nv40->dirty |= NV40_NEW_BCOL;
621 }
622
623 static void
624 nv40_set_stencil_ref(struct pipe_context *pipe,
625 const struct pipe_stencil_ref *sr)
626 {
627 struct nv40_context *nv40 = nv40_context(pipe);
628
629 nv40->stencil_ref = *sr;
630 nv40->dirty |= NV40_NEW_SR;
631 }
632
633 static void
634 nv40_set_clip_state(struct pipe_context *pipe,
635 const struct pipe_clip_state *clip)
636 {
637 struct nv40_context *nv40 = nv40_context(pipe);
638
639 nv40->clip = *clip;
640 nv40->dirty |= NV40_NEW_UCP;
641 nv40->draw_dirty |= NV40_NEW_UCP;
642 }
643
644 static void
645 nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
646 struct pipe_buffer *buf )
647 {
648 struct nv40_context *nv40 = nv40_context(pipe);
649
650 nv40->constbuf[shader] = buf;
651 nv40->constbuf_nr[shader] = buf->size / (4 * sizeof(float));
652
653 if (shader == PIPE_SHADER_VERTEX) {
654 nv40->dirty |= NV40_NEW_VERTPROG;
655 } else
656 if (shader == PIPE_SHADER_FRAGMENT) {
657 nv40->dirty |= NV40_NEW_FRAGPROG;
658 }
659 }
660
661 static void
662 nv40_set_framebuffer_state(struct pipe_context *pipe,
663 const struct pipe_framebuffer_state *fb)
664 {
665 struct nv40_context *nv40 = nv40_context(pipe);
666
667 nv40->framebuffer = *fb;
668 nv40->dirty |= NV40_NEW_FB;
669 }
670
671 static void
672 nv40_set_polygon_stipple(struct pipe_context *pipe,
673 const struct pipe_poly_stipple *stipple)
674 {
675 struct nv40_context *nv40 = nv40_context(pipe);
676
677 memcpy(nv40->stipple, stipple->stipple, 4 * 32);
678 nv40->dirty |= NV40_NEW_STIPPLE;
679 }
680
681 static void
682 nv40_set_scissor_state(struct pipe_context *pipe,
683 const struct pipe_scissor_state *s)
684 {
685 struct nv40_context *nv40 = nv40_context(pipe);
686
687 nv40->scissor = *s;
688 nv40->dirty |= NV40_NEW_SCISSOR;
689 }
690
691 static void
692 nv40_set_viewport_state(struct pipe_context *pipe,
693 const struct pipe_viewport_state *vpt)
694 {
695 struct nv40_context *nv40 = nv40_context(pipe);
696
697 nv40->viewport = *vpt;
698 nv40->dirty |= NV40_NEW_VIEWPORT;
699 nv40->draw_dirty |= NV40_NEW_VIEWPORT;
700 }
701
702 static void
703 nv40_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
704 const struct pipe_vertex_buffer *vb)
705 {
706 struct nv40_context *nv40 = nv40_context(pipe);
707
708 memcpy(nv40->vtxbuf, vb, sizeof(*vb) * count);
709 nv40->vtxbuf_nr = count;
710
711 nv40->dirty |= NV40_NEW_ARRAYS;
712 nv40->draw_dirty |= NV40_NEW_ARRAYS;
713 }
714
715 static void *
716 nv40_vtxelts_state_create(struct pipe_context *pipe,
717 unsigned num_elements,
718 const struct pipe_vertex_element *elements)
719 {
720 struct nv40_vtxelt_state *cso = CALLOC_STRUCT(nv40_vtxelt_state);
721
722 assert(num_elements < 16); /* not doing fallbacks yet */
723 cso->num_elements = num_elements;
724 memcpy(cso->pipe, elements, num_elements * sizeof(*elements));
725
726 /* nv40_vtxelt_construct(cso);*/
727
728 return (void *)cso;
729 }
730
731 static void
732 nv40_vtxelts_state_delete(struct pipe_context *pipe, void *hwcso)
733 {
734 FREE(hwcso);
735 }
736
737 static void
738 nv40_vtxelts_state_bind(struct pipe_context *pipe, void *hwcso)
739 {
740 struct nv40_context *nv40 = nv40_context(pipe);
741
742 nv40->vtxelt = hwcso;
743 nv40->dirty |= NV40_NEW_ARRAYS;
744 nv40->draw_dirty |= NV40_NEW_ARRAYS;
745 }
746
747 void
748 nv40_init_state_functions(struct nv40_context *nv40)
749 {
750 nv40->pipe.create_blend_state = nv40_blend_state_create;
751 nv40->pipe.bind_blend_state = nv40_blend_state_bind;
752 nv40->pipe.delete_blend_state = nv40_blend_state_delete;
753
754 nv40->pipe.create_sampler_state = nv40_sampler_state_create;
755 nv40->pipe.bind_fragment_sampler_states = nv40_sampler_state_bind;
756 nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
757 nv40->pipe.set_fragment_sampler_views = nv40_set_fragment_sampler_views;
758 nv40->pipe.create_sampler_view = nv40_create_sampler_view;
759 nv40->pipe.sampler_view_destroy = nv40_sampler_view_destroy;
760
761 nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
762 nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
763 nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
764
765 nv40->pipe.create_depth_stencil_alpha_state =
766 nv40_depth_stencil_alpha_state_create;
767 nv40->pipe.bind_depth_stencil_alpha_state =
768 nv40_depth_stencil_alpha_state_bind;
769 nv40->pipe.delete_depth_stencil_alpha_state =
770 nv40_depth_stencil_alpha_state_delete;
771
772 nv40->pipe.create_vs_state = nv40_vp_state_create;
773 nv40->pipe.bind_vs_state = nv40_vp_state_bind;
774 nv40->pipe.delete_vs_state = nv40_vp_state_delete;
775
776 nv40->pipe.create_fs_state = nv40_fp_state_create;
777 nv40->pipe.bind_fs_state = nv40_fp_state_bind;
778 nv40->pipe.delete_fs_state = nv40_fp_state_delete;
779
780 nv40->pipe.set_blend_color = nv40_set_blend_color;
781 nv40->pipe.set_stencil_ref = nv40_set_stencil_ref;
782 nv40->pipe.set_clip_state = nv40_set_clip_state;
783 nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
784 nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
785 nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
786 nv40->pipe.set_scissor_state = nv40_set_scissor_state;
787 nv40->pipe.set_viewport_state = nv40_set_viewport_state;
788
789 nv40->pipe.create_vertex_elements_state = nv40_vtxelts_state_create;
790 nv40->pipe.delete_vertex_elements_state = nv40_vtxelts_state_delete;
791 nv40->pipe.bind_vertex_elements_state = nv40_vtxelts_state_bind;
792
793 nv40->pipe.set_vertex_buffers = nv40_set_vertex_buffers;
794 }
795