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63d0ecc915875d0f43cac7c8377526ae550d7137
[mesa.git] / src / gallium / drivers / nv40 / nv40_state.c
1 #include "pipe/p_state.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_util.h"
4 #include "pipe/p_inlines.h"
5
6 #include "draw/draw_context.h"
7
8 #include "tgsi/tgsi_parse.h"
9
10 #include "nv40_context.h"
11 #include "nv40_state.h"
12
13 static void *
14 nv40_blend_state_create(struct pipe_context *pipe,
15 const struct pipe_blend_state *cso)
16 {
17 struct nv40_context *nv40 = nv40_context(pipe);
18 struct nouveau_grobj *curie = nv40->screen->curie;
19 struct nv40_blend_state *bso = CALLOC(1, sizeof(*bso));
20 struct nouveau_stateobj *so = so_new(16, 0);
21
22 if (cso->blend_enable) {
23 so_method(so, curie, NV40TCL_BLEND_ENABLE, 3);
24 so_data (so, 1);
25 so_data (so, (nvgl_blend_func(cso->alpha_src_factor) << 16) |
26 nvgl_blend_func(cso->rgb_src_factor));
27 so_data (so, nvgl_blend_func(cso->alpha_dst_factor) << 16 |
28 nvgl_blend_func(cso->rgb_dst_factor));
29 so_method(so, curie, NV40TCL_BLEND_EQUATION, 1);
30 so_data (so, nvgl_blend_eqn(cso->alpha_func) << 16 |
31 nvgl_blend_eqn(cso->rgb_func));
32 } else {
33 so_method(so, curie, NV40TCL_BLEND_ENABLE, 1);
34 so_data (so, 0);
35 }
36
37 so_method(so, curie, NV40TCL_COLOR_MASK, 1);
38 so_data (so, (((cso->colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
39 ((cso->colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
40 ((cso->colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) |
41 ((cso->colormask & PIPE_MASK_B) ? (0x01 << 0) : 0)));
42
43 if (cso->logicop_enable) {
44 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
45 so_data (so, 1);
46 so_data (so, nvgl_logicop_func(cso->logicop_func));
47 } else {
48 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
49 so_data (so, 0);
50 }
51
52 so_method(so, curie, NV40TCL_DITHER_ENABLE, 1);
53 so_data (so, cso->dither ? 1 : 0);
54
55 so_ref(so, &bso->so);
56 bso->pipe = *cso;
57 return (void *)bso;
58 }
59
60 static void
61 nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
62 {
63 struct nv40_context *nv40 = nv40_context(pipe);
64
65 nv40->blend = hwcso;
66 nv40->dirty |= NV40_NEW_BLEND;
67 }
68
69 static void
70 nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
71 {
72 struct nv40_blend_state *bso = hwcso;
73
74 so_ref(NULL, &bso->so);
75 FREE(bso);
76 }
77
78
79 static INLINE unsigned
80 wrap_mode(unsigned wrap) {
81 unsigned ret;
82
83 switch (wrap) {
84 case PIPE_TEX_WRAP_REPEAT:
85 ret = NV40TCL_TEX_WRAP_S_REPEAT;
86 break;
87 case PIPE_TEX_WRAP_MIRROR_REPEAT:
88 ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
89 break;
90 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
91 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
92 break;
93 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
94 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
95 break;
96 case PIPE_TEX_WRAP_CLAMP:
97 ret = NV40TCL_TEX_WRAP_S_CLAMP;
98 break;
99 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
100 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
101 break;
102 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
103 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
104 break;
105 case PIPE_TEX_WRAP_MIRROR_CLAMP:
106 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
107 break;
108 default:
109 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
110 ret = NV40TCL_TEX_WRAP_S_REPEAT;
111 break;
112 }
113
114 return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
115 }
116
117 static void *
118 nv40_sampler_state_create(struct pipe_context *pipe,
119 const struct pipe_sampler_state *cso)
120 {
121 struct nv40_sampler_state *ps;
122 uint32_t filter = 0;
123
124 ps = MALLOC(sizeof(struct nv40_sampler_state));
125
126 ps->fmt = 0;
127 if (!cso->normalized_coords)
128 ps->fmt |= NV40TCL_TEX_FORMAT_RECT;
129
130 ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) |
131 (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
132 (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT));
133
134 ps->en = 0;
135 if (cso->max_anisotropy >= 2.0) {
136 /* no idea, binary driver sets it, works without it.. meh.. */
137 ps->wrap |= (1 << 5);
138
139 if (cso->max_anisotropy >= 16.0) {
140 ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
141 } else
142 if (cso->max_anisotropy >= 12.0) {
143 ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
144 } else
145 if (cso->max_anisotropy >= 10.0) {
146 ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
147 } else
148 if (cso->max_anisotropy >= 8.0) {
149 ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
150 } else
151 if (cso->max_anisotropy >= 6.0) {
152 ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
153 } else
154 if (cso->max_anisotropy >= 4.0) {
155 ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
156 } else {
157 ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
158 }
159 }
160
161 switch (cso->mag_img_filter) {
162 case PIPE_TEX_FILTER_LINEAR:
163 filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
164 break;
165 case PIPE_TEX_FILTER_NEAREST:
166 default:
167 filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
168 break;
169 }
170
171 switch (cso->min_img_filter) {
172 case PIPE_TEX_FILTER_LINEAR:
173 switch (cso->min_mip_filter) {
174 case PIPE_TEX_MIPFILTER_NEAREST:
175 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
176 break;
177 case PIPE_TEX_MIPFILTER_LINEAR:
178 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
179 break;
180 case PIPE_TEX_MIPFILTER_NONE:
181 default:
182 filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
183 break;
184 }
185 break;
186 case PIPE_TEX_FILTER_NEAREST:
187 default:
188 switch (cso->min_mip_filter) {
189 case PIPE_TEX_MIPFILTER_NEAREST:
190 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
191 break;
192 case PIPE_TEX_MIPFILTER_LINEAR:
193 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
194 break;
195 case PIPE_TEX_MIPFILTER_NONE:
196 default:
197 filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
198 break;
199 }
200 break;
201 }
202
203 ps->filt = filter;
204
205 {
206 float limit;
207
208 limit = CLAMP(cso->lod_bias, -16.0, 15.0);
209 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
210
211 limit = CLAMP(cso->max_lod, 0.0, 15.0);
212 ps->en |= (int)(limit * 256.0) << 7;
213
214 limit = CLAMP(cso->min_lod, 0.0, 15.0);
215 ps->en |= (int)(limit * 256.0) << 19;
216 }
217
218
219 if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
220 switch (cso->compare_func) {
221 case PIPE_FUNC_NEVER:
222 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NEVER;
223 break;
224 case PIPE_FUNC_GREATER:
225 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GREATER;
226 break;
227 case PIPE_FUNC_EQUAL:
228 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_EQUAL;
229 break;
230 case PIPE_FUNC_GEQUAL:
231 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GEQUAL;
232 break;
233 case PIPE_FUNC_LESS:
234 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LESS;
235 break;
236 case PIPE_FUNC_NOTEQUAL:
237 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL;
238 break;
239 case PIPE_FUNC_LEQUAL:
240 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LEQUAL;
241 break;
242 case PIPE_FUNC_ALWAYS:
243 ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_ALWAYS;
244 break;
245 default:
246 break;
247 }
248 }
249
250 ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
251 (float_to_ubyte(cso->border_color[0]) << 16) |
252 (float_to_ubyte(cso->border_color[1]) << 8) |
253 (float_to_ubyte(cso->border_color[2]) << 0));
254
255 return (void *)ps;
256 }
257
258 static void
259 nv40_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
260 {
261 struct nv40_context *nv40 = nv40_context(pipe);
262 unsigned unit;
263
264 for (unit = 0; unit < nr; unit++) {
265 nv40->tex_sampler[unit] = sampler[unit];
266 nv40->dirty_samplers |= (1 << unit);
267 }
268
269 for (unit = nr; unit < nv40->nr_samplers; unit++) {
270 nv40->tex_sampler[unit] = NULL;
271 nv40->dirty_samplers |= (1 << unit);
272 }
273
274 nv40->nr_samplers = nr;
275 nv40->dirty |= NV40_NEW_SAMPLER;
276 }
277
278 static void
279 nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
280 {
281 FREE(hwcso);
282 }
283
284 static void
285 nv40_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
286 struct pipe_texture **miptree)
287 {
288 struct nv40_context *nv40 = nv40_context(pipe);
289 unsigned unit;
290
291 for (unit = 0; unit < nr; unit++) {
292 pipe_texture_reference((struct pipe_texture **)
293 &nv40->tex_miptree[unit], miptree[unit]);
294 nv40->dirty_samplers |= (1 << unit);
295 }
296
297 for (unit = nr; unit < nv40->nr_textures; unit++) {
298 pipe_texture_reference((struct pipe_texture **)
299 &nv40->tex_miptree[unit], NULL);
300 nv40->dirty_samplers |= (1 << unit);
301 }
302
303 nv40->nr_textures = nr;
304 nv40->dirty |= NV40_NEW_SAMPLER;
305 }
306
307 static void *
308 nv40_rasterizer_state_create(struct pipe_context *pipe,
309 const struct pipe_rasterizer_state *cso)
310 {
311 struct nv40_context *nv40 = nv40_context(pipe);
312 struct nv40_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
313 struct nouveau_stateobj *so = so_new(32, 0);
314 struct nouveau_grobj *curie = nv40->screen->curie;
315
316 /*XXX: ignored:
317 * light_twoside
318 * point_smooth -nohw
319 * multisample
320 */
321
322 so_method(so, curie, NV40TCL_SHADE_MODEL, 1);
323 so_data (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT :
324 NV40TCL_SHADE_MODEL_SMOOTH);
325
326 so_method(so, curie, NV40TCL_LINE_WIDTH, 2);
327 so_data (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
328 so_data (so, cso->line_smooth ? 1 : 0);
329 so_method(so, curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
330 so_data (so, cso->line_stipple_enable ? 1 : 0);
331 so_data (so, (cso->line_stipple_pattern << 16) |
332 cso->line_stipple_factor);
333
334 so_method(so, curie, NV40TCL_POINT_SIZE, 1);
335 so_data (so, fui(cso->point_size));
336
337 so_method(so, curie, NV40TCL_POLYGON_MODE_FRONT, 6);
338 if (cso->front_winding == PIPE_WINDING_CCW) {
339 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
340 so_data(so, nvgl_polygon_mode(cso->fill_cw));
341 switch (cso->cull_mode) {
342 case PIPE_WINDING_CCW:
343 so_data(so, NV40TCL_CULL_FACE_FRONT);
344 break;
345 case PIPE_WINDING_CW:
346 so_data(so, NV40TCL_CULL_FACE_BACK);
347 break;
348 case PIPE_WINDING_BOTH:
349 so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
350 break;
351 default:
352 so_data(so, NV40TCL_CULL_FACE_BACK);
353 break;
354 }
355 so_data(so, NV40TCL_FRONT_FACE_CCW);
356 } else {
357 so_data(so, nvgl_polygon_mode(cso->fill_cw));
358 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
359 switch (cso->cull_mode) {
360 case PIPE_WINDING_CCW:
361 so_data(so, NV40TCL_CULL_FACE_BACK);
362 break;
363 case PIPE_WINDING_CW:
364 so_data(so, NV40TCL_CULL_FACE_FRONT);
365 break;
366 case PIPE_WINDING_BOTH:
367 so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
368 break;
369 default:
370 so_data(so, NV40TCL_CULL_FACE_BACK);
371 break;
372 }
373 so_data(so, NV40TCL_FRONT_FACE_CW);
374 }
375 so_data(so, cso->poly_smooth ? 1 : 0);
376 so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
377
378 so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
379 so_data (so, cso->poly_stipple_enable ? 1 : 0);
380
381 so_method(so, curie, NV40TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
382 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
383 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
384 so_data(so, 1);
385 else
386 so_data(so, 0);
387 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_LINE) ||
388 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_LINE))
389 so_data(so, 1);
390 else
391 so_data(so, 0);
392 if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_FILL) ||
393 (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_FILL))
394 so_data(so, 1);
395 else
396 so_data(so, 0);
397 if (cso->offset_cw || cso->offset_ccw) {
398 so_method(so, curie, NV40TCL_POLYGON_OFFSET_FACTOR, 2);
399 so_data (so, fui(cso->offset_scale));
400 so_data (so, fui(cso->offset_units * 2));
401 }
402
403 so_method(so, curie, NV40TCL_POINT_SPRITE, 1);
404 if (cso->point_sprite) {
405 unsigned psctl = (1 << 0), i;
406
407 for (i = 0; i < 8; i++) {
408 if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
409 psctl |= (1 << (8 + i));
410 }
411
412 so_data(so, psctl);
413 } else {
414 so_data(so, 0);
415 }
416
417 so_ref(so, &rsso->so);
418 rsso->pipe = *cso;
419 return (void *)rsso;
420 }
421
422 static void
423 nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
424 {
425 struct nv40_context *nv40 = nv40_context(pipe);
426
427 nv40->rasterizer = hwcso;
428 nv40->dirty |= NV40_NEW_RAST;
429 nv40->draw_dirty |= NV40_NEW_RAST;
430 }
431
432 static void
433 nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
434 {
435 struct nv40_rasterizer_state *rsso = hwcso;
436
437 so_ref(NULL, &rsso->so);
438 FREE(rsso);
439 }
440
441 static void *
442 nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe,
443 const struct pipe_depth_stencil_alpha_state *cso)
444 {
445 struct nv40_context *nv40 = nv40_context(pipe);
446 struct nv40_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
447 struct nouveau_stateobj *so = so_new(32, 0);
448 struct nouveau_grobj *curie = nv40->screen->curie;
449
450 so_method(so, curie, NV40TCL_DEPTH_FUNC, 3);
451 so_data (so, nvgl_comparison_op(cso->depth.func));
452 so_data (so, cso->depth.writemask ? 1 : 0);
453 so_data (so, cso->depth.enabled ? 1 : 0);
454
455 so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
456 so_data (so, cso->alpha.enabled ? 1 : 0);
457 so_data (so, nvgl_comparison_op(cso->alpha.func));
458 so_data (so, float_to_ubyte(cso->alpha.ref));
459
460 if (cso->stencil[0].enabled) {
461 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 8);
462 so_data (so, cso->stencil[0].enabled ? 1 : 0);
463 so_data (so, cso->stencil[0].write_mask);
464 so_data (so, nvgl_comparison_op(cso->stencil[0].func));
465 so_data (so, cso->stencil[0].ref_value);
466 so_data (so, cso->stencil[0].value_mask);
467 so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op));
468 so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
469 so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
470 } else {
471 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 1);
472 so_data (so, 0);
473 }
474
475 if (cso->stencil[1].enabled) {
476 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 8);
477 so_data (so, cso->stencil[1].enabled ? 1 : 0);
478 so_data (so, cso->stencil[1].write_mask);
479 so_data (so, nvgl_comparison_op(cso->stencil[1].func));
480 so_data (so, cso->stencil[1].ref_value);
481 so_data (so, cso->stencil[1].value_mask);
482 so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op));
483 so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
484 so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
485 } else {
486 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 1);
487 so_data (so, 0);
488 }
489
490 so_ref(so, &zsaso->so);
491 zsaso->pipe = *cso;
492 return (void *)zsaso;
493 }
494
495 static void
496 nv40_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
497 {
498 struct nv40_context *nv40 = nv40_context(pipe);
499
500 nv40->zsa = hwcso;
501 nv40->dirty |= NV40_NEW_ZSA;
502 }
503
504 static void
505 nv40_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
506 {
507 struct nv40_zsa_state *zsaso = hwcso;
508
509 so_ref(NULL, &zsaso->so);
510 FREE(zsaso);
511 }
512
513 static void *
514 nv40_vp_state_create(struct pipe_context *pipe,
515 const struct pipe_shader_state *cso)
516 {
517 struct nv40_context *nv40 = nv40_context(pipe);
518 struct nv40_vertex_program *vp;
519
520 vp = CALLOC(1, sizeof(struct nv40_vertex_program));
521 vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
522 vp->draw = draw_create_vertex_shader(nv40->draw, &vp->pipe);
523
524 return (void *)vp;
525 }
526
527 static void
528 nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
529 {
530 struct nv40_context *nv40 = nv40_context(pipe);
531
532 nv40->vertprog = hwcso;
533 nv40->dirty |= NV40_NEW_VERTPROG;
534 nv40->draw_dirty |= NV40_NEW_VERTPROG;
535 }
536
537 static void
538 nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
539 {
540 struct nv40_context *nv40 = nv40_context(pipe);
541 struct nv40_vertex_program *vp = hwcso;
542
543 draw_delete_vertex_shader(nv40->draw, vp->draw);
544 nv40_vertprog_destroy(nv40, vp);
545 FREE((void*)vp->pipe.tokens);
546 FREE(vp);
547 }
548
549 static void *
550 nv40_fp_state_create(struct pipe_context *pipe,
551 const struct pipe_shader_state *cso)
552 {
553 struct nv40_fragment_program *fp;
554
555 fp = CALLOC(1, sizeof(struct nv40_fragment_program));
556 fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
557
558 tgsi_scan_shader(fp->pipe.tokens, &fp->info);
559
560 return (void *)fp;
561 }
562
563 static void
564 nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
565 {
566 struct nv40_context *nv40 = nv40_context(pipe);
567
568 nv40->fragprog = hwcso;
569 nv40->dirty |= NV40_NEW_FRAGPROG;
570 }
571
572 static void
573 nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
574 {
575 struct nv40_context *nv40 = nv40_context(pipe);
576 struct nv40_fragment_program *fp = hwcso;
577
578 nv40_fragprog_destroy(nv40, fp);
579 FREE((void*)fp->pipe.tokens);
580 FREE(fp);
581 }
582
583 static void
584 nv40_set_blend_color(struct pipe_context *pipe,
585 const struct pipe_blend_color *bcol)
586 {
587 struct nv40_context *nv40 = nv40_context(pipe);
588
589 nv40->blend_colour = *bcol;
590 nv40->dirty |= NV40_NEW_BCOL;
591 }
592
593 static void
594 nv40_set_clip_state(struct pipe_context *pipe,
595 const struct pipe_clip_state *clip)
596 {
597 struct nv40_context *nv40 = nv40_context(pipe);
598
599 nv40->clip = *clip;
600 nv40->dirty |= NV40_NEW_UCP;
601 nv40->draw_dirty |= NV40_NEW_UCP;
602 }
603
604 static void
605 nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
606 const struct pipe_constant_buffer *buf )
607 {
608 struct nv40_context *nv40 = nv40_context(pipe);
609
610 nv40->constbuf[shader] = buf->buffer;
611 nv40->constbuf_nr[shader] = buf->size / (4 * sizeof(float));
612
613 if (shader == PIPE_SHADER_VERTEX) {
614 nv40->dirty |= NV40_NEW_VERTPROG;
615 } else
616 if (shader == PIPE_SHADER_FRAGMENT) {
617 nv40->dirty |= NV40_NEW_FRAGPROG;
618 }
619 }
620
621 static void
622 nv40_set_framebuffer_state(struct pipe_context *pipe,
623 const struct pipe_framebuffer_state *fb)
624 {
625 struct nv40_context *nv40 = nv40_context(pipe);
626
627 nv40->framebuffer = *fb;
628 nv40->dirty |= NV40_NEW_FB;
629 }
630
631 static void
632 nv40_set_polygon_stipple(struct pipe_context *pipe,
633 const struct pipe_poly_stipple *stipple)
634 {
635 struct nv40_context *nv40 = nv40_context(pipe);
636
637 memcpy(nv40->stipple, stipple->stipple, 4 * 32);
638 nv40->dirty |= NV40_NEW_STIPPLE;
639 }
640
641 static void
642 nv40_set_scissor_state(struct pipe_context *pipe,
643 const struct pipe_scissor_state *s)
644 {
645 struct nv40_context *nv40 = nv40_context(pipe);
646
647 nv40->scissor = *s;
648 nv40->dirty |= NV40_NEW_SCISSOR;
649 }
650
651 static void
652 nv40_set_viewport_state(struct pipe_context *pipe,
653 const struct pipe_viewport_state *vpt)
654 {
655 struct nv40_context *nv40 = nv40_context(pipe);
656
657 nv40->viewport = *vpt;
658 nv40->dirty |= NV40_NEW_VIEWPORT;
659 nv40->draw_dirty |= NV40_NEW_VIEWPORT;
660 }
661
662 static void
663 nv40_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
664 const struct pipe_vertex_buffer *vb)
665 {
666 struct nv40_context *nv40 = nv40_context(pipe);
667
668 memcpy(nv40->vtxbuf, vb, sizeof(*vb) * count);
669 nv40->vtxbuf_nr = count;
670
671 nv40->dirty |= NV40_NEW_ARRAYS;
672 nv40->draw_dirty |= NV40_NEW_ARRAYS;
673 }
674
675 static void
676 nv40_set_vertex_elements(struct pipe_context *pipe, unsigned count,
677 const struct pipe_vertex_element *ve)
678 {
679 struct nv40_context *nv40 = nv40_context(pipe);
680
681 memcpy(nv40->vtxelt, ve, sizeof(*ve) * count);
682 nv40->vtxelt_nr = count;
683
684 nv40->dirty |= NV40_NEW_ARRAYS;
685 nv40->draw_dirty |= NV40_NEW_ARRAYS;
686 }
687
688 static void
689 nv40_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield)
690 {
691 struct nv40_context *nv40 = nv40_context(pipe);
692
693 nv40->edgeflags = bitfield;
694 nv40->dirty |= NV40_NEW_ARRAYS;
695 nv40->draw_dirty |= NV40_NEW_ARRAYS;
696 }
697
698 void
699 nv40_init_state_functions(struct nv40_context *nv40)
700 {
701 nv40->pipe.create_blend_state = nv40_blend_state_create;
702 nv40->pipe.bind_blend_state = nv40_blend_state_bind;
703 nv40->pipe.delete_blend_state = nv40_blend_state_delete;
704
705 nv40->pipe.create_sampler_state = nv40_sampler_state_create;
706 nv40->pipe.bind_sampler_states = nv40_sampler_state_bind;
707 nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
708 nv40->pipe.set_sampler_textures = nv40_set_sampler_texture;
709
710 nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
711 nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
712 nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
713
714 nv40->pipe.create_depth_stencil_alpha_state =
715 nv40_depth_stencil_alpha_state_create;
716 nv40->pipe.bind_depth_stencil_alpha_state =
717 nv40_depth_stencil_alpha_state_bind;
718 nv40->pipe.delete_depth_stencil_alpha_state =
719 nv40_depth_stencil_alpha_state_delete;
720
721 nv40->pipe.create_vs_state = nv40_vp_state_create;
722 nv40->pipe.bind_vs_state = nv40_vp_state_bind;
723 nv40->pipe.delete_vs_state = nv40_vp_state_delete;
724
725 nv40->pipe.create_fs_state = nv40_fp_state_create;
726 nv40->pipe.bind_fs_state = nv40_fp_state_bind;
727 nv40->pipe.delete_fs_state = nv40_fp_state_delete;
728
729 nv40->pipe.set_blend_color = nv40_set_blend_color;
730 nv40->pipe.set_clip_state = nv40_set_clip_state;
731 nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
732 nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
733 nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
734 nv40->pipe.set_scissor_state = nv40_set_scissor_state;
735 nv40->pipe.set_viewport_state = nv40_set_viewport_state;
736
737 nv40->pipe.set_edgeflags = nv40_set_edgeflags;
738 nv40->pipe.set_vertex_buffers = nv40_set_vertex_buffers;
739 nv40->pipe.set_vertex_elements = nv40_set_vertex_elements;
740 }
741