src/gallium/drivers/nv40/nv40_state.c

   1 #include "pipe/p_state.h"
   2 #include "pipe/p_defines.h"
   3 #include "pipe/p_util.h"
   4 #include "pipe/p_inlines.h"
   5
   6 #include "draw/draw_context.h"
   7
   8 #include "nv40_context.h"
   9 #include "nv40_state.h"
  10
  11 static void *
  12 nv40_blend_state_create(struct pipe_context *pipe,
  13                         const struct pipe_blend_state *cso)
  14 {
  15         struct nv40_context *nv40 = nv40_context(pipe);
  16         struct nouveau_grobj *curie = nv40->screen->curie;
  17         struct nv40_blend_state *bso = CALLOC(1, sizeof(*bso));
  18         struct nouveau_stateobj *so = so_new(16, 0);
  19
  20         if (cso->blend_enable) {
  21                 so_method(so, curie, NV40TCL_BLEND_ENABLE, 3);
  22                 so_data  (so, 1);
  23                 so_data  (so, (nvgl_blend_func(cso->alpha_src_factor) << 16) |
  24                                nvgl_blend_func(cso->rgb_src_factor));
  25                 so_data  (so, nvgl_blend_func(cso->alpha_dst_factor) << 16 |
  26                               nvgl_blend_func(cso->rgb_dst_factor));
  27                 so_method(so, curie, NV40TCL_BLEND_EQUATION, 1);
  28                 so_data  (so, nvgl_blend_eqn(cso->alpha_func) << 16 |
  29                               nvgl_blend_eqn(cso->rgb_func));
  30         } else {
  31                 so_method(so, curie, NV40TCL_BLEND_ENABLE, 1);
  32                 so_data  (so, 0);
  33         }
  34
  35         so_method(so, curie, NV40TCL_COLOR_MASK, 1);
  36         so_data  (so, (((cso->colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
  37                        ((cso->colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
  38                        ((cso->colormask & PIPE_MASK_G) ? (0x01 <<  8) : 0) |
  39                        ((cso->colormask & PIPE_MASK_B) ? (0x01 <<  0) : 0)));
  40
  41         if (cso->logicop_enable) {
  42                 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
  43                 so_data  (so, 1);
  44                 so_data  (so, nvgl_logicop_func(cso->logicop_func));
  45         } else {
  46                 so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
  47                 so_data  (so, 0);
  48         }
  49
  50         so_method(so, curie, NV40TCL_DITHER_ENABLE, 1);
  51         so_data  (so, cso->dither ? 1 : 0);
  52
  53         so_ref(so, &bso->so);
  54         bso->pipe = *cso;
  55         return (void *)bso;
  56 }
  57
  58 static void
  59 nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
  60 {
  61         struct nv40_context *nv40 = nv40_context(pipe);
  62
  63         nv40->blend = hwcso;
  64         nv40->dirty |= NV40_NEW_BLEND;
  65 }
  66
  67 static void
  68 nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
  69 {
  70         struct nv40_blend_state *bso = hwcso;
  71
  72         so_ref(NULL, &bso->so);
  73         FREE(bso);
  74 }
  75
  76
  77 static INLINE unsigned
  78 wrap_mode(unsigned wrap) {
  79         unsigned ret;
  80
  81         switch (wrap) {
  82         case PIPE_TEX_WRAP_REPEAT:
  83                 ret = NV40TCL_TEX_WRAP_S_REPEAT;
  84                 break;
  85         case PIPE_TEX_WRAP_MIRROR_REPEAT:
  86                 ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
  87                 break;
  88         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
  89                 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
  90                 break;
  91         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
  92                 ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
  93                 break;
  94         case PIPE_TEX_WRAP_CLAMP:
  95                 ret = NV40TCL_TEX_WRAP_S_CLAMP;
  96                 break;
  97         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
  98                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
  99                 break;
 100         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 101                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
 102                 break;
 103         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 104                 ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
 105                 break;
 106         default:
 107                 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
 108                 ret = NV40TCL_TEX_WRAP_S_REPEAT;
 109                 break;
 110         }
 111
 112         return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
 113 }
 114
 115 static void *
 116 nv40_sampler_state_create(struct pipe_context *pipe,
 117                           const struct pipe_sampler_state *cso)
 118 {
 119         struct nv40_sampler_state *ps;
 120         uint32_t filter = 0;
 121
 122         ps = MALLOC(sizeof(struct nv40_sampler_state));
 123
 124         ps->fmt = 0;
 125         if (!cso->normalized_coords)
 126                 ps->fmt |= NV40TCL_TEX_FORMAT_RECT;
 127
 128         ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) |
 129                     (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
 130                     (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT));
 131
 132         ps->en = 0;
 133         if (cso->max_anisotropy >= 2.0) {
 134                 /* no idea, binary driver sets it, works without it.. meh.. */
 135                 ps->wrap |= (1 << 5);
 136
 137                 if (cso->max_anisotropy >= 16.0) {
 138                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
 139                 } else
 140                 if (cso->max_anisotropy >= 12.0) {
 141                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
 142                 } else
 143                 if (cso->max_anisotropy >= 10.0) {
 144                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
 145                 } else
 146                 if (cso->max_anisotropy >= 8.0) {
 147                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
 148                 } else
 149                 if (cso->max_anisotropy >= 6.0) {
 150                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
 151                 } else
 152                 if (cso->max_anisotropy >= 4.0) {
 153                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
 154                 } else {
 155                         ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
 156                 }
 157         }
 158
 159         switch (cso->mag_img_filter) {
 160         case PIPE_TEX_FILTER_LINEAR:
 161                 filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
 162                 break;
 163         case PIPE_TEX_FILTER_NEAREST:
 164         default:
 165                 filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
 166                 break;
 167         }
 168
 169         switch (cso->min_img_filter) {
 170         case PIPE_TEX_FILTER_LINEAR:
 171                 switch (cso->min_mip_filter) {
 172                 case PIPE_TEX_MIPFILTER_NEAREST:
 173                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
 174                         break;
 175                 case PIPE_TEX_MIPFILTER_LINEAR:
 176                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
 177                         break;
 178                 case PIPE_TEX_MIPFILTER_NONE:
 179                 default:
 180                         filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
 181                         break;
 182                 }
 183                 break;
 184         case PIPE_TEX_FILTER_NEAREST:
 185         default:
 186                 switch (cso->min_mip_filter) {
 187                 case PIPE_TEX_MIPFILTER_NEAREST:
 188                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
 189                 break;
 190                 case PIPE_TEX_MIPFILTER_LINEAR:
 191                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
 192                         break;
 193                 case PIPE_TEX_MIPFILTER_NONE:
 194                 default:
 195                         filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
 196                         break;
 197                 }
 198                 break;
 199         }
 200
 201         ps->filt = filter;
 202
 203         {
 204                 float limit;
 205
 206                 limit = CLAMP(cso->lod_bias, -16.0, 15.0);
 207                 ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 208
 209                 limit = CLAMP(cso->max_lod, 0.0, 15.0);
 210                 ps->en |= (int)(limit * 256.0) << 7;
 211
 212                 limit = CLAMP(cso->min_lod, 0.0, 15.0);
 213                 ps->en |= (int)(limit * 256.0) << 19;
 214         }
 215
 216
 217         if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
 218                 switch (cso->compare_func) {
 219                 case PIPE_FUNC_NEVER:
 220                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NEVER;
 221                         break;
 222                 case PIPE_FUNC_GREATER:
 223                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GREATER;
 224                         break;
 225                 case PIPE_FUNC_EQUAL:
 226                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_EQUAL;
 227                         break;
 228                 case PIPE_FUNC_GEQUAL:
 229                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GEQUAL;
 230                         break;
 231                 case PIPE_FUNC_LESS:
 232                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LESS;
 233                         break;
 234                 case PIPE_FUNC_NOTEQUAL:
 235                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL;
 236                         break;
 237                 case PIPE_FUNC_LEQUAL:
 238                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LEQUAL;
 239                         break;
 240                 case PIPE_FUNC_ALWAYS:
 241                         ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_ALWAYS;
 242                         break;
 243                 default:
 244                         break;
 245                 }
 246         }
 247
 248         ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
 249                     (float_to_ubyte(cso->border_color[0]) << 16) |
 250                     (float_to_ubyte(cso->border_color[1]) <<  8) |
 251                     (float_to_ubyte(cso->border_color[2]) <<  0));
 252
 253         return (void *)ps;
 254 }
 255
 256 static void
 257 nv40_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
 258 {
 259         struct nv40_context *nv40 = nv40_context(pipe);
 260         unsigned unit;
 261
 262         for (unit = 0; unit < nr; unit++) {
 263                 nv40->tex_sampler[unit] = sampler[unit];
 264                 nv40->dirty_samplers |= (1 << unit);
 265         }
 266
 267         for (unit = nr; unit < nv40->nr_samplers; unit++) {
 268                 nv40->tex_sampler[unit] = NULL;
 269                 nv40->dirty_samplers |= (1 << unit);
 270         }
 271
 272         nv40->nr_samplers = nr;
 273         nv40->dirty |= NV40_NEW_SAMPLER;
 274 }
 275
 276 static void
 277 nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
 278 {
 279         FREE(hwcso);
 280 }
 281
 282 static void
 283 nv40_set_sampler_texture(struct pipe_context *pipe, unsigned nr,
 284                          struct pipe_texture **miptree)
 285 {
 286         struct nv40_context *nv40 = nv40_context(pipe);
 287         unsigned unit;
 288
 289         for (unit = 0; unit < nr; unit++) {
 290                 pipe_texture_reference((struct pipe_texture **)
 291                                        &nv40->tex_miptree[unit], miptree[unit]);
 292                 nv40->dirty_samplers |= (1 << unit);
 293         }
 294
 295         for (unit = nr; unit < nv40->nr_textures; unit++) {
 296                 pipe_texture_reference((struct pipe_texture **)
 297                                        &nv40->tex_miptree[unit], NULL);
 298                 nv40->dirty_samplers |= (1 << unit);
 299         }
 300
 301         nv40->nr_textures = nr;
 302         nv40->dirty |= NV40_NEW_SAMPLER;
 303 }
 304
 305 static void *
 306 nv40_rasterizer_state_create(struct pipe_context *pipe,
 307                              const struct pipe_rasterizer_state *cso)
 308 {
 309         struct nv40_context *nv40 = nv40_context(pipe);
 310         struct nv40_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
 311         struct nouveau_stateobj *so = so_new(32, 0);
 312         struct nouveau_grobj *curie = nv40->screen->curie;
 313
 314         /*XXX: ignored:
 315          *      light_twoside
 316          *      point_smooth -nohw
 317          *      multisample
 318          */
 319
 320         so_method(so, curie, NV40TCL_SHADE_MODEL, 1);
 321         so_data  (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT :
 322                                        NV40TCL_SHADE_MODEL_SMOOTH);
 323
 324         so_method(so, curie, NV40TCL_LINE_WIDTH, 2);
 325         so_data  (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
 326         so_data  (so, cso->line_smooth ? 1 : 0);
 327         so_method(so, curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
 328         so_data  (so, cso->line_stipple_enable ? 1 : 0);
 329         so_data  (so, (cso->line_stipple_pattern << 16) |
 330                        cso->line_stipple_factor);
 331
 332         so_method(so, curie, NV40TCL_POINT_SIZE, 1);
 333         so_data  (so, fui(cso->point_size));
 334
 335         so_method(so, curie, NV40TCL_POLYGON_MODE_FRONT, 6);
 336         if (cso->front_winding == PIPE_WINDING_CCW) {
 337                 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 338                 so_data(so, nvgl_polygon_mode(cso->fill_cw));
 339                 switch (cso->cull_mode) {
 340                 case PIPE_WINDING_CCW:
 341                         so_data(so, NV40TCL_CULL_FACE_FRONT);
 342                         break;
 343                 case PIPE_WINDING_CW:
 344                         so_data(so, NV40TCL_CULL_FACE_BACK);
 345                         break;
 346                 case PIPE_WINDING_BOTH:
 347                         so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
 348                         break;
 349                 default:
 350                         so_data(so, NV40TCL_CULL_FACE_BACK);
 351                         break;
 352                 }
 353                 so_data(so, NV40TCL_FRONT_FACE_CCW);
 354         } else {
 355                 so_data(so, nvgl_polygon_mode(cso->fill_cw));
 356                 so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 357                 switch (cso->cull_mode) {
 358                 case PIPE_WINDING_CCW:
 359                         so_data(so, NV40TCL_CULL_FACE_BACK);
 360                         break;
 361                 case PIPE_WINDING_CW:
 362                         so_data(so, NV40TCL_CULL_FACE_FRONT);
 363                         break;
 364                 case PIPE_WINDING_BOTH:
 365                         so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK);
 366                         break;
 367                 default:
 368                         so_data(so, NV40TCL_CULL_FACE_BACK);
 369                         break;
 370                 }
 371                 so_data(so, NV40TCL_FRONT_FACE_CW);
 372         }
 373         so_data(so, cso->poly_smooth ? 1 : 0);
 374         so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
 375
 376         so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
 377         so_data  (so, cso->poly_stipple_enable ? 1 : 0);
 378
 379         so_method(so, curie, NV40TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
 380         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
 381             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
 382                 so_data(so, 1);
 383         else
 384                 so_data(so, 0);
 385         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_LINE) ||
 386             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_LINE))
 387                 so_data(so, 1);
 388         else
 389                 so_data(so, 0);
 390         if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_FILL) ||
 391             (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_FILL))
 392                 so_data(so, 1);
 393         else
 394                 so_data(so, 0);
 395         if (cso->offset_cw || cso->offset_ccw) {
 396                 so_method(so, curie, NV40TCL_POLYGON_OFFSET_FACTOR, 2);
 397                 so_data  (so, fui(cso->offset_scale));
 398                 so_data  (so, fui(cso->offset_units * 2));
 399         }
 400
 401         so_method(so, curie, NV40TCL_POINT_SPRITE, 1);
 402         if (cso->point_sprite) {
 403                 unsigned psctl = (1 << 0), i;
 404
 405                 for (i = 0; i < 8; i++) {
 406                         if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE)
 407                                 psctl |= (1 << (8 + i));
 408                 }
 409
 410                 so_data(so, psctl);
 411         } else {
 412                 so_data(so, 0);
 413         }
 414
 415         so_ref(so, &rsso->so);
 416         rsso->pipe = *cso;
 417         return (void *)rsso;
 418 }
 419
 420 static void
 421 nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 422 {
 423         struct nv40_context *nv40 = nv40_context(pipe);
 424
 425         nv40->rasterizer = hwcso;
 426         nv40->dirty |= NV40_NEW_RAST;
 427         nv40->draw_dirty |= NV40_NEW_RAST;
 428 }
 429
 430 static void
 431 nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
 432 {
 433         struct nv40_rasterizer_state *rsso = hwcso;
 434
 435         so_ref(NULL, &rsso->so);
 436         FREE(rsso);
 437 }
 438
 439 static void *
 440 nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 441                         const struct pipe_depth_stencil_alpha_state *cso)
 442 {
 443         struct nv40_context *nv40 = nv40_context(pipe);
 444         struct nv40_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
 445         struct nouveau_stateobj *so = so_new(32, 0);
 446         struct nouveau_grobj *curie = nv40->screen->curie;
 447
 448         so_method(so, curie, NV40TCL_DEPTH_FUNC, 3);
 449         so_data  (so, nvgl_comparison_op(cso->depth.func));
 450         so_data  (so, cso->depth.writemask ? 1 : 0);
 451         so_data  (so, cso->depth.enabled ? 1 : 0);
 452
 453         so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
 454         so_data  (so, cso->alpha.enabled ? 1 : 0);
 455         so_data  (so, nvgl_comparison_op(cso->alpha.func));
 456         so_data  (so, float_to_ubyte(cso->alpha.ref));
 457
 458         if (cso->stencil[0].enabled) {
 459                 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 8);
 460                 so_data  (so, cso->stencil[0].enabled ? 1 : 0);
 461                 so_data  (so, cso->stencil[0].write_mask);
 462                 so_data  (so, nvgl_comparison_op(cso->stencil[0].func));
 463                 so_data  (so, cso->stencil[0].ref_value);
 464                 so_data  (so, cso->stencil[0].value_mask);
 465                 so_data  (so, nvgl_stencil_op(cso->stencil[0].fail_op));
 466                 so_data  (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
 467                 so_data  (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
 468         } else {
 469                 so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 1);
 470                 so_data  (so, 0);
 471         }
 472
 473         if (cso->stencil[1].enabled) {
 474                 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 8);
 475                 so_data  (so, cso->stencil[1].enabled ? 1 : 0);
 476                 so_data  (so, cso->stencil[1].write_mask);
 477                 so_data  (so, nvgl_comparison_op(cso->stencil[1].func));
 478                 so_data  (so, cso->stencil[1].ref_value);
 479                 so_data  (so, cso->stencil[1].value_mask);
 480                 so_data  (so, nvgl_stencil_op(cso->stencil[1].fail_op));
 481                 so_data  (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
 482                 so_data  (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
 483         } else {
 484                 so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 1);
 485                 so_data  (so, 0);
 486         }
 487
 488         so_ref(so, &zsaso->so);
 489         zsaso->pipe = *cso;
 490         return (void *)zsaso;
 491 }
 492
 493 static void
 494 nv40_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso)
 495 {
 496         struct nv40_context *nv40 = nv40_context(pipe);
 497
 498         nv40->zsa = hwcso;
 499         nv40->dirty |= NV40_NEW_ZSA;
 500 }
 501
 502 static void
 503 nv40_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
 504 {
 505         struct nv40_zsa_state *zsaso = hwcso;
 506
 507         so_ref(NULL, &zsaso->so);
 508         FREE(zsaso);
 509 }
 510
 511 static void *
 512 nv40_vp_state_create(struct pipe_context *pipe,
 513                      const struct pipe_shader_state *cso)
 514 {
 515         struct nv40_context *nv40 = nv40_context(pipe);
 516         struct nv40_vertex_program *vp;
 517
 518         vp = CALLOC(1, sizeof(struct nv40_vertex_program));
 519         vp->pipe = *cso;
 520         vp->draw = draw_create_vertex_shader(nv40->draw, &vp->pipe);
 521
 522         return (void *)vp;
 523 }
 524
 525 static void
 526 nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
 527 {
 528         struct nv40_context *nv40 = nv40_context(pipe);
 529
 530         nv40->vertprog = hwcso;
 531         nv40->dirty |= NV40_NEW_VERTPROG;
 532         nv40->draw_dirty |= NV40_NEW_VERTPROG;
 533 }
 534
 535 static void
 536 nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
 537 {
 538         struct nv40_context *nv40 = nv40_context(pipe);
 539         struct nv40_vertex_program *vp = hwcso;
 540
 541         draw_delete_vertex_shader(nv40->draw, vp->draw);
 542         nv40_vertprog_destroy(nv40, vp);
 543         FREE(vp);
 544 }
 545
 546 static void *
 547 nv40_fp_state_create(struct pipe_context *pipe,
 548                      const struct pipe_shader_state *cso)
 549 {
 550         struct nv40_fragment_program *fp;
 551
 552         fp = CALLOC(1, sizeof(struct nv40_fragment_program));
 553         fp->pipe = *cso;
 554
 555         tgsi_scan_shader(fp->pipe.tokens, &fp->info);
 556
 557         return (void *)fp;
 558 }
 559
 560 static void
 561 nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
 562 {
 563         struct nv40_context *nv40 = nv40_context(pipe);
 564
 565         nv40->fragprog = hwcso;
 566         nv40->dirty |= NV40_NEW_FRAGPROG;
 567 }
 568
 569 static void
 570 nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
 571 {
 572         struct nv40_context *nv40 = nv40_context(pipe);
 573         struct nv40_fragment_program *fp = hwcso;
 574
 575         nv40_fragprog_destroy(nv40, fp);
 576         FREE(fp);
 577 }
 578
 579 static void
 580 nv40_set_blend_color(struct pipe_context *pipe,
 581                      const struct pipe_blend_color *bcol)
 582 {
 583         struct nv40_context *nv40 = nv40_context(pipe);
 584
 585         nv40->blend_colour = *bcol;
 586         nv40->dirty |= NV40_NEW_BCOL;
 587 }
 588
 589 static void
 590 nv40_set_clip_state(struct pipe_context *pipe,
 591                     const struct pipe_clip_state *clip)
 592 {
 593         struct nv40_context *nv40 = nv40_context(pipe);
 594
 595         nv40->clip = *clip;
 596         nv40->dirty |= NV40_NEW_UCP;
 597         nv40->draw_dirty |= NV40_NEW_UCP;
 598 }
 599
 600 static void
 601 nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
 602                          const struct pipe_constant_buffer *buf )
 603 {
 604         struct nv40_context *nv40 = nv40_context(pipe);
 605
 606         nv40->constbuf[shader] = buf->buffer;
 607         nv40->constbuf_nr[shader] = buf->size / (4 * sizeof(float));
 608
 609         if (shader == PIPE_SHADER_VERTEX) {
 610                 nv40->dirty |= NV40_NEW_VERTPROG;
 611         } else
 612         if (shader == PIPE_SHADER_FRAGMENT) {
 613                 nv40->dirty |= NV40_NEW_FRAGPROG;
 614         }
 615 }
 616
 617 static void
 618 nv40_set_framebuffer_state(struct pipe_context *pipe,
 619                            const struct pipe_framebuffer_state *fb)
 620 {
 621         struct nv40_context *nv40 = nv40_context(pipe);
 622
 623         nv40->framebuffer = *fb;
 624         nv40->dirty |= NV40_NEW_FB;
 625 }
 626
 627 static void
 628 nv40_set_polygon_stipple(struct pipe_context *pipe,
 629                          const struct pipe_poly_stipple *stipple)
 630 {
 631         struct nv40_context *nv40 = nv40_context(pipe);
 632
 633         memcpy(nv40->stipple, stipple->stipple, 4 * 32);
 634         nv40->dirty |= NV40_NEW_STIPPLE;
 635 }
 636
 637 static void
 638 nv40_set_scissor_state(struct pipe_context *pipe,
 639                        const struct pipe_scissor_state *s)
 640 {
 641         struct nv40_context *nv40 = nv40_context(pipe);
 642
 643         nv40->scissor = *s;
 644         nv40->dirty |= NV40_NEW_SCISSOR;
 645 }
 646
 647 static void
 648 nv40_set_viewport_state(struct pipe_context *pipe,
 649                         const struct pipe_viewport_state *vpt)
 650 {
 651         struct nv40_context *nv40 = nv40_context(pipe);
 652
 653         nv40->viewport = *vpt;
 654         nv40->dirty |= NV40_NEW_VIEWPORT;
 655         nv40->draw_dirty |= NV40_NEW_VIEWPORT;
 656 }
 657
 658 static void
 659 nv40_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
 660                         const struct pipe_vertex_buffer *vb)
 661 {
 662         struct nv40_context *nv40 = nv40_context(pipe);
 663
 664         memcpy(nv40->vtxbuf, vb, sizeof(*vb) * count);
 665         nv40->vtxbuf_nr = count;
 666
 667         nv40->dirty |= NV40_NEW_ARRAYS;
 668         nv40->draw_dirty |= NV40_NEW_ARRAYS;
 669 }
 670
 671 static void
 672 nv40_set_vertex_elements(struct pipe_context *pipe, unsigned count,
 673                          const struct pipe_vertex_element *ve)
 674 {
 675         struct nv40_context *nv40 = nv40_context(pipe);
 676
 677         memcpy(nv40->vtxelt, ve, sizeof(*ve) * count);
 678         nv40->vtxelt_nr = count;
 679
 680         nv40->dirty |= NV40_NEW_ARRAYS;
 681         nv40->draw_dirty |= NV40_NEW_ARRAYS;
 682 }
 683
 684 static void
 685 nv40_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield)
 686 {
 687         struct nv40_context *nv40 = nv40_context(pipe);
 688
 689         nv40->edgeflags = bitfield;
 690         nv40->dirty |= NV40_NEW_ARRAYS;
 691         nv40->draw_dirty |= NV40_NEW_ARRAYS;
 692 }
 693
 694 void
 695 nv40_init_state_functions(struct nv40_context *nv40)
 696 {
 697         nv40->pipe.create_blend_state = nv40_blend_state_create;
 698         nv40->pipe.bind_blend_state = nv40_blend_state_bind;
 699         nv40->pipe.delete_blend_state = nv40_blend_state_delete;
 700
 701         nv40->pipe.create_sampler_state = nv40_sampler_state_create;
 702         nv40->pipe.bind_sampler_states = nv40_sampler_state_bind;
 703         nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
 704         nv40->pipe.set_sampler_textures = nv40_set_sampler_texture;
 705
 706         nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
 707         nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
 708         nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
 709
 710         nv40->pipe.create_depth_stencil_alpha_state =
 711                 nv40_depth_stencil_alpha_state_create;
 712         nv40->pipe.bind_depth_stencil_alpha_state =
 713                 nv40_depth_stencil_alpha_state_bind;
 714         nv40->pipe.delete_depth_stencil_alpha_state =
 715                 nv40_depth_stencil_alpha_state_delete;
 716
 717         nv40->pipe.create_vs_state = nv40_vp_state_create;
 718         nv40->pipe.bind_vs_state = nv40_vp_state_bind;
 719         nv40->pipe.delete_vs_state = nv40_vp_state_delete;
 720
 721         nv40->pipe.create_fs_state = nv40_fp_state_create;
 722         nv40->pipe.bind_fs_state = nv40_fp_state_bind;
 723         nv40->pipe.delete_fs_state = nv40_fp_state_delete;
 724
 725         nv40->pipe.set_blend_color = nv40_set_blend_color;
 726         nv40->pipe.set_clip_state = nv40_set_clip_state;
 727         nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
 728         nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
 729         nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
 730         nv40->pipe.set_scissor_state = nv40_set_scissor_state;
 731         nv40->pipe.set_viewport_state = nv40_set_viewport_state;
 732
 733         nv40->pipe.set_edgeflags = nv40_set_edgeflags;
 734         nv40->pipe.set_vertex_buffers = nv40_set_vertex_buffers;
 735         nv40->pipe.set_vertex_elements = nv40_set_vertex_elements;
 736 }
 737