src/gallium/drivers/nv40/nv40_state_fb.c

   1 #include "nv40_context.h"
   2
   3 static boolean
   4 nv40_state_framebuffer_validate(struct nv40_context *nv40)
   5 {
   6         struct pipe_framebuffer_state *fb = &nv40->framebuffer;
   7         struct pipe_surface *rt[4], *zeta;
   8         uint32_t rt_enable, rt_format;
   9         int i, colour_format = 0, zeta_format = 0;
  10         struct nouveau_stateobj *so = so_new(64, 10);
  11         unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
  12         unsigned w = fb->width;
  13         unsigned h = fb->height;
  14
  15         rt_enable = 0;
  16         for (i = 0; i < fb->num_cbufs; i++) {
  17                 if (colour_format) {
  18                         assert(colour_format == fb->cbufs[i]->format);
  19                 } else {
  20                         colour_format = fb->cbufs[i]->format;
  21                         rt_enable |= (NV40TCL_RT_ENABLE_COLOR0 << i);
  22                         rt[i] = fb->cbufs[i];
  23                 }
  24         }
  25
  26         if (rt_enable & (NV40TCL_RT_ENABLE_COLOR1 | NV40TCL_RT_ENABLE_COLOR2 |
  27                          NV40TCL_RT_ENABLE_COLOR3))
  28                 rt_enable |= NV40TCL_RT_ENABLE_MRT;
  29
  30         if (fb->zsbuf) {
  31                 zeta_format = fb->zsbuf->format;
  32                 zeta = fb->zsbuf;
  33         }
  34
  35         rt_format = NV40TCL_RT_FORMAT_TYPE_LINEAR;
  36
  37         switch (colour_format) {
  38         case PIPE_FORMAT_A8R8G8B8_UNORM:
  39         case 0:
  40                 rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8;
  41                 break;
  42         case PIPE_FORMAT_R5G6B5_UNORM:
  43                 rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5;
  44                 break;
  45         default:
  46                 assert(0);
  47         }
  48
  49         switch (zeta_format) {
  50         case PIPE_FORMAT_Z16_UNORM:
  51                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16;
  52                 break;
  53         case PIPE_FORMAT_Z24S8_UNORM:
  54         case 0:
  55                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8;
  56                 break;
  57         default:
  58                 assert(0);
  59         }
  60
  61         if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
  62                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR0, 1);
  63                 so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  64                           nv40->nvws->channel->vram->handle,
  65                           nv40->nvws->channel->gart->handle);
  66                 so_method(so, nv40->screen->curie, NV40TCL_COLOR0_PITCH, 2);
  67                 so_data  (so, rt[0]->pitch * rt[0]->cpp);
  68                 so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags |
  69                           NOUVEAU_BO_LOW, 0, 0);
  70         }
  71
  72         if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
  73                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR1, 1);
  74                 so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  75                           nv40->nvws->channel->vram->handle,
  76                           nv40->nvws->channel->gart->handle);
  77                 so_method(so, nv40->screen->curie, NV40TCL_COLOR1_OFFSET, 2);
  78                 so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags |
  79                           NOUVEAU_BO_LOW, 0, 0);
  80                 so_data  (so, rt[1]->pitch * rt[1]->cpp);
  81         }
  82
  83         if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
  84                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR2, 1);
  85                 so_reloc (so, rt[2]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  86                           nv40->nvws->channel->vram->handle,
  87                           nv40->nvws->channel->gart->handle);
  88                 so_method(so, nv40->screen->curie, NV40TCL_COLOR2_OFFSET, 1);
  89                 so_reloc (so, rt[2]->buffer, rt[2]->offset, rt_flags |
  90                           NOUVEAU_BO_LOW, 0, 0);
  91                 so_method(so, nv40->screen->curie, NV40TCL_COLOR2_PITCH, 1);
  92                 so_data  (so, rt[2]->pitch * rt[2]->cpp);
  93         }
  94
  95         if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
  96                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR3, 1);
  97                 so_reloc (so, rt[3]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  98                           nv40->nvws->channel->vram->handle,
  99                           nv40->nvws->channel->gart->handle);
 100                 so_method(so, nv40->screen->curie, NV40TCL_COLOR3_OFFSET, 1);
 101                 so_reloc (so, rt[3]->buffer, rt[3]->offset, rt_flags |
 102                           NOUVEAU_BO_LOW, 0, 0);
 103                 so_method(so, nv40->screen->curie, NV40TCL_COLOR3_PITCH, 1);
 104                 so_data  (so, rt[3]->pitch * rt[3]->cpp);
 105         }
 106
 107         if (zeta_format) {
 108                 so_method(so, nv40->screen->curie, NV40TCL_DMA_ZETA, 1);
 109                 so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR,
 110                           nv40->nvws->channel->vram->handle,
 111                           nv40->nvws->channel->gart->handle);
 112                 so_method(so, nv40->screen->curie, NV40TCL_ZETA_OFFSET, 1);
 113                 so_reloc (so, zeta->buffer, zeta->offset, rt_flags |
 114                           NOUVEAU_BO_LOW, 0, 0);
 115                 so_method(so, nv40->screen->curie, NV40TCL_ZETA_PITCH, 1);
 116                 so_data  (so, zeta->pitch * zeta->cpp);
 117         }
 118
 119         so_method(so, nv40->screen->curie, NV40TCL_RT_ENABLE, 1);
 120         so_data  (so, rt_enable);
 121         so_method(so, nv40->screen->curie, NV40TCL_RT_HORIZ, 3);
 122         so_data  (so, (w << 16) | 0);
 123         so_data  (so, (h << 16) | 0);
 124         so_data  (so, rt_format);
 125         so_method(so, nv40->screen->curie, NV40TCL_VIEWPORT_HORIZ, 2);
 126         so_data  (so, (w << 16) | 0);
 127         so_data  (so, (h << 16) | 0);
 128         so_method(so, nv40->screen->curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 129         so_data  (so, ((w - 1) << 16) | 0);
 130         so_data  (so, ((h - 1) << 16) | 0);
 131         so_method(so, nv40->screen->curie, 0x1d88, 1);
 132         so_data  (so, (1 << 12) | h);
 133
 134         so_ref(so, &nv40->state.hw[NV40_STATE_FB]);
 135         return TRUE;
 136 }
 137
 138 struct nv40_state_entry nv40_state_framebuffer = {
 139         .validate = nv40_state_framebuffer_validate,
 140         .dirty = {
 141                 .pipe = NV40_NEW_FB,
 142                 .hw = NV40_STATE_FB
 143         }
 144 };