1 #include "pipe/p_context.h"
2 #include "pipe/p_state.h"
3 #include "pipe/p_util.h"
5 #include "nv40_context.h"
6 #include "nv40_state.h"
8 #include "nouveau/nouveau_channel.h"
9 #include "nouveau/nouveau_pushbuf.h"
12 nv40_vbo_ncomp(uint format
)
16 if (pf_size_x(format
)) ncomp
++;
17 if (pf_size_y(format
)) ncomp
++;
18 if (pf_size_z(format
)) ncomp
++;
19 if (pf_size_w(format
)) ncomp
++;
25 nv40_vbo_type(uint format
)
27 switch (pf_type(format
)) {
28 case PIPE_FORMAT_TYPE_FLOAT
:
29 return NV40TCL_VTXFMT_TYPE_FLOAT
;
30 case PIPE_FORMAT_TYPE_UNORM
:
31 return NV40TCL_VTXFMT_TYPE_UBYTE
;
35 pf_sprint_name(fs
, format
);
36 NOUVEAU_ERR("Unknown format %s\n", fs
);
37 return NV40TCL_VTXFMT_TYPE_FLOAT
;
43 nv40_vbo_set_idxbuf(struct nv40_context
*nv40
, struct pipe_buffer
*ib
,
50 nv40
->idxbuf_format
= 0xdeadbeef;
54 /* No support for 8bit indices, no support at all on 0x4497 chips */
55 if (nv40
->hw
->curie
->grclass
== NV44TCL
|| ib_size
== 1)
60 type
= NV40TCL_IDXBUF_FORMAT_TYPE_U16
;
63 type
= NV40TCL_IDXBUF_FORMAT_TYPE_U32
;
69 if (ib
!= nv40
->idxbuf
||
70 type
!= nv40
->idxbuf_format
) {
71 nv40
->dirty
|= NV40_NEW_ARRAYS
;
73 nv40
->idxbuf_format
= type
;
80 nv40_vbo_static_attrib(struct nv40_context
*nv40
, int attrib
,
81 struct pipe_vertex_element
*ve
,
82 struct pipe_vertex_buffer
*vb
)
84 struct pipe_winsys
*ws
= nv40
->pipe
.winsys
;
88 type
= nv40_vbo_type(ve
->src_format
);
89 ncomp
= nv40_vbo_ncomp(ve
->src_format
);
91 map
= ws
->buffer_map(ws
, vb
->buffer
, PIPE_BUFFER_USAGE_CPU_READ
);
92 map
+= vb
->buffer_offset
+ ve
->src_offset
;
95 case NV40TCL_VTXFMT_TYPE_FLOAT
:
99 BEGIN_RING(curie
, NV40TCL_VTX_ATTR_4F_X(attrib
), 4);
126 ws
->buffer_unmap(ws
, vb
->buffer
);
132 ws
->buffer_unmap(ws
, vb
->buffer
);
136 ws
->buffer_unmap(ws
, vb
->buffer
);
142 nv40_draw_arrays(struct pipe_context
*pipe
, unsigned mode
, unsigned start
,
145 struct nv40_context
*nv40
= nv40_context(pipe
);
148 nv40_vbo_set_idxbuf(nv40
, NULL
, 0);
149 nv40_emit_hw_state(nv40
);
151 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
152 OUT_RING (nvgl_primitive(mode
));
156 BEGIN_RING(curie
, NV40TCL_VB_VERTEX_BATCH
, 1);
157 OUT_RING (((nr
- 1) << 24) | start
);
163 unsigned push
= nr
> 2047 ? 2047 : nr
;
167 BEGIN_RING_NI(curie
, NV40TCL_VB_VERTEX_BATCH
, push
);
169 OUT_RING(((0x100 - 1) << 24) | start
);
174 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
177 pipe
->flush(pipe
, 0);
182 nv40_draw_elements_u08(struct nv40_context
*nv40
, void *ib
,
183 unsigned start
, unsigned count
)
185 uint8_t *elts
= (uint8_t *)ib
+ start
;
189 BEGIN_RING(curie
, NV40TCL_VB_ELEMENT_U32
, 1);
195 push
= MIN2(count
, 2047 * 2);
197 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U16
, push
>> 1);
198 for (i
= 0; i
< push
; i
+=2)
199 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
207 nv40_draw_elements_u16(struct nv40_context
*nv40
, void *ib
,
208 unsigned start
, unsigned count
)
210 uint16_t *elts
= (uint16_t *)ib
+ start
;
214 BEGIN_RING(curie
, NV40TCL_VB_ELEMENT_U32
, 1);
220 push
= MIN2(count
, 2047 * 2);
222 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U16
, push
>> 1);
223 for (i
= 0; i
< push
; i
+=2)
224 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
232 nv40_draw_elements_u32(struct nv40_context
*nv40
, void *ib
,
233 unsigned start
, unsigned count
)
235 uint32_t *elts
= (uint32_t *)ib
+ start
;
239 push
= MIN2(count
, 2047);
241 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U32
, push
);
242 OUT_RINGp (elts
, push
);
250 nv40_draw_elements_inline(struct pipe_context
*pipe
,
251 struct pipe_buffer
*ib
, unsigned ib_size
,
252 unsigned mode
, unsigned start
, unsigned count
)
254 struct nv40_context
*nv40
= nv40_context(pipe
);
255 struct pipe_winsys
*ws
= pipe
->winsys
;
258 nv40_emit_hw_state(nv40
);
260 map
= ws
->buffer_map(ws
, ib
, PIPE_BUFFER_USAGE_CPU_READ
);
262 NOUVEAU_ERR("failed mapping ib\n");
266 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
267 OUT_RING (nvgl_primitive(mode
));
271 nv40_draw_elements_u08(nv40
, map
, start
, count
);
274 nv40_draw_elements_u16(nv40
, map
, start
, count
);
277 nv40_draw_elements_u32(nv40
, map
, start
, count
);
280 NOUVEAU_ERR("invalid idxbuf fmt %d\n", ib_size
);
284 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
287 ws
->buffer_unmap(ws
, ib
);
293 nv40_draw_elements_vbo(struct pipe_context
*pipe
,
294 unsigned mode
, unsigned start
, unsigned count
)
296 struct nv40_context
*nv40
= nv40_context(pipe
);
299 nv40_emit_hw_state(nv40
);
301 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
302 OUT_RING (nvgl_primitive(mode
));
306 BEGIN_RING(curie
, NV40TCL_VB_INDEX_BATCH
, 1);
307 OUT_RING (((nr
- 1) << 24) | start
);
313 unsigned push
= nr
> 2047 ? 2047 : nr
;
317 BEGIN_RING_NI(curie
, NV40TCL_VB_INDEX_BATCH
, push
);
319 OUT_RING(((0x100 - 1) << 24) | start
);
324 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
331 nv40_draw_elements(struct pipe_context
*pipe
,
332 struct pipe_buffer
*indexBuffer
, unsigned indexSize
,
333 unsigned mode
, unsigned start
, unsigned count
)
335 struct nv40_context
*nv40
= nv40_context(pipe
);
337 if (nv40_vbo_set_idxbuf(nv40
, indexBuffer
, indexSize
)) {
338 nv40_draw_elements_vbo(pipe
, mode
, start
, count
);
340 nv40_draw_elements_inline(pipe
, indexBuffer
, indexSize
,
344 pipe
->flush(pipe
, 0);
349 nv40_vbo_validate(struct nv40_context
*nv40
)
351 struct nv40_vertex_program
*vp
= nv40
->vertprog
;
352 struct nouveau_stateobj
*vtxbuf
, *vtxfmt
;
353 struct pipe_buffer
*ib
= nv40
->idxbuf
;
354 unsigned ib_format
= nv40
->idxbuf_format
;
355 unsigned inputs
, hw
, num_hw
;
356 unsigned vb_flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
;
359 for (hw
= 0; hw
< 16 && inputs
; hw
++) {
360 if (inputs
& (1 << hw
)) {
362 inputs
&= ~(1 << hw
);
367 vtxbuf
= so_new(20, 18);
368 so_method(vtxbuf
, nv40
->hw
->curie
, NV40TCL_VTXBUF_ADDRESS(0), num_hw
);
369 vtxfmt
= so_new(17, 0);
370 so_method(vtxfmt
, nv40
->hw
->curie
, NV40TCL_VTXFMT(0), num_hw
);
373 for (hw
= 0; hw
< num_hw
; hw
++) {
374 struct pipe_vertex_element
*ve
;
375 struct pipe_vertex_buffer
*vb
;
377 if (!(inputs
& (1 << hw
))) {
379 so_data(vtxfmt
, NV40TCL_VTXFMT_TYPE_FLOAT
);
383 ve
= &nv40
->vtxelt
[hw
];
384 vb
= &nv40
->vtxbuf
[ve
->vertex_buffer_index
];
386 if (!vb
->pitch
&& nv40_vbo_static_attrib(nv40
, hw
, ve
, vb
)) {
388 so_data(vtxfmt
, NV40TCL_VTXFMT_TYPE_FLOAT
);
392 so_reloc(vtxbuf
, vb
->buffer
, vb
->buffer_offset
+ ve
->src_offset
,
393 vb_flags
| NOUVEAU_BO_LOW
| NOUVEAU_BO_OR
,
394 0, NV40TCL_VTXBUF_ADDRESS_DMA1
);
395 so_data (vtxfmt
, ((vb
->pitch
<< NV40TCL_VTXFMT_STRIDE_SHIFT
) |
396 (nv40_vbo_ncomp(ve
->src_format
) <<
397 NV40TCL_VTXFMT_SIZE_SHIFT
) |
398 nv40_vbo_type(ve
->src_format
)));
402 so_method(vtxbuf
, nv40
->hw
->curie
, NV40TCL_IDXBUF_ADDRESS
, 2);
403 so_reloc (vtxbuf
, ib
, 0, vb_flags
| NOUVEAU_BO_LOW
, 0, 0);
404 so_reloc (vtxbuf
, ib
, ib_format
, vb_flags
| NOUVEAU_BO_OR
,
405 0, NV40TCL_IDXBUF_FORMAT_DMA1
);
408 so_method(vtxbuf
, nv40
->hw
->curie
, 0x1710, 1);
411 so_ref(vtxbuf
, &nv40
->state
.hw
[NV40_STATE_VTXBUF
]);
412 nv40
->state
.dirty
|= (1ULL << NV40_STATE_VTXBUF
);
413 so_ref(vtxfmt
, &nv40
->state
.hw
[NV40_STATE_VTXFMT
]);
414 nv40
->state
.dirty
|= (1ULL << NV40_STATE_VTXFMT
);
418 struct nv40_state_entry nv40_state_vbo
= {
419 .validate
= nv40_vbo_validate
,
421 .pipe
= NV40_NEW_ARRAYS
,