1 #include "pipe/p_context.h"
2 #include "pipe/p_state.h"
3 #include "pipe/p_util.h"
5 #include "nv40_context.h"
6 #include "nv40_state.h"
8 #include "nouveau/nouveau_channel.h"
9 #include "nouveau/nouveau_pushbuf.h"
14 nv40_vbo_format_to_hw(enum pipe_format pipe
, unsigned *fmt
, unsigned *ncomp
)
19 case PIPE_FORMAT_R32_FLOAT
:
20 case PIPE_FORMAT_R32G32_FLOAT
:
21 case PIPE_FORMAT_R32G32B32_FLOAT
:
22 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
23 *fmt
= NV40TCL_VTXFMT_TYPE_FLOAT
;
25 case PIPE_FORMAT_R8_UNORM
:
26 case PIPE_FORMAT_R8G8_UNORM
:
27 case PIPE_FORMAT_R8G8B8_UNORM
:
28 case PIPE_FORMAT_R8G8B8A8_UNORM
:
29 *fmt
= NV40TCL_VTXFMT_TYPE_UBYTE
;
31 case PIPE_FORMAT_R16_SSCALED
:
32 case PIPE_FORMAT_R16G16_SSCALED
:
33 case PIPE_FORMAT_R16G16B16_SSCALED
:
34 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
35 *fmt
= NV40TCL_VTXFMT_TYPE_USHORT
;
38 pf_sprint_name(fs
, pipe
);
39 NOUVEAU_ERR("Unknown format %s\n", fs
);
44 case PIPE_FORMAT_R8_UNORM
:
45 case PIPE_FORMAT_R32_FLOAT
:
46 case PIPE_FORMAT_R16_SSCALED
:
49 case PIPE_FORMAT_R8G8_UNORM
:
50 case PIPE_FORMAT_R32G32_FLOAT
:
51 case PIPE_FORMAT_R16G16_SSCALED
:
54 case PIPE_FORMAT_R8G8B8_UNORM
:
55 case PIPE_FORMAT_R32G32B32_FLOAT
:
56 case PIPE_FORMAT_R16G16B16_SSCALED
:
59 case PIPE_FORMAT_R8G8B8A8_UNORM
:
60 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
61 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
65 pf_sprint_name(fs
, pipe
);
66 NOUVEAU_ERR("Unknown format %s\n", fs
);
74 nv40_vbo_set_idxbuf(struct nv40_context
*nv40
, struct pipe_buffer
*ib
,
81 nv40
->idxbuf_format
= 0xdeadbeef;
85 /* No support for 8bit indices, no support at all on 0x4497 chips */
86 if (nv40
->screen
->curie
->grclass
== NV44TCL
|| ib_size
== 1)
91 type
= NV40TCL_IDXBUF_FORMAT_TYPE_U16
;
94 type
= NV40TCL_IDXBUF_FORMAT_TYPE_U32
;
100 if (ib
!= nv40
->idxbuf
||
101 type
!= nv40
->idxbuf_format
) {
102 nv40
->dirty
|= NV40_NEW_ARRAYS
;
104 nv40
->idxbuf_format
= type
;
111 nv40_vbo_static_attrib(struct nv40_context
*nv40
, int attrib
,
112 struct pipe_vertex_element
*ve
,
113 struct pipe_vertex_buffer
*vb
)
115 struct pipe_winsys
*ws
= nv40
->pipe
.winsys
;
116 unsigned type
, ncomp
;
119 if (nv40_vbo_format_to_hw(ve
->src_format
, &type
, &ncomp
))
122 map
= ws
->buffer_map(ws
, vb
->buffer
, PIPE_BUFFER_USAGE_CPU_READ
);
123 map
+= vb
->buffer_offset
+ ve
->src_offset
;
126 case NV40TCL_VTXFMT_TYPE_FLOAT
:
130 BEGIN_RING(curie
, NV40TCL_VTX_ATTR_4F_X(attrib
), 4);
157 ws
->buffer_unmap(ws
, vb
->buffer
);
163 ws
->buffer_unmap(ws
, vb
->buffer
);
167 ws
->buffer_unmap(ws
, vb
->buffer
);
173 nv40_draw_arrays(struct pipe_context
*pipe
, unsigned mode
, unsigned start
,
176 struct nv40_context
*nv40
= nv40_context(pipe
);
179 nv40_vbo_set_idxbuf(nv40
, NULL
, 0);
180 if (FORCE_SWTNL
|| !nv40_state_validate(nv40
)) {
181 return nv40_draw_elements_swtnl(pipe
, NULL
, 0,
184 nv40_state_emit(nv40
);
186 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
187 OUT_RING (nvgl_primitive(mode
));
191 BEGIN_RING(curie
, NV40TCL_VB_VERTEX_BATCH
, 1);
192 OUT_RING (((nr
- 1) << 24) | start
);
198 unsigned push
= nr
> 2047 ? 2047 : nr
;
202 BEGIN_RING_NI(curie
, NV40TCL_VB_VERTEX_BATCH
, push
);
204 OUT_RING(((0x100 - 1) << 24) | start
);
209 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
212 pipe
->flush(pipe
, 0, NULL
);
217 nv40_draw_elements_u08(struct nv40_context
*nv40
, void *ib
,
218 unsigned start
, unsigned count
)
220 uint8_t *elts
= (uint8_t *)ib
+ start
;
224 BEGIN_RING(curie
, NV40TCL_VB_ELEMENT_U32
, 1);
230 push
= MIN2(count
, 2047 * 2);
232 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U16
, push
>> 1);
233 for (i
= 0; i
< push
; i
+=2)
234 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
242 nv40_draw_elements_u16(struct nv40_context
*nv40
, void *ib
,
243 unsigned start
, unsigned count
)
245 uint16_t *elts
= (uint16_t *)ib
+ start
;
249 BEGIN_RING(curie
, NV40TCL_VB_ELEMENT_U32
, 1);
255 push
= MIN2(count
, 2047 * 2);
257 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U16
, push
>> 1);
258 for (i
= 0; i
< push
; i
+=2)
259 OUT_RING((elts
[i
+1] << 16) | elts
[i
]);
267 nv40_draw_elements_u32(struct nv40_context
*nv40
, void *ib
,
268 unsigned start
, unsigned count
)
270 uint32_t *elts
= (uint32_t *)ib
+ start
;
274 push
= MIN2(count
, 2047);
276 BEGIN_RING_NI(curie
, NV40TCL_VB_ELEMENT_U32
, push
);
277 OUT_RINGp (elts
, push
);
285 nv40_draw_elements_inline(struct pipe_context
*pipe
,
286 struct pipe_buffer
*ib
, unsigned ib_size
,
287 unsigned mode
, unsigned start
, unsigned count
)
289 struct nv40_context
*nv40
= nv40_context(pipe
);
290 struct pipe_winsys
*ws
= pipe
->winsys
;
293 nv40_state_emit(nv40
);
295 map
= ws
->buffer_map(ws
, ib
, PIPE_BUFFER_USAGE_CPU_READ
);
297 NOUVEAU_ERR("failed mapping ib\n");
301 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
302 OUT_RING (nvgl_primitive(mode
));
306 nv40_draw_elements_u08(nv40
, map
, start
, count
);
309 nv40_draw_elements_u16(nv40
, map
, start
, count
);
312 nv40_draw_elements_u32(nv40
, map
, start
, count
);
315 NOUVEAU_ERR("invalid idxbuf fmt %d\n", ib_size
);
319 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
322 ws
->buffer_unmap(ws
, ib
);
328 nv40_draw_elements_vbo(struct pipe_context
*pipe
,
329 unsigned mode
, unsigned start
, unsigned count
)
331 struct nv40_context
*nv40
= nv40_context(pipe
);
334 nv40_state_emit(nv40
);
336 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
337 OUT_RING (nvgl_primitive(mode
));
341 BEGIN_RING(curie
, NV40TCL_VB_INDEX_BATCH
, 1);
342 OUT_RING (((nr
- 1) << 24) | start
);
348 unsigned push
= nr
> 2047 ? 2047 : nr
;
352 BEGIN_RING_NI(curie
, NV40TCL_VB_INDEX_BATCH
, push
);
354 OUT_RING(((0x100 - 1) << 24) | start
);
359 BEGIN_RING(curie
, NV40TCL_BEGIN_END
, 1);
366 nv40_draw_elements(struct pipe_context
*pipe
,
367 struct pipe_buffer
*indexBuffer
, unsigned indexSize
,
368 unsigned mode
, unsigned start
, unsigned count
)
370 struct nv40_context
*nv40
= nv40_context(pipe
);
373 idxbuf
= nv40_vbo_set_idxbuf(nv40
, indexBuffer
, indexSize
);
374 if (FORCE_SWTNL
|| !nv40_state_validate(nv40
)) {
375 return nv40_draw_elements_swtnl(pipe
, NULL
, 0,
378 nv40_state_emit(nv40
);
381 nv40_draw_elements_vbo(pipe
, mode
, start
, count
);
383 nv40_draw_elements_inline(pipe
, indexBuffer
, indexSize
,
387 pipe
->flush(pipe
, 0, NULL
);
392 nv40_vbo_validate(struct nv40_context
*nv40
)
394 struct nv40_vertex_program
*vp
= nv40
->vertprog
;
395 struct nouveau_stateobj
*vtxbuf
, *vtxfmt
;
396 struct pipe_buffer
*ib
= nv40
->idxbuf
;
397 unsigned ib_format
= nv40
->idxbuf_format
;
398 unsigned inputs
, hw
, num_hw
;
399 unsigned vb_flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
;
402 for (hw
= 0; hw
< 16 && inputs
; hw
++) {
403 if (inputs
& (1 << hw
)) {
405 inputs
&= ~(1 << hw
);
410 vtxbuf
= so_new(20, 18);
411 so_method(vtxbuf
, nv40
->screen
->curie
, NV40TCL_VTXBUF_ADDRESS(0), num_hw
);
412 vtxfmt
= so_new(17, 0);
413 so_method(vtxfmt
, nv40
->screen
->curie
, NV40TCL_VTXFMT(0), num_hw
);
416 for (hw
= 0; hw
< num_hw
; hw
++) {
417 struct pipe_vertex_element
*ve
;
418 struct pipe_vertex_buffer
*vb
;
419 unsigned type
, ncomp
;
421 if (!(inputs
& (1 << hw
))) {
423 so_data(vtxfmt
, NV40TCL_VTXFMT_TYPE_FLOAT
);
427 ve
= &nv40
->vtxelt
[hw
];
428 vb
= &nv40
->vtxbuf
[ve
->vertex_buffer_index
];
430 if (!vb
->pitch
&& nv40_vbo_static_attrib(nv40
, hw
, ve
, vb
)) {
432 so_data(vtxfmt
, NV40TCL_VTXFMT_TYPE_FLOAT
);
436 if (nv40_vbo_format_to_hw(ve
->src_format
, &type
, &ncomp
)) {
437 nv40
->fallback_swtnl
|= NV40_NEW_ARRAYS
;
438 so_ref(NULL
, &vtxbuf
);
439 so_ref(NULL
, &vtxfmt
);
443 so_reloc(vtxbuf
, vb
->buffer
, vb
->buffer_offset
+ ve
->src_offset
,
444 vb_flags
| NOUVEAU_BO_LOW
| NOUVEAU_BO_OR
,
445 0, NV40TCL_VTXBUF_ADDRESS_DMA1
);
446 so_data (vtxfmt
, ((vb
->pitch
<< NV40TCL_VTXFMT_STRIDE_SHIFT
) |
447 (ncomp
<< NV40TCL_VTXFMT_SIZE_SHIFT
) | type
));
451 so_method(vtxbuf
, nv40
->screen
->curie
, NV40TCL_IDXBUF_ADDRESS
, 2);
452 so_reloc (vtxbuf
, ib
, 0, vb_flags
| NOUVEAU_BO_LOW
, 0, 0);
453 so_reloc (vtxbuf
, ib
, ib_format
, vb_flags
| NOUVEAU_BO_OR
,
454 0, NV40TCL_IDXBUF_FORMAT_DMA1
);
457 so_method(vtxbuf
, nv40
->screen
->curie
, 0x1710, 1);
460 so_ref(vtxbuf
, &nv40
->state
.hw
[NV40_STATE_VTXBUF
]);
461 nv40
->state
.dirty
|= (1ULL << NV40_STATE_VTXBUF
);
462 so_ref(vtxfmt
, &nv40
->state
.hw
[NV40_STATE_VTXFMT
]);
463 nv40
->state
.dirty
|= (1ULL << NV40_STATE_VTXFMT
);
467 struct nv40_state_entry nv40_state_vbo
= {
468 .validate
= nv40_vbo_validate
,
470 .pipe
= NV40_NEW_ARRAYS
,