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gallium: remove the swizzling parts of ExtSwizzle
[mesa.git] / src / gallium / drivers / nv40 / nv40_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
9
10 #include "nv40_context.h"
11 #include "nv40_state.h"
12
13 /* TODO (at least...):
14 * 1. Indexed consts + ARL
15 * 3. NV_vp11, NV_vp2, NV_vp3 features
16 * - extra arith opcodes
17 * - branching
18 * - texture sampling
19 * - indexed attribs
20 * - indexed results
21 * 4. bugs
22 */
23
24 #define SWZ_X 0
25 #define SWZ_Y 1
26 #define SWZ_Z 2
27 #define SWZ_W 3
28 #define MASK_X 8
29 #define MASK_Y 4
30 #define MASK_Z 2
31 #define MASK_W 1
32 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
33 #define DEF_SCALE 0
34 #define DEF_CTEST 0
35 #include "nv40_shader.h"
36
37 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
38 #define neg(s) nv40_sr_neg((s))
39 #define abs(s) nv40_sr_abs((s))
40
41 #define NV40_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
42
43 struct nv40_vpc {
44 struct nv40_vertex_program *vp;
45
46 struct nv40_vertex_program_exec *vpi;
47
48 unsigned r_temps;
49 unsigned r_temps_discard;
50 struct nv40_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
51 struct nv40_sreg *r_address;
52 struct nv40_sreg *r_temp;
53
54 struct nv40_sreg *imm;
55 unsigned nr_imm;
56
57 unsigned hpos_idx;
58 };
59
60 static struct nv40_sreg
61 temp(struct nv40_vpc *vpc)
62 {
63 int idx = ffs(~vpc->r_temps) - 1;
64
65 if (idx < 0) {
66 NOUVEAU_ERR("out of temps!!\n");
67 assert(0);
68 return nv40_sr(NV40SR_TEMP, 0);
69 }
70
71 vpc->r_temps |= (1 << idx);
72 vpc->r_temps_discard |= (1 << idx);
73 return nv40_sr(NV40SR_TEMP, idx);
74 }
75
76 static INLINE void
77 release_temps(struct nv40_vpc *vpc)
78 {
79 vpc->r_temps &= ~vpc->r_temps_discard;
80 vpc->r_temps_discard = 0;
81 }
82
83 static struct nv40_sreg
84 constant(struct nv40_vpc *vpc, int pipe, float x, float y, float z, float w)
85 {
86 struct nv40_vertex_program *vp = vpc->vp;
87 struct nv40_vertex_program_data *vpd;
88 int idx;
89
90 if (pipe >= 0) {
91 for (idx = 0; idx < vp->nr_consts; idx++) {
92 if (vp->consts[idx].index == pipe)
93 return nv40_sr(NV40SR_CONST, idx);
94 }
95 }
96
97 idx = vp->nr_consts++;
98 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
99 vpd = &vp->consts[idx];
100
101 vpd->index = pipe;
102 vpd->value[0] = x;
103 vpd->value[1] = y;
104 vpd->value[2] = z;
105 vpd->value[3] = w;
106 return nv40_sr(NV40SR_CONST, idx);
107 }
108
109 #define arith(cc,s,o,d,m,s0,s1,s2) \
110 nv40_vp_arith((cc), (s), NV40_VP_INST_##o, (d), (m), (s0), (s1), (s2))
111
112 static void
113 emit_src(struct nv40_vpc *vpc, uint32_t *hw, int pos, struct nv40_sreg src)
114 {
115 struct nv40_vertex_program *vp = vpc->vp;
116 uint32_t sr = 0;
117
118 switch (src.type) {
119 case NV40SR_TEMP:
120 sr |= (NV40_VP_SRC_REG_TYPE_TEMP << NV40_VP_SRC_REG_TYPE_SHIFT);
121 sr |= (src.index << NV40_VP_SRC_TEMP_SRC_SHIFT);
122 break;
123 case NV40SR_INPUT:
124 sr |= (NV40_VP_SRC_REG_TYPE_INPUT <<
125 NV40_VP_SRC_REG_TYPE_SHIFT);
126 vp->ir |= (1 << src.index);
127 hw[1] |= (src.index << NV40_VP_INST_INPUT_SRC_SHIFT);
128 break;
129 case NV40SR_CONST:
130 sr |= (NV40_VP_SRC_REG_TYPE_CONST <<
131 NV40_VP_SRC_REG_TYPE_SHIFT);
132 assert(vpc->vpi->const_index == -1 ||
133 vpc->vpi->const_index == src.index);
134 vpc->vpi->const_index = src.index;
135 break;
136 case NV40SR_NONE:
137 sr |= (NV40_VP_SRC_REG_TYPE_INPUT <<
138 NV40_VP_SRC_REG_TYPE_SHIFT);
139 break;
140 default:
141 assert(0);
142 }
143
144 if (src.negate)
145 sr |= NV40_VP_SRC_NEGATE;
146
147 if (src.abs)
148 hw[0] |= (1 << (21 + pos));
149
150 sr |= ((src.swz[0] << NV40_VP_SRC_SWZ_X_SHIFT) |
151 (src.swz[1] << NV40_VP_SRC_SWZ_Y_SHIFT) |
152 (src.swz[2] << NV40_VP_SRC_SWZ_Z_SHIFT) |
153 (src.swz[3] << NV40_VP_SRC_SWZ_W_SHIFT));
154
155 switch (pos) {
156 case 0:
157 hw[1] |= ((sr & NV40_VP_SRC0_HIGH_MASK) >>
158 NV40_VP_SRC0_HIGH_SHIFT) << NV40_VP_INST_SRC0H_SHIFT;
159 hw[2] |= (sr & NV40_VP_SRC0_LOW_MASK) <<
160 NV40_VP_INST_SRC0L_SHIFT;
161 break;
162 case 1:
163 hw[2] |= sr << NV40_VP_INST_SRC1_SHIFT;
164 break;
165 case 2:
166 hw[2] |= ((sr & NV40_VP_SRC2_HIGH_MASK) >>
167 NV40_VP_SRC2_HIGH_SHIFT) << NV40_VP_INST_SRC2H_SHIFT;
168 hw[3] |= (sr & NV40_VP_SRC2_LOW_MASK) <<
169 NV40_VP_INST_SRC2L_SHIFT;
170 break;
171 default:
172 assert(0);
173 }
174 }
175
176 static void
177 emit_dst(struct nv40_vpc *vpc, uint32_t *hw, int slot, struct nv40_sreg dst)
178 {
179 struct nv40_vertex_program *vp = vpc->vp;
180
181 switch (dst.type) {
182 case NV40SR_TEMP:
183 hw[3] |= NV40_VP_INST_DEST_MASK;
184 if (slot == 0) {
185 hw[0] |= (dst.index <<
186 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
187 } else {
188 hw[3] |= (dst.index <<
189 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
190 }
191 break;
192 case NV40SR_OUTPUT:
193 switch (dst.index) {
194 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
195 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
196 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
197 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
198 case NV40_VP_INST_DEST_FOGC : vp->or |= (1 << 4); break;
199 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
200 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
201 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
202 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
203 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
204 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
205 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
206 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
207 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
208 case NV40_VP_INST_DEST_CLIP(0):
209 vp->or |= (1 << 6);
210 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE0;
211 dst.index = NV40_VP_INST_DEST_FOGC;
212 break;
213 case NV40_VP_INST_DEST_CLIP(1):
214 vp->or |= (1 << 7);
215 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE1;
216 dst.index = NV40_VP_INST_DEST_FOGC;
217 break;
218 case NV40_VP_INST_DEST_CLIP(2):
219 vp->or |= (1 << 8);
220 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE2;
221 dst.index = NV40_VP_INST_DEST_FOGC;
222 break;
223 case NV40_VP_INST_DEST_CLIP(3):
224 vp->or |= (1 << 9);
225 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE3;
226 dst.index = NV40_VP_INST_DEST_PSZ;
227 break;
228 case NV40_VP_INST_DEST_CLIP(4):
229 vp->or |= (1 << 10);
230 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE4;
231 dst.index = NV40_VP_INST_DEST_PSZ;
232 break;
233 case NV40_VP_INST_DEST_CLIP(5):
234 vp->or |= (1 << 11);
235 vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE5;
236 dst.index = NV40_VP_INST_DEST_PSZ;
237 break;
238 default:
239 break;
240 }
241
242 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
243 if (slot == 0) {
244 hw[0] |= NV40_VP_INST_VEC_RESULT;
245 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
246 } else {
247 hw[3] |= NV40_VP_INST_SCA_RESULT;
248 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
249 }
250 break;
251 default:
252 assert(0);
253 }
254 }
255
256 static void
257 nv40_vp_arith(struct nv40_vpc *vpc, int slot, int op,
258 struct nv40_sreg dst, int mask,
259 struct nv40_sreg s0, struct nv40_sreg s1,
260 struct nv40_sreg s2)
261 {
262 struct nv40_vertex_program *vp = vpc->vp;
263 uint32_t *hw;
264
265 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
266 vpc->vpi = &vp->insns[vp->nr_insns - 1];
267 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
268 vpc->vpi->const_index = -1;
269
270 hw = vpc->vpi->data;
271
272 hw[0] |= (NV40_VP_INST_COND_TR << NV40_VP_INST_COND_SHIFT);
273 hw[0] |= ((0 << NV40_VP_INST_COND_SWZ_X_SHIFT) |
274 (1 << NV40_VP_INST_COND_SWZ_Y_SHIFT) |
275 (2 << NV40_VP_INST_COND_SWZ_Z_SHIFT) |
276 (3 << NV40_VP_INST_COND_SWZ_W_SHIFT));
277
278 if (slot == 0) {
279 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
280 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
281 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
282 } else {
283 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
284 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
285 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
286 }
287
288 emit_dst(vpc, hw, slot, dst);
289 emit_src(vpc, hw, 0, s0);
290 emit_src(vpc, hw, 1, s1);
291 emit_src(vpc, hw, 2, s2);
292 }
293
294 static INLINE struct nv40_sreg
295 tgsi_src(struct nv40_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
296 struct nv40_sreg src;
297
298 switch (fsrc->SrcRegister.File) {
299 case TGSI_FILE_INPUT:
300 src = nv40_sr(NV40SR_INPUT, fsrc->SrcRegister.Index);
301 break;
302 case TGSI_FILE_CONSTANT:
303 src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
304 break;
305 case TGSI_FILE_IMMEDIATE:
306 src = vpc->imm[fsrc->SrcRegister.Index];
307 break;
308 case TGSI_FILE_TEMPORARY:
309 src = vpc->r_temp[fsrc->SrcRegister.Index];
310 break;
311 default:
312 NOUVEAU_ERR("bad src file\n");
313 break;
314 }
315
316 src.abs = fsrc->SrcRegisterExtMod.Absolute;
317 src.negate = fsrc->SrcRegister.Negate;
318 src.swz[0] = fsrc->SrcRegister.SwizzleX;
319 src.swz[1] = fsrc->SrcRegister.SwizzleY;
320 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
321 src.swz[3] = fsrc->SrcRegister.SwizzleW;
322 return src;
323 }
324
325 static INLINE struct nv40_sreg
326 tgsi_dst(struct nv40_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
327 struct nv40_sreg dst;
328
329 switch (fdst->DstRegister.File) {
330 case TGSI_FILE_OUTPUT:
331 dst = vpc->r_result[fdst->DstRegister.Index];
332 break;
333 case TGSI_FILE_TEMPORARY:
334 dst = vpc->r_temp[fdst->DstRegister.Index];
335 break;
336 case TGSI_FILE_ADDRESS:
337 dst = vpc->r_address[fdst->DstRegister.Index];
338 break;
339 default:
340 NOUVEAU_ERR("bad dst file\n");
341 break;
342 }
343
344 return dst;
345 }
346
347 static INLINE int
348 tgsi_mask(uint tgsi)
349 {
350 int mask = 0;
351
352 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
353 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
354 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
355 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
356 return mask;
357 }
358
359 static boolean
360 src_native_swz(struct nv40_vpc *vpc, const struct tgsi_full_src_register *fsrc,
361 struct nv40_sreg *src)
362 {
363 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
364 struct nv40_sreg tgsi = tgsi_src(vpc, fsrc);
365 uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
366 uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
367 fsrc->SrcRegisterExtSwz.NegateY,
368 fsrc->SrcRegisterExtSwz.NegateZ,
369 fsrc->SrcRegisterExtSwz.NegateW };
370 uint c;
371
372 for (c = 0; c < 4; c++) {
373 switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) {
374 case TGSI_SWIZZLE_X:
375 case TGSI_SWIZZLE_Y:
376 case TGSI_SWIZZLE_Z:
377 case TGSI_SWIZZLE_W:
378 mask |= tgsi_mask(1 << c);
379 break;
380 default:
381 assert(0);
382 }
383
384 if (!tgsi.negate && neg[c])
385 neg_mask |= tgsi_mask(1 << c);
386 }
387
388 if (mask == MASK_ALL && !neg_mask)
389 return TRUE;
390
391 *src = temp(vpc);
392
393 if (mask)
394 arith(vpc, 0, OP_MOV, *src, mask, tgsi, none, none);
395
396 if (zero_mask)
397 arith(vpc, 0, OP_SFL, *src, zero_mask, *src, none, none);
398
399 if (one_mask)
400 arith(vpc, 0, OP_STR, *src, one_mask, *src, none, none);
401
402 if (neg_mask) {
403 struct nv40_sreg one = temp(vpc);
404 arith(vpc, 0, OP_STR, one, neg_mask, one, none, none);
405 arith(vpc, 0, OP_MUL, *src, neg_mask, *src, neg(one), none);
406 }
407
408 return FALSE;
409 }
410
411 static boolean
412 nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
413 const struct tgsi_full_instruction *finst)
414 {
415 struct nv40_sreg src[3], dst, tmp;
416 struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
417 int mask;
418 int ai = -1, ci = -1, ii = -1;
419 int i;
420
421 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
422 return TRUE;
423
424 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
425 const struct tgsi_full_src_register *fsrc;
426
427 fsrc = &finst->FullSrcRegisters[i];
428 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
429 src[i] = tgsi_src(vpc, fsrc);
430 }
431 }
432
433 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
434 const struct tgsi_full_src_register *fsrc;
435
436 fsrc = &finst->FullSrcRegisters[i];
437
438 switch (fsrc->SrcRegister.File) {
439 case TGSI_FILE_INPUT:
440 case TGSI_FILE_CONSTANT:
441 case TGSI_FILE_TEMPORARY:
442 if (!src_native_swz(vpc, fsrc, &src[i]))
443 continue;
444 break;
445 default:
446 break;
447 }
448
449 switch (fsrc->SrcRegister.File) {
450 case TGSI_FILE_INPUT:
451 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
452 ai = fsrc->SrcRegister.Index;
453 src[i] = tgsi_src(vpc, fsrc);
454 } else {
455 src[i] = temp(vpc);
456 arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
457 tgsi_src(vpc, fsrc), none, none);
458 }
459 break;
460 case TGSI_FILE_CONSTANT:
461 if ((ci == -1 && ii == -1) ||
462 ci == fsrc->SrcRegister.Index) {
463 ci = fsrc->SrcRegister.Index;
464 src[i] = tgsi_src(vpc, fsrc);
465 } else {
466 src[i] = temp(vpc);
467 arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
468 tgsi_src(vpc, fsrc), none, none);
469 }
470 break;
471 case TGSI_FILE_IMMEDIATE:
472 if ((ci == -1 && ii == -1) ||
473 ii == fsrc->SrcRegister.Index) {
474 ii = fsrc->SrcRegister.Index;
475 src[i] = tgsi_src(vpc, fsrc);
476 } else {
477 src[i] = temp(vpc);
478 arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
479 tgsi_src(vpc, fsrc), none, none);
480 }
481 break;
482 case TGSI_FILE_TEMPORARY:
483 /* handled above */
484 break;
485 default:
486 NOUVEAU_ERR("bad src file\n");
487 return FALSE;
488 }
489 }
490
491 dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
492 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
493
494 switch (finst->Instruction.Opcode) {
495 case TGSI_OPCODE_ABS:
496 arith(vpc, 0, OP_MOV, dst, mask, abs(src[0]), none, none);
497 break;
498 case TGSI_OPCODE_ADD:
499 arith(vpc, 0, OP_ADD, dst, mask, src[0], none, src[1]);
500 break;
501 case TGSI_OPCODE_ARL:
502 arith(vpc, 0, OP_ARL, dst, mask, src[0], none, none);
503 break;
504 case TGSI_OPCODE_DP3:
505 arith(vpc, 0, OP_DP3, dst, mask, src[0], src[1], none);
506 break;
507 case TGSI_OPCODE_DP4:
508 arith(vpc, 0, OP_DP4, dst, mask, src[0], src[1], none);
509 break;
510 case TGSI_OPCODE_DPH:
511 arith(vpc, 0, OP_DPH, dst, mask, src[0], src[1], none);
512 break;
513 case TGSI_OPCODE_DST:
514 arith(vpc, 0, OP_DST, dst, mask, src[0], src[1], none);
515 break;
516 case TGSI_OPCODE_EX2:
517 arith(vpc, 1, OP_EX2, dst, mask, none, none, src[0]);
518 break;
519 case TGSI_OPCODE_EXP:
520 arith(vpc, 1, OP_EXP, dst, mask, none, none, src[0]);
521 break;
522 case TGSI_OPCODE_FLR:
523 arith(vpc, 0, OP_FLR, dst, mask, src[0], none, none);
524 break;
525 case TGSI_OPCODE_FRC:
526 arith(vpc, 0, OP_FRC, dst, mask, src[0], none, none);
527 break;
528 case TGSI_OPCODE_LG2:
529 arith(vpc, 1, OP_LG2, dst, mask, none, none, src[0]);
530 break;
531 case TGSI_OPCODE_LIT:
532 arith(vpc, 1, OP_LIT, dst, mask, none, none, src[0]);
533 break;
534 case TGSI_OPCODE_LOG:
535 arith(vpc, 1, OP_LOG, dst, mask, none, none, src[0]);
536 break;
537 case TGSI_OPCODE_MAD:
538 arith(vpc, 0, OP_MAD, dst, mask, src[0], src[1], src[2]);
539 break;
540 case TGSI_OPCODE_MAX:
541 arith(vpc, 0, OP_MAX, dst, mask, src[0], src[1], none);
542 break;
543 case TGSI_OPCODE_MIN:
544 arith(vpc, 0, OP_MIN, dst, mask, src[0], src[1], none);
545 break;
546 case TGSI_OPCODE_MOV:
547 arith(vpc, 0, OP_MOV, dst, mask, src[0], none, none);
548 break;
549 case TGSI_OPCODE_MUL:
550 arith(vpc, 0, OP_MUL, dst, mask, src[0], src[1], none);
551 break;
552 case TGSI_OPCODE_POW:
553 tmp = temp(vpc);
554 arith(vpc, 1, OP_LG2, tmp, MASK_X, none, none,
555 swz(src[0], X, X, X, X));
556 arith(vpc, 0, OP_MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
557 swz(src[1], X, X, X, X), none);
558 arith(vpc, 1, OP_EX2, dst, mask, none, none,
559 swz(tmp, X, X, X, X));
560 break;
561 case TGSI_OPCODE_RCP:
562 arith(vpc, 1, OP_RCP, dst, mask, none, none, src[0]);
563 break;
564 case TGSI_OPCODE_RET:
565 break;
566 case TGSI_OPCODE_RSQ:
567 arith(vpc, 1, OP_RSQ, dst, mask, none, none, abs(src[0]));
568 break;
569 case TGSI_OPCODE_SGE:
570 arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
571 break;
572 case TGSI_OPCODE_SLT:
573 arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
574 break;
575 case TGSI_OPCODE_SUB:
576 arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
577 break;
578 case TGSI_OPCODE_XPD:
579 tmp = temp(vpc);
580 arith(vpc, 0, OP_MUL, tmp, mask,
581 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
582 arith(vpc, 0, OP_MAD, dst, (mask & ~MASK_W),
583 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
584 neg(tmp));
585 break;
586 default:
587 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
588 return FALSE;
589 }
590
591 release_temps(vpc);
592 return TRUE;
593 }
594
595 static boolean
596 nv40_vertprog_parse_decl_output(struct nv40_vpc *vpc,
597 const struct tgsi_full_declaration *fdec)
598 {
599 unsigned idx = fdec->DeclarationRange.First;
600 int hw;
601
602 switch (fdec->Semantic.SemanticName) {
603 case TGSI_SEMANTIC_POSITION:
604 hw = NV40_VP_INST_DEST_POS;
605 vpc->hpos_idx = idx;
606 break;
607 case TGSI_SEMANTIC_COLOR:
608 if (fdec->Semantic.SemanticIndex == 0) {
609 hw = NV40_VP_INST_DEST_COL0;
610 } else
611 if (fdec->Semantic.SemanticIndex == 1) {
612 hw = NV40_VP_INST_DEST_COL1;
613 } else {
614 NOUVEAU_ERR("bad colour semantic index\n");
615 return FALSE;
616 }
617 break;
618 case TGSI_SEMANTIC_BCOLOR:
619 if (fdec->Semantic.SemanticIndex == 0) {
620 hw = NV40_VP_INST_DEST_BFC0;
621 } else
622 if (fdec->Semantic.SemanticIndex == 1) {
623 hw = NV40_VP_INST_DEST_BFC1;
624 } else {
625 NOUVEAU_ERR("bad bcolour semantic index\n");
626 return FALSE;
627 }
628 break;
629 case TGSI_SEMANTIC_FOG:
630 hw = NV40_VP_INST_DEST_FOGC;
631 break;
632 case TGSI_SEMANTIC_PSIZE:
633 hw = NV40_VP_INST_DEST_PSZ;
634 break;
635 case TGSI_SEMANTIC_GENERIC:
636 if (fdec->Semantic.SemanticIndex <= 7) {
637 hw = NV40_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
638 } else {
639 NOUVEAU_ERR("bad generic semantic index\n");
640 return FALSE;
641 }
642 break;
643 default:
644 NOUVEAU_ERR("bad output semantic\n");
645 return FALSE;
646 }
647
648 vpc->r_result[idx] = nv40_sr(NV40SR_OUTPUT, hw);
649 return TRUE;
650 }
651
652 static boolean
653 nv40_vertprog_prepare(struct nv40_vpc *vpc)
654 {
655 struct tgsi_parse_context p;
656 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
657
658 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
659 while (!tgsi_parse_end_of_tokens(&p)) {
660 const union tgsi_full_token *tok = &p.FullToken;
661
662 tgsi_parse_token(&p);
663 switch(tok->Token.Type) {
664 case TGSI_TOKEN_TYPE_IMMEDIATE:
665 nr_imm++;
666 break;
667 case TGSI_TOKEN_TYPE_DECLARATION:
668 {
669 const struct tgsi_full_declaration *fdec;
670
671 fdec = &p.FullToken.FullDeclaration;
672 switch (fdec->Declaration.File) {
673 case TGSI_FILE_TEMPORARY:
674 if (fdec->DeclarationRange.Last > high_temp) {
675 high_temp =
676 fdec->DeclarationRange.Last;
677 }
678 break;
679 #if 0 /* this would be nice.. except gallium doesn't track it */
680 case TGSI_FILE_ADDRESS:
681 if (fdec->DeclarationRange.Last > high_addr) {
682 high_addr =
683 fdec->DeclarationRange.Last;
684 }
685 break;
686 #endif
687 case TGSI_FILE_OUTPUT:
688 if (!nv40_vertprog_parse_decl_output(vpc, fdec))
689 return FALSE;
690 break;
691 default:
692 break;
693 }
694 }
695 break;
696 #if 1 /* yay, parse instructions looking for address regs instead */
697 case TGSI_TOKEN_TYPE_INSTRUCTION:
698 {
699 const struct tgsi_full_instruction *finst;
700 const struct tgsi_full_dst_register *fdst;
701
702 finst = &p.FullToken.FullInstruction;
703 fdst = &finst->FullDstRegisters[0];
704
705 if (fdst->DstRegister.File == TGSI_FILE_ADDRESS) {
706 if (fdst->DstRegister.Index > high_addr)
707 high_addr = fdst->DstRegister.Index;
708 }
709
710 }
711 break;
712 #endif
713 default:
714 break;
715 }
716 }
717 tgsi_parse_free(&p);
718
719 if (nr_imm) {
720 vpc->imm = CALLOC(nr_imm, sizeof(struct nv40_sreg));
721 assert(vpc->imm);
722 }
723
724 if (++high_temp) {
725 vpc->r_temp = CALLOC(high_temp, sizeof(struct nv40_sreg));
726 for (i = 0; i < high_temp; i++)
727 vpc->r_temp[i] = temp(vpc);
728 }
729
730 if (++high_addr) {
731 vpc->r_address = CALLOC(high_addr, sizeof(struct nv40_sreg));
732 for (i = 0; i < high_addr; i++)
733 vpc->r_address[i] = temp(vpc);
734 }
735
736 vpc->r_temps_discard = 0;
737 return TRUE;
738 }
739
740 static void
741 nv40_vertprog_translate(struct nv40_context *nv40,
742 struct nv40_vertex_program *vp)
743 {
744 struct tgsi_parse_context parse;
745 struct nv40_vpc *vpc = NULL;
746 struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
747 int i;
748
749 vpc = CALLOC(1, sizeof(struct nv40_vpc));
750 if (!vpc)
751 return;
752 vpc->vp = vp;
753
754 if (!nv40_vertprog_prepare(vpc)) {
755 FREE(vpc);
756 return;
757 }
758
759 /* Redirect post-transform vertex position to a temp if user clip
760 * planes are enabled. We need to append code the the vtxprog
761 * to handle clip planes later.
762 */
763 if (vp->ucp.nr) {
764 vpc->r_result[vpc->hpos_idx] = temp(vpc);
765 vpc->r_temps_discard = 0;
766 }
767
768 tgsi_parse_init(&parse, vp->pipe.tokens);
769
770 while (!tgsi_parse_end_of_tokens(&parse)) {
771 tgsi_parse_token(&parse);
772
773 switch (parse.FullToken.Token.Type) {
774 case TGSI_TOKEN_TYPE_IMMEDIATE:
775 {
776 const struct tgsi_full_immediate *imm;
777
778 imm = &parse.FullToken.FullImmediate;
779 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
780 assert(imm->Immediate.NrTokens == 4 + 1);
781 vpc->imm[vpc->nr_imm++] =
782 constant(vpc, -1,
783 imm->u[0].Float,
784 imm->u[1].Float,
785 imm->u[2].Float,
786 imm->u[3].Float);
787 }
788 break;
789 case TGSI_TOKEN_TYPE_INSTRUCTION:
790 {
791 const struct tgsi_full_instruction *finst;
792 finst = &parse.FullToken.FullInstruction;
793 if (!nv40_vertprog_parse_instruction(vpc, finst))
794 goto out_err;
795 }
796 break;
797 default:
798 break;
799 }
800 }
801
802 /* Write out HPOS if it was redirected to a temp earlier */
803 if (vpc->r_result[vpc->hpos_idx].type != NV40SR_OUTPUT) {
804 struct nv40_sreg hpos = nv40_sr(NV40SR_OUTPUT,
805 NV40_VP_INST_DEST_POS);
806 struct nv40_sreg htmp = vpc->r_result[vpc->hpos_idx];
807
808 arith(vpc, 0, OP_MOV, hpos, MASK_ALL, htmp, none, none);
809 }
810
811 /* Insert code to handle user clip planes */
812 for (i = 0; i < vp->ucp.nr; i++) {
813 struct nv40_sreg cdst = nv40_sr(NV40SR_OUTPUT,
814 NV40_VP_INST_DEST_CLIP(i));
815 struct nv40_sreg ceqn = constant(vpc, -1,
816 nv40->clip.ucp[i][0],
817 nv40->clip.ucp[i][1],
818 nv40->clip.ucp[i][2],
819 nv40->clip.ucp[i][3]);
820 struct nv40_sreg htmp = vpc->r_result[vpc->hpos_idx];
821 unsigned mask;
822
823 switch (i) {
824 case 0: case 3: mask = MASK_Y; break;
825 case 1: case 4: mask = MASK_Z; break;
826 case 2: case 5: mask = MASK_W; break;
827 default:
828 NOUVEAU_ERR("invalid clip dist #%d\n", i);
829 goto out_err;
830 }
831
832 arith(vpc, 0, OP_DP4, cdst, mask, htmp, ceqn, none);
833 }
834
835 vp->insns[vp->nr_insns - 1].data[3] |= NV40_VP_INST_LAST;
836 vp->translated = TRUE;
837 out_err:
838 tgsi_parse_free(&parse);
839 if (vpc->r_temp)
840 FREE(vpc->r_temp);
841 if (vpc->r_address)
842 FREE(vpc->r_address);
843 if (vpc->imm)
844 FREE(vpc->imm);
845 FREE(vpc);
846 }
847
848 static boolean
849 nv40_vertprog_validate(struct nv40_context *nv40)
850 {
851 struct pipe_screen *pscreen = nv40->pipe.screen;
852 struct nouveau_grobj *curie = nv40->screen->curie;
853 struct nv40_vertex_program *vp;
854 struct pipe_buffer *constbuf;
855 boolean upload_code = FALSE, upload_data = FALSE;
856 int i;
857
858 if (nv40->render_mode == HW) {
859 vp = nv40->vertprog;
860 constbuf = nv40->constbuf[PIPE_SHADER_VERTEX];
861
862 if ((nv40->dirty & NV40_NEW_UCP) ||
863 memcmp(&nv40->clip, &vp->ucp, sizeof(vp->ucp))) {
864 nv40_vertprog_destroy(nv40, vp);
865 memcpy(&vp->ucp, &nv40->clip, sizeof(vp->ucp));
866 }
867 } else {
868 vp = nv40->swtnl.vertprog;
869 constbuf = NULL;
870 }
871
872 /* Translate TGSI shader into hw bytecode */
873 if (vp->translated)
874 goto check_gpu_resources;
875
876 nv40->fallback_swtnl &= ~NV40_NEW_VERTPROG;
877 nv40_vertprog_translate(nv40, vp);
878 if (!vp->translated) {
879 nv40->fallback_swtnl |= NV40_NEW_VERTPROG;
880 return FALSE;
881 }
882
883 check_gpu_resources:
884 /* Allocate hw vtxprog exec slots */
885 if (!vp->exec) {
886 struct nouveau_resource *heap = nv40->screen->vp_exec_heap;
887 struct nouveau_stateobj *so;
888 uint vplen = vp->nr_insns;
889
890 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
891 while (heap->next && heap->size < vplen) {
892 struct nv40_vertex_program *evict;
893
894 evict = heap->next->priv;
895 nouveau_resource_free(&evict->exec);
896 }
897
898 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
899 assert(0);
900 }
901
902 so = so_new(7, 0);
903 so_method(so, curie, NV40TCL_VP_START_FROM_ID, 1);
904 so_data (so, vp->exec->start);
905 so_method(so, curie, NV40TCL_VP_ATTRIB_EN, 2);
906 so_data (so, vp->ir);
907 so_data (so, vp->or);
908 so_method(so, curie, NV40TCL_CLIP_PLANE_ENABLE, 1);
909 so_data (so, vp->clip_ctrl);
910 so_ref(so, &vp->so);
911 so_ref(NULL, &so);
912
913 upload_code = TRUE;
914 }
915
916 /* Allocate hw vtxprog const slots */
917 if (vp->nr_consts && !vp->data) {
918 struct nouveau_resource *heap = nv40->screen->vp_data_heap;
919
920 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
921 while (heap->next && heap->size < vp->nr_consts) {
922 struct nv40_vertex_program *evict;
923
924 evict = heap->next->priv;
925 nouveau_resource_free(&evict->data);
926 }
927
928 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
929 assert(0);
930 }
931
932 /*XXX: handle this some day */
933 assert(vp->data->start >= vp->data_start_min);
934
935 upload_data = TRUE;
936 if (vp->data_start != vp->data->start)
937 upload_code = TRUE;
938 }
939
940 /* If exec or data segments moved we need to patch the program to
941 * fixup offsets and register IDs.
942 */
943 if (vp->exec_start != vp->exec->start) {
944 for (i = 0; i < vp->nr_insns; i++) {
945 struct nv40_vertex_program_exec *vpi = &vp->insns[i];
946
947 if (vpi->has_branch_offset) {
948 assert(0);
949 }
950 }
951
952 vp->exec_start = vp->exec->start;
953 }
954
955 if (vp->nr_consts && vp->data_start != vp->data->start) {
956 for (i = 0; i < vp->nr_insns; i++) {
957 struct nv40_vertex_program_exec *vpi = &vp->insns[i];
958
959 if (vpi->const_index >= 0) {
960 vpi->data[1] &= ~NV40_VP_INST_CONST_SRC_MASK;
961 vpi->data[1] |=
962 (vpi->const_index + vp->data->start) <<
963 NV40_VP_INST_CONST_SRC_SHIFT;
964
965 }
966 }
967
968 vp->data_start = vp->data->start;
969 }
970
971 /* Update + Upload constant values */
972 if (vp->nr_consts) {
973 float *map = NULL;
974
975 if (constbuf) {
976 map = pipe_buffer_map(pscreen, constbuf,
977 PIPE_BUFFER_USAGE_CPU_READ);
978 }
979
980 for (i = 0; i < vp->nr_consts; i++) {
981 struct nv40_vertex_program_data *vpd = &vp->consts[i];
982
983 if (vpd->index >= 0) {
984 if (!upload_data &&
985 !memcmp(vpd->value, &map[vpd->index * 4],
986 4 * sizeof(float)))
987 continue;
988 memcpy(vpd->value, &map[vpd->index * 4],
989 4 * sizeof(float));
990 }
991
992 BEGIN_RING(curie, NV40TCL_VP_UPLOAD_CONST_ID, 5);
993 OUT_RING (i + vp->data->start);
994 OUT_RINGp ((uint32_t *)vpd->value, 4);
995 }
996
997 if (constbuf)
998 pscreen->buffer_unmap(pscreen, constbuf);
999 }
1000
1001 /* Upload vtxprog */
1002 if (upload_code) {
1003 #if 0
1004 for (i = 0; i < vp->nr_insns; i++) {
1005 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
1006 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
1007 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
1008 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
1009 }
1010 #endif
1011 BEGIN_RING(curie, NV40TCL_VP_UPLOAD_FROM_ID, 1);
1012 OUT_RING (vp->exec->start);
1013 for (i = 0; i < vp->nr_insns; i++) {
1014 BEGIN_RING(curie, NV40TCL_VP_UPLOAD_INST(0), 4);
1015 OUT_RINGp (vp->insns[i].data, 4);
1016 }
1017 }
1018
1019 if (vp->so != nv40->state.hw[NV40_STATE_VERTPROG]) {
1020 so_ref(vp->so, &nv40->state.hw[NV40_STATE_VERTPROG]);
1021 return TRUE;
1022 }
1023
1024 return FALSE;
1025 }
1026
1027 void
1028 nv40_vertprog_destroy(struct nv40_context *nv40, struct nv40_vertex_program *vp)
1029 {
1030 vp->translated = FALSE;
1031
1032 if (vp->nr_insns) {
1033 FREE(vp->insns);
1034 vp->insns = NULL;
1035 vp->nr_insns = 0;
1036 }
1037
1038 if (vp->nr_consts) {
1039 FREE(vp->consts);
1040 vp->consts = NULL;
1041 vp->nr_consts = 0;
1042 }
1043
1044 nouveau_resource_free(&vp->exec);
1045 vp->exec_start = 0;
1046 nouveau_resource_free(&vp->data);
1047 vp->data_start = 0;
1048 vp->data_start_min = 0;
1049
1050 vp->ir = vp->or = vp->clip_ctrl = 0;
1051 so_ref(NULL, &vp->so);
1052 }
1053
1054 struct nv40_state_entry nv40_state_vertprog = {
1055 .validate = nv40_vertprog_validate,
1056 .dirty = {
1057 .pipe = NV40_NEW_VERTPROG | NV40_NEW_UCP,
1058 .hw = NV40_STATE_VERTPROG,
1059 }
1060 };
1061