1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
10 #include "nv40_context.h"
11 #include "nvfx_state.h"
13 /* TODO (at least...):
14 * 1. Indexed consts + ARL
15 * 3. NV_vp11, NV_vp2, NV_vp3 features
16 * - extra arith opcodes
32 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
35 #include "nv40_shader.h"
37 #define swz(s,x,y,z,w) nvfx_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
38 #define neg(s) nvfx_sr_neg((s))
39 #define abs(s) nvfx_sr_abs((s))
41 #define NV40_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
44 struct nvfx_vertex_program
*vp
;
46 struct nvfx_vertex_program_exec
*vpi
;
49 unsigned r_temps_discard
;
50 struct nvfx_sreg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
51 struct nvfx_sreg
*r_address
;
52 struct nvfx_sreg
*r_temp
;
54 struct nvfx_sreg
*imm
;
60 static struct nvfx_sreg
61 temp(struct nv40_vpc
*vpc
)
63 int idx
= ffs(~vpc
->r_temps
) - 1;
66 NOUVEAU_ERR("out of temps!!\n");
68 return nvfx_sr(NVFXSR_TEMP
, 0);
71 vpc
->r_temps
|= (1 << idx
);
72 vpc
->r_temps_discard
|= (1 << idx
);
73 return nvfx_sr(NVFXSR_TEMP
, idx
);
77 release_temps(struct nv40_vpc
*vpc
)
79 vpc
->r_temps
&= ~vpc
->r_temps_discard
;
80 vpc
->r_temps_discard
= 0;
83 static struct nvfx_sreg
84 constant(struct nv40_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
86 struct nvfx_vertex_program
*vp
= vpc
->vp
;
87 struct nvfx_vertex_program_data
*vpd
;
91 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
92 if (vp
->consts
[idx
].index
== pipe
)
93 return nvfx_sr(NVFXSR_CONST
, idx
);
97 idx
= vp
->nr_consts
++;
98 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
99 vpd
= &vp
->consts
[idx
];
106 return nvfx_sr(NVFXSR_CONST
, idx
);
109 #define arith(cc,s,o,d,m,s0,s1,s2) \
110 nv40_vp_arith((cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
113 emit_src(struct nv40_vpc
*vpc
, uint32_t *hw
, int pos
, struct nvfx_sreg src
)
115 struct nvfx_vertex_program
*vp
= vpc
->vp
;
120 sr
|= (NV40_VP_SRC_REG_TYPE_TEMP
<< NV40_VP_SRC_REG_TYPE_SHIFT
);
121 sr
|= (src
.index
<< NV40_VP_SRC_TEMP_SRC_SHIFT
);
124 sr
|= (NV40_VP_SRC_REG_TYPE_INPUT
<<
125 NV40_VP_SRC_REG_TYPE_SHIFT
);
126 vp
->ir
|= (1 << src
.index
);
127 hw
[1] |= (src
.index
<< NV40_VP_INST_INPUT_SRC_SHIFT
);
130 sr
|= (NV40_VP_SRC_REG_TYPE_CONST
<<
131 NV40_VP_SRC_REG_TYPE_SHIFT
);
132 assert(vpc
->vpi
->const_index
== -1 ||
133 vpc
->vpi
->const_index
== src
.index
);
134 vpc
->vpi
->const_index
= src
.index
;
137 sr
|= (NV40_VP_SRC_REG_TYPE_INPUT
<<
138 NV40_VP_SRC_REG_TYPE_SHIFT
);
145 sr
|= NV40_VP_SRC_NEGATE
;
148 hw
[0] |= (1 << (21 + pos
));
150 sr
|= ((src
.swz
[0] << NV40_VP_SRC_SWZ_X_SHIFT
) |
151 (src
.swz
[1] << NV40_VP_SRC_SWZ_Y_SHIFT
) |
152 (src
.swz
[2] << NV40_VP_SRC_SWZ_Z_SHIFT
) |
153 (src
.swz
[3] << NV40_VP_SRC_SWZ_W_SHIFT
));
157 hw
[1] |= ((sr
& NV40_VP_SRC0_HIGH_MASK
) >>
158 NV40_VP_SRC0_HIGH_SHIFT
) << NV40_VP_INST_SRC0H_SHIFT
;
159 hw
[2] |= (sr
& NV40_VP_SRC0_LOW_MASK
) <<
160 NV40_VP_INST_SRC0L_SHIFT
;
163 hw
[2] |= sr
<< NV40_VP_INST_SRC1_SHIFT
;
166 hw
[2] |= ((sr
& NV40_VP_SRC2_HIGH_MASK
) >>
167 NV40_VP_SRC2_HIGH_SHIFT
) << NV40_VP_INST_SRC2H_SHIFT
;
168 hw
[3] |= (sr
& NV40_VP_SRC2_LOW_MASK
) <<
169 NV40_VP_INST_SRC2L_SHIFT
;
177 emit_dst(struct nv40_vpc
*vpc
, uint32_t *hw
, int slot
, struct nvfx_sreg dst
)
179 struct nvfx_vertex_program
*vp
= vpc
->vp
;
183 hw
[3] |= NV40_VP_INST_DEST_MASK
;
185 hw
[0] |= (dst
.index
<<
186 NV40_VP_INST_VEC_DEST_TEMP_SHIFT
);
188 hw
[3] |= (dst
.index
<<
189 NV40_VP_INST_SCA_DEST_TEMP_SHIFT
);
194 case NV40_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
195 case NV40_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
196 case NV40_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
197 case NV40_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
198 case NV40_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
199 case NV40_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
200 case NV40_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
201 case NV40_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
202 case NV40_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
203 case NV40_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
204 case NV40_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
205 case NV40_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
206 case NV40_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
207 case NV40_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
208 case NV40_VP_INST_DEST_CLIP(0):
210 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0
;
211 dst
.index
= NV40_VP_INST_DEST_FOGC
;
213 case NV40_VP_INST_DEST_CLIP(1):
215 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1
;
216 dst
.index
= NV40_VP_INST_DEST_FOGC
;
218 case NV40_VP_INST_DEST_CLIP(2):
220 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2
;
221 dst
.index
= NV40_VP_INST_DEST_FOGC
;
223 case NV40_VP_INST_DEST_CLIP(3):
225 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3
;
226 dst
.index
= NV40_VP_INST_DEST_PSZ
;
228 case NV40_VP_INST_DEST_CLIP(4):
230 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4
;
231 dst
.index
= NV40_VP_INST_DEST_PSZ
;
233 case NV40_VP_INST_DEST_CLIP(5):
235 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5
;
236 dst
.index
= NV40_VP_INST_DEST_PSZ
;
242 hw
[3] |= (dst
.index
<< NV40_VP_INST_DEST_SHIFT
);
244 hw
[0] |= NV40_VP_INST_VEC_RESULT
;
245 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
| (1<<20);
247 hw
[3] |= NV40_VP_INST_SCA_RESULT
;
248 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
257 nv40_vp_arith(struct nv40_vpc
*vpc
, int slot
, int op
,
258 struct nvfx_sreg dst
, int mask
,
259 struct nvfx_sreg s0
, struct nvfx_sreg s1
,
262 struct nvfx_vertex_program
*vp
= vpc
->vp
;
265 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
266 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
267 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
268 vpc
->vpi
->const_index
= -1;
272 hw
[0] |= (NVFX_VP_INST_COND_TR
<< NV40_VP_INST_COND_SHIFT
);
273 hw
[0] |= ((0 << NV40_VP_INST_COND_SWZ_X_SHIFT
) |
274 (1 << NV40_VP_INST_COND_SWZ_Y_SHIFT
) |
275 (2 << NV40_VP_INST_COND_SWZ_Z_SHIFT
) |
276 (3 << NV40_VP_INST_COND_SWZ_W_SHIFT
));
279 hw
[1] |= (op
<< NV40_VP_INST_VEC_OPCODE_SHIFT
);
280 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
281 hw
[3] |= (mask
<< NV40_VP_INST_VEC_WRITEMASK_SHIFT
);
283 hw
[1] |= (op
<< NV40_VP_INST_SCA_OPCODE_SHIFT
);
284 hw
[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK
| (1 << 20));
285 hw
[3] |= (mask
<< NV40_VP_INST_SCA_WRITEMASK_SHIFT
);
288 emit_dst(vpc
, hw
, slot
, dst
);
289 emit_src(vpc
, hw
, 0, s0
);
290 emit_src(vpc
, hw
, 1, s1
);
291 emit_src(vpc
, hw
, 2, s2
);
294 static INLINE
struct nvfx_sreg
295 tgsi_src(struct nv40_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
296 struct nvfx_sreg src
;
298 switch (fsrc
->Register
.File
) {
299 case TGSI_FILE_INPUT
:
300 src
= nvfx_sr(NVFXSR_INPUT
, fsrc
->Register
.Index
);
302 case TGSI_FILE_CONSTANT
:
303 src
= constant(vpc
, fsrc
->Register
.Index
, 0, 0, 0, 0);
305 case TGSI_FILE_IMMEDIATE
:
306 src
= vpc
->imm
[fsrc
->Register
.Index
];
308 case TGSI_FILE_TEMPORARY
:
309 src
= vpc
->r_temp
[fsrc
->Register
.Index
];
312 NOUVEAU_ERR("bad src file\n");
316 src
.abs
= fsrc
->Register
.Absolute
;
317 src
.negate
= fsrc
->Register
.Negate
;
318 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
319 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
320 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
321 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
325 static INLINE
struct nvfx_sreg
326 tgsi_dst(struct nv40_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
327 struct nvfx_sreg dst
;
329 switch (fdst
->Register
.File
) {
330 case TGSI_FILE_OUTPUT
:
331 dst
= vpc
->r_result
[fdst
->Register
.Index
];
333 case TGSI_FILE_TEMPORARY
:
334 dst
= vpc
->r_temp
[fdst
->Register
.Index
];
336 case TGSI_FILE_ADDRESS
:
337 dst
= vpc
->r_address
[fdst
->Register
.Index
];
340 NOUVEAU_ERR("bad dst file\n");
352 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= MASK_X
;
353 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= MASK_Y
;
354 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= MASK_Z
;
355 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= MASK_W
;
360 src_native_swz(struct nv40_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
,
361 struct nvfx_sreg
*src
)
363 const struct nvfx_sreg none
= nvfx_sr(NVFXSR_NONE
, 0);
364 struct nvfx_sreg tgsi
= tgsi_src(vpc
, fsrc
);
368 for (c
= 0; c
< 4; c
++) {
369 switch (tgsi_util_get_full_src_register_swizzle(fsrc
, c
)) {
374 mask
|= tgsi_mask(1 << c
);
381 if (mask
== MASK_ALL
)
387 arith(vpc
, VEC
, MOV
, *src
, mask
, tgsi
, none
, none
);
393 nv40_vertprog_parse_instruction(struct nv40_vpc
*vpc
,
394 const struct tgsi_full_instruction
*finst
)
396 struct nvfx_sreg src
[3], dst
, tmp
;
397 struct nvfx_sreg none
= nvfx_sr(NVFXSR_NONE
, 0);
399 int ai
= -1, ci
= -1, ii
= -1;
402 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
405 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
406 const struct tgsi_full_src_register
*fsrc
;
408 fsrc
= &finst
->Src
[i
];
409 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
410 src
[i
] = tgsi_src(vpc
, fsrc
);
414 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
415 const struct tgsi_full_src_register
*fsrc
;
417 fsrc
= &finst
->Src
[i
];
419 switch (fsrc
->Register
.File
) {
420 case TGSI_FILE_INPUT
:
421 case TGSI_FILE_CONSTANT
:
422 case TGSI_FILE_TEMPORARY
:
423 if (!src_native_swz(vpc
, fsrc
, &src
[i
]))
430 switch (fsrc
->Register
.File
) {
431 case TGSI_FILE_INPUT
:
432 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
433 ai
= fsrc
->Register
.Index
;
434 src
[i
] = tgsi_src(vpc
, fsrc
);
437 arith(vpc
, VEC
, MOV
, src
[i
], MASK_ALL
,
438 tgsi_src(vpc
, fsrc
), none
, none
);
441 case TGSI_FILE_CONSTANT
:
442 if ((ci
== -1 && ii
== -1) ||
443 ci
== fsrc
->Register
.Index
) {
444 ci
= fsrc
->Register
.Index
;
445 src
[i
] = tgsi_src(vpc
, fsrc
);
448 arith(vpc
, VEC
, MOV
, src
[i
], MASK_ALL
,
449 tgsi_src(vpc
, fsrc
), none
, none
);
452 case TGSI_FILE_IMMEDIATE
:
453 if ((ci
== -1 && ii
== -1) ||
454 ii
== fsrc
->Register
.Index
) {
455 ii
= fsrc
->Register
.Index
;
456 src
[i
] = tgsi_src(vpc
, fsrc
);
459 arith(vpc
, VEC
, MOV
, src
[i
], MASK_ALL
,
460 tgsi_src(vpc
, fsrc
), none
, none
);
463 case TGSI_FILE_TEMPORARY
:
467 NOUVEAU_ERR("bad src file\n");
472 dst
= tgsi_dst(vpc
, &finst
->Dst
[0]);
473 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
475 switch (finst
->Instruction
.Opcode
) {
476 case TGSI_OPCODE_ABS
:
477 arith(vpc
, VEC
, MOV
, dst
, mask
, abs(src
[0]), none
, none
);
479 case TGSI_OPCODE_ADD
:
480 arith(vpc
, VEC
, ADD
, dst
, mask
, src
[0], none
, src
[1]);
482 case TGSI_OPCODE_ARL
:
483 arith(vpc
, VEC
, ARL
, dst
, mask
, src
[0], none
, none
);
485 case TGSI_OPCODE_DP3
:
486 arith(vpc
, VEC
, DP3
, dst
, mask
, src
[0], src
[1], none
);
488 case TGSI_OPCODE_DP4
:
489 arith(vpc
, VEC
, DP4
, dst
, mask
, src
[0], src
[1], none
);
491 case TGSI_OPCODE_DPH
:
492 arith(vpc
, VEC
, DPH
, dst
, mask
, src
[0], src
[1], none
);
494 case TGSI_OPCODE_DST
:
495 arith(vpc
, VEC
, DST
, dst
, mask
, src
[0], src
[1], none
);
497 case TGSI_OPCODE_EX2
:
498 arith(vpc
, SCA
, EX2
, dst
, mask
, none
, none
, src
[0]);
500 case TGSI_OPCODE_EXP
:
501 arith(vpc
, SCA
, EXP
, dst
, mask
, none
, none
, src
[0]);
503 case TGSI_OPCODE_FLR
:
504 arith(vpc
, VEC
, FLR
, dst
, mask
, src
[0], none
, none
);
506 case TGSI_OPCODE_FRC
:
507 arith(vpc
, VEC
, FRC
, dst
, mask
, src
[0], none
, none
);
509 case TGSI_OPCODE_LG2
:
510 arith(vpc
, SCA
, LG2
, dst
, mask
, none
, none
, src
[0]);
512 case TGSI_OPCODE_LIT
:
513 arith(vpc
, SCA
, LIT
, dst
, mask
, none
, none
, src
[0]);
515 case TGSI_OPCODE_LOG
:
516 arith(vpc
, SCA
, LOG
, dst
, mask
, none
, none
, src
[0]);
518 case TGSI_OPCODE_MAD
:
519 arith(vpc
, VEC
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]);
521 case TGSI_OPCODE_MAX
:
522 arith(vpc
, VEC
, MAX
, dst
, mask
, src
[0], src
[1], none
);
524 case TGSI_OPCODE_MIN
:
525 arith(vpc
, VEC
, MIN
, dst
, mask
, src
[0], src
[1], none
);
527 case TGSI_OPCODE_MOV
:
528 arith(vpc
, VEC
, MOV
, dst
, mask
, src
[0], none
, none
);
530 case TGSI_OPCODE_MUL
:
531 arith(vpc
, VEC
, MUL
, dst
, mask
, src
[0], src
[1], none
);
533 case TGSI_OPCODE_POW
:
535 arith(vpc
, SCA
, LG2
, tmp
, MASK_X
, none
, none
,
536 swz(src
[0], X
, X
, X
, X
));
537 arith(vpc
, VEC
, MUL
, tmp
, MASK_X
, swz(tmp
, X
, X
, X
, X
),
538 swz(src
[1], X
, X
, X
, X
), none
);
539 arith(vpc
, SCA
, EX2
, dst
, mask
, none
, none
,
540 swz(tmp
, X
, X
, X
, X
));
542 case TGSI_OPCODE_RCP
:
543 arith(vpc
, SCA
, RCP
, dst
, mask
, none
, none
, src
[0]);
545 case TGSI_OPCODE_RET
:
547 case TGSI_OPCODE_RSQ
:
548 arith(vpc
, SCA
, RSQ
, dst
, mask
, none
, none
, abs(src
[0]));
550 case TGSI_OPCODE_SGE
:
551 arith(vpc
, VEC
, SGE
, dst
, mask
, src
[0], src
[1], none
);
553 case TGSI_OPCODE_SLT
:
554 arith(vpc
, VEC
, SLT
, dst
, mask
, src
[0], src
[1], none
);
556 case TGSI_OPCODE_SUB
:
557 arith(vpc
, VEC
, ADD
, dst
, mask
, src
[0], none
, neg(src
[1]));
559 case TGSI_OPCODE_XPD
:
561 arith(vpc
, VEC
, MUL
, tmp
, mask
,
562 swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
);
563 arith(vpc
, VEC
, MAD
, dst
, (mask
& ~MASK_W
),
564 swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
),
568 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
577 nv40_vertprog_parse_decl_output(struct nv40_vpc
*vpc
,
578 const struct tgsi_full_declaration
*fdec
)
580 unsigned idx
= fdec
->Range
.First
;
583 switch (fdec
->Semantic
.Name
) {
584 case TGSI_SEMANTIC_POSITION
:
585 hw
= NV40_VP_INST_DEST_POS
;
588 case TGSI_SEMANTIC_COLOR
:
589 if (fdec
->Semantic
.Index
== 0) {
590 hw
= NV40_VP_INST_DEST_COL0
;
592 if (fdec
->Semantic
.Index
== 1) {
593 hw
= NV40_VP_INST_DEST_COL1
;
595 NOUVEAU_ERR("bad colour semantic index\n");
599 case TGSI_SEMANTIC_BCOLOR
:
600 if (fdec
->Semantic
.Index
== 0) {
601 hw
= NV40_VP_INST_DEST_BFC0
;
603 if (fdec
->Semantic
.Index
== 1) {
604 hw
= NV40_VP_INST_DEST_BFC1
;
606 NOUVEAU_ERR("bad bcolour semantic index\n");
610 case TGSI_SEMANTIC_FOG
:
611 hw
= NV40_VP_INST_DEST_FOGC
;
613 case TGSI_SEMANTIC_PSIZE
:
614 hw
= NV40_VP_INST_DEST_PSZ
;
616 case TGSI_SEMANTIC_GENERIC
:
617 if (fdec
->Semantic
.Index
<= 7) {
618 hw
= NV40_VP_INST_DEST_TC(fdec
->Semantic
.Index
);
620 NOUVEAU_ERR("bad generic semantic index\n");
624 case TGSI_SEMANTIC_EDGEFLAG
:
625 /* not really an error just a fallback */
626 NOUVEAU_ERR("cannot handle edgeflag output\n");
629 NOUVEAU_ERR("bad output semantic\n");
633 vpc
->r_result
[idx
] = nvfx_sr(NVFXSR_OUTPUT
, hw
);
638 nv40_vertprog_prepare(struct nv40_vpc
*vpc
)
640 struct tgsi_parse_context p
;
641 int high_temp
= -1, high_addr
= -1, nr_imm
= 0, i
;
643 tgsi_parse_init(&p
, vpc
->vp
->pipe
.tokens
);
644 while (!tgsi_parse_end_of_tokens(&p
)) {
645 const union tgsi_full_token
*tok
= &p
.FullToken
;
647 tgsi_parse_token(&p
);
648 switch(tok
->Token
.Type
) {
649 case TGSI_TOKEN_TYPE_IMMEDIATE
:
652 case TGSI_TOKEN_TYPE_DECLARATION
:
654 const struct tgsi_full_declaration
*fdec
;
656 fdec
= &p
.FullToken
.FullDeclaration
;
657 switch (fdec
->Declaration
.File
) {
658 case TGSI_FILE_TEMPORARY
:
659 if (fdec
->Range
.Last
> high_temp
) {
664 #if 0 /* this would be nice.. except gallium doesn't track it */
665 case TGSI_FILE_ADDRESS
:
666 if (fdec
->Range
.Last
> high_addr
) {
672 case TGSI_FILE_OUTPUT
:
673 if (!nv40_vertprog_parse_decl_output(vpc
, fdec
))
681 #if 1 /* yay, parse instructions looking for address regs instead */
682 case TGSI_TOKEN_TYPE_INSTRUCTION
:
684 const struct tgsi_full_instruction
*finst
;
685 const struct tgsi_full_dst_register
*fdst
;
687 finst
= &p
.FullToken
.FullInstruction
;
688 fdst
= &finst
->Dst
[0];
690 if (fdst
->Register
.File
== TGSI_FILE_ADDRESS
) {
691 if (fdst
->Register
.Index
> high_addr
)
692 high_addr
= fdst
->Register
.Index
;
705 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nvfx_sreg
));
710 vpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_sreg
));
711 for (i
= 0; i
< high_temp
; i
++)
712 vpc
->r_temp
[i
] = temp(vpc
);
716 vpc
->r_address
= CALLOC(high_addr
, sizeof(struct nvfx_sreg
));
717 for (i
= 0; i
< high_addr
; i
++)
718 vpc
->r_address
[i
] = temp(vpc
);
721 vpc
->r_temps_discard
= 0;
726 nv40_vertprog_translate(struct nvfx_context
*nvfx
,
727 struct nvfx_vertex_program
*vp
)
729 struct tgsi_parse_context parse
;
730 struct nv40_vpc
*vpc
= NULL
;
731 struct nvfx_sreg none
= nvfx_sr(NVFXSR_NONE
, 0);
734 vpc
= CALLOC(1, sizeof(struct nv40_vpc
));
739 if (!nv40_vertprog_prepare(vpc
)) {
744 /* Redirect post-transform vertex position to a temp if user clip
745 * planes are enabled. We need to append code to the vtxprog
746 * to handle clip planes later.
749 vpc
->r_result
[vpc
->hpos_idx
] = temp(vpc
);
750 vpc
->r_temps_discard
= 0;
753 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
755 while (!tgsi_parse_end_of_tokens(&parse
)) {
756 tgsi_parse_token(&parse
);
758 switch (parse
.FullToken
.Token
.Type
) {
759 case TGSI_TOKEN_TYPE_IMMEDIATE
:
761 const struct tgsi_full_immediate
*imm
;
763 imm
= &parse
.FullToken
.FullImmediate
;
764 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
765 assert(imm
->Immediate
.NrTokens
== 4 + 1);
766 vpc
->imm
[vpc
->nr_imm
++] =
774 case TGSI_TOKEN_TYPE_INSTRUCTION
:
776 const struct tgsi_full_instruction
*finst
;
777 finst
= &parse
.FullToken
.FullInstruction
;
778 if (!nv40_vertprog_parse_instruction(vpc
, finst
))
787 /* Write out HPOS if it was redirected to a temp earlier */
788 if (vpc
->r_result
[vpc
->hpos_idx
].type
!= NVFXSR_OUTPUT
) {
789 struct nvfx_sreg hpos
= nvfx_sr(NVFXSR_OUTPUT
,
790 NV40_VP_INST_DEST_POS
);
791 struct nvfx_sreg htmp
= vpc
->r_result
[vpc
->hpos_idx
];
793 arith(vpc
, VEC
, MOV
, hpos
, MASK_ALL
, htmp
, none
, none
);
796 /* Insert code to handle user clip planes */
797 for (i
= 0; i
< vp
->ucp
.nr
; i
++) {
798 struct nvfx_sreg cdst
= nvfx_sr(NVFXSR_OUTPUT
,
799 NV40_VP_INST_DEST_CLIP(i
));
800 struct nvfx_sreg ceqn
= constant(vpc
, -1,
801 nvfx
->clip
.ucp
[i
][0],
802 nvfx
->clip
.ucp
[i
][1],
803 nvfx
->clip
.ucp
[i
][2],
804 nvfx
->clip
.ucp
[i
][3]);
805 struct nvfx_sreg htmp
= vpc
->r_result
[vpc
->hpos_idx
];
809 case 0: case 3: mask
= MASK_Y
; break;
810 case 1: case 4: mask
= MASK_Z
; break;
811 case 2: case 5: mask
= MASK_W
; break;
813 NOUVEAU_ERR("invalid clip dist #%d\n", i
);
817 arith(vpc
, VEC
, DP4
, cdst
, mask
, htmp
, ceqn
, none
);
820 vp
->insns
[vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
821 vp
->translated
= TRUE
;
823 tgsi_parse_free(&parse
);
827 FREE(vpc
->r_address
);
834 nv40_vertprog_validate(struct nvfx_context
*nvfx
)
836 struct pipe_screen
*pscreen
= nvfx
->pipe
.screen
;
837 struct nvfx_screen
*screen
= nvfx
->screen
;
838 struct nouveau_channel
*chan
= screen
->base
.channel
;
839 struct nouveau_grobj
*eng3d
= screen
->eng3d
;
840 struct nvfx_vertex_program
*vp
;
841 struct pipe_buffer
*constbuf
;
842 boolean upload_code
= FALSE
, upload_data
= FALSE
;
845 if (nvfx
->render_mode
== HW
) {
847 constbuf
= nvfx
->constbuf
[PIPE_SHADER_VERTEX
];
849 if ((nvfx
->dirty
& NVFX_NEW_UCP
) ||
850 memcmp(&nvfx
->clip
, &vp
->ucp
, sizeof(vp
->ucp
))) {
851 nv40_vertprog_destroy(nvfx
, vp
);
852 memcpy(&vp
->ucp
, &nvfx
->clip
, sizeof(vp
->ucp
));
855 vp
= nvfx
->swtnl
.vertprog
;
859 /* Translate TGSI shader into hw bytecode */
861 goto check_gpu_resources
;
863 nvfx
->fallback_swtnl
&= ~NVFX_NEW_VERTPROG
;
864 nv40_vertprog_translate(nvfx
, vp
);
865 if (!vp
->translated
) {
866 nvfx
->fallback_swtnl
|= NVFX_NEW_VERTPROG
;
871 /* Allocate hw vtxprog exec slots */
873 struct nouveau_resource
*heap
= nvfx
->screen
->vp_exec_heap
;
874 struct nouveau_stateobj
*so
;
875 uint vplen
= vp
->nr_insns
;
877 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
)) {
878 while (heap
->next
&& heap
->size
< vplen
) {
879 struct nvfx_vertex_program
*evict
;
881 evict
= heap
->next
->priv
;
882 nouveau_resource_free(&evict
->exec
);
885 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
))
889 so
= so_new(3, 4, 0);
890 so_method(so
, eng3d
, NV34TCL_VP_START_FROM_ID
, 1);
891 so_data (so
, vp
->exec
->start
);
892 so_method(so
, eng3d
, NV40TCL_VP_ATTRIB_EN
, 2);
893 so_data (so
, vp
->ir
);
894 so_data (so
, vp
->or);
895 so_method(so
, eng3d
, NV34TCL_VP_CLIP_PLANES_ENABLE
, 1);
896 so_data (so
, vp
->clip_ctrl
);
903 /* Allocate hw vtxprog const slots */
904 if (vp
->nr_consts
&& !vp
->data
) {
905 struct nouveau_resource
*heap
= nvfx
->screen
->vp_data_heap
;
907 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
)) {
908 while (heap
->next
&& heap
->size
< vp
->nr_consts
) {
909 struct nvfx_vertex_program
*evict
;
911 evict
= heap
->next
->priv
;
912 nouveau_resource_free(&evict
->data
);
915 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
))
919 /*XXX: handle this some day */
920 assert(vp
->data
->start
>= vp
->data_start_min
);
923 if (vp
->data_start
!= vp
->data
->start
)
927 /* If exec or data segments moved we need to patch the program to
928 * fixup offsets and register IDs.
930 if (vp
->exec_start
!= vp
->exec
->start
) {
931 for (i
= 0; i
< vp
->nr_insns
; i
++) {
932 struct nvfx_vertex_program_exec
*vpi
= &vp
->insns
[i
];
934 if (vpi
->has_branch_offset
) {
939 vp
->exec_start
= vp
->exec
->start
;
942 if (vp
->nr_consts
&& vp
->data_start
!= vp
->data
->start
) {
943 for (i
= 0; i
< vp
->nr_insns
; i
++) {
944 struct nvfx_vertex_program_exec
*vpi
= &vp
->insns
[i
];
946 if (vpi
->const_index
>= 0) {
947 vpi
->data
[1] &= ~NV40_VP_INST_CONST_SRC_MASK
;
949 (vpi
->const_index
+ vp
->data
->start
) <<
950 NV40_VP_INST_CONST_SRC_SHIFT
;
955 vp
->data_start
= vp
->data
->start
;
958 /* Update + Upload constant values */
963 map
= pipe_buffer_map(pscreen
, constbuf
,
964 PIPE_BUFFER_USAGE_CPU_READ
);
967 for (i
= 0; i
< vp
->nr_consts
; i
++) {
968 struct nvfx_vertex_program_data
*vpd
= &vp
->consts
[i
];
970 if (vpd
->index
>= 0) {
972 !memcmp(vpd
->value
, &map
[vpd
->index
* 4],
975 memcpy(vpd
->value
, &map
[vpd
->index
* 4],
979 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_CONST_ID
, 5);
980 OUT_RING (chan
, i
+ vp
->data
->start
);
981 OUT_RINGp (chan
, (uint32_t *)vpd
->value
, 4);
985 pscreen
->buffer_unmap(pscreen
, constbuf
);
991 for (i
= 0; i
< vp
->nr_insns
; i
++) {
992 NOUVEAU_MSG("VP %d: 0x%08x\n", i
, vp
->insns
[i
].data
[0]);
993 NOUVEAU_MSG("VP %d: 0x%08x\n", i
, vp
->insns
[i
].data
[1]);
994 NOUVEAU_MSG("VP %d: 0x%08x\n", i
, vp
->insns
[i
].data
[2]);
995 NOUVEAU_MSG("VP %d: 0x%08x\n", i
, vp
->insns
[i
].data
[3]);
998 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_FROM_ID
, 1);
999 OUT_RING (chan
, vp
->exec
->start
);
1000 for (i
= 0; i
< vp
->nr_insns
; i
++) {
1001 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_INST(0), 4);
1002 OUT_RINGp (chan
, vp
->insns
[i
].data
, 4);
1006 if (vp
->so
!= nvfx
->state
.hw
[NVFX_STATE_VERTPROG
]) {
1007 so_ref(vp
->so
, &nvfx
->state
.hw
[NVFX_STATE_VERTPROG
]);
1015 nv40_vertprog_destroy(struct nvfx_context
*nvfx
, struct nvfx_vertex_program
*vp
)
1017 vp
->translated
= FALSE
;
1025 if (vp
->nr_consts
) {
1031 nouveau_resource_free(&vp
->exec
);
1033 nouveau_resource_free(&vp
->data
);
1035 vp
->data_start_min
= 0;
1037 vp
->ir
= vp
->or = vp
->clip_ctrl
= 0;
1038 so_ref(NULL
, &vp
->so
);
1041 struct nvfx_state_entry nv40_state_vertprog
= {
1042 .validate
= nv40_vertprog_validate
,
1044 .pipe
= NVFX_NEW_VERTPROG
| NVFX_NEW_UCP
,
1045 .hw
= NVFX_STATE_VERTPROG
,