src/gallium/drivers/nv50/codegen/nv50_ir_driver.h

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #ifndef __NV50_IR_DRIVER_H__
  24 #define __NV50_IR_DRIVER_H__
  25
  26 #include "pipe/p_shader_tokens.h"
  27
  28 #include "tgsi/tgsi_util.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_scan.h"
  31
  32 /*
  33  * This struct constitutes linkage information in TGSI terminology.
  34  *
  35  * It is created by the code generator and handed to the pipe driver
  36  * for input/output slot assignment.
  37  */
  38 struct nv50_ir_varying
  39 {
  40    uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */
  41
  42    unsigned mask     : 4; /* vec4 mask */
  43    unsigned linear   : 1; /* linearly interpolated if true (and not flat) */
  44    unsigned flat     : 1;
  45    unsigned sc       : 1; /* special colour interpolation mode (SHADE_MODEL) */
  46    unsigned centroid : 1;
  47    unsigned patch    : 1; /* patch constant value */
  48    unsigned regular  : 1; /* driver-specific meaning (e.g. input in sreg) */
  49    unsigned input    : 1; /* indicates direction of system values */
  50    unsigned oread    : 1; /* true if output is read from parallel TCP */
  51
  52    ubyte id; /* TGSI register index */
  53    ubyte sn; /* TGSI semantic name */
  54    ubyte si; /* TGSI semantic index */
  55 };
  56
  57 #define NV50_PROGRAM_IR_TGSI 0
  58 #define NV50_PROGRAM_IR_SM4  1
  59 #define NV50_PROGRAM_IR_GLSL 2
  60 #define NV50_PROGRAM_IR_LLVM 3
  61
  62 #ifdef DEBUG
  63 # define NV50_IR_DEBUG_BASIC     (1 << 0)
  64 # define NV50_IR_DEBUG_VERBOSE   (2 << 0)
  65 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
  66 #else
  67 # define NV50_IR_DEBUG_BASIC     0
  68 # define NV50_IR_DEBUG_VERBOSE   0
  69 # define NV50_IR_DEBUG_REG_ALLOC 0
  70 #endif
  71
  72 #define NV50_SEMANTIC_CLIPDISTANCE  (TGSI_SEMANTIC_COUNT + 0)
  73 #define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4)
  74 #define NV50_SEMANTIC_LAYER         (TGSI_SEMANTIC_COUNT + 5)
  75 #define NV50_SEMANTIC_INVOCATIONID  (TGSI_SEMANTIC_COUNT + 6)
  76 #define NV50_SEMANTIC_TESSFACTOR    (TGSI_SEMANTIC_COUNT + 7)
  77 #define NV50_SEMANTIC_TESSCOORD     (TGSI_SEMANTIC_COUNT + 8)
  78 #define NV50_SEMANTIC_SAMPLEMASK    (TGSI_SEMANTIC_COUNT + 9)
  79 #define NV50_SEMANTIC_COUNT         (TGSI_SEMANTIC_COUNT + 10)
  80
  81 #define NV50_TESS_PART_FRACT_ODD  0
  82 #define NV50_TESS_PART_FRACT_EVEN 1
  83 #define NV50_TESS_PART_POW2       2
  84 #define NV50_TESS_PART_INTEGER    3
  85
  86 #define NV50_PRIM_PATCHES PIPE_PRIM_MAX
  87
  88 struct nv50_ir_prog_symbol
  89 {
  90    uint32_t label;
  91    uint32_t offset;
  92 };
  93
  94 #define NVISA_GF100_CHIPSET_C0 0xc0
  95 #define NVISA_GF100_CHIPSET_D0 0xd0
  96 #define NVISA_GK104_CHIPSET    0xe0
  97 #define NVISA_GK110_CHIPSET    0xf0
  98
  99 struct nv50_ir_prog_info
 100 {
 101    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
 102
 103    uint8_t type; /* PIPE_SHADER */
 104
 105    uint8_t optLevel; /* optimization level (0 to 3) */
 106    uint8_t dbgFlags;
 107
 108    struct {
 109       int16_t maxGPR;     /* may be -1 if none used */
 110       int16_t maxOutput;
 111       uint32_t tlsSpace;  /* required local memory per thread */
 112       uint32_t *code;
 113       uint32_t codeSize;
 114       uint8_t sourceRep;  /* NV50_PROGRAM_IR */
 115       const void *source;
 116       void *relocData;
 117       struct nv50_ir_prog_symbol *syms;
 118       uint16_t numSyms;
 119    } bin;
 120
 121    struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
 122    struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS];
 123    struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS];
 124    uint8_t numInputs;
 125    uint8_t numOutputs;
 126    uint8_t numPatchConstants; /* also included in numInputs/numOutputs */
 127    uint8_t numSysVals;
 128
 129    struct {
 130       uint32_t *buf;    /* for IMMEDIATE_ARRAY */
 131       uint16_t bufSize; /* size of immediate array */
 132       uint16_t count;   /* count of inline immediates */
 133       uint32_t *data;   /* inline immediate data */
 134       uint8_t *type;    /* for each vec4 (128 bit) */
 135    } immd;
 136
 137    union {
 138       struct {
 139          uint32_t inputMask[4]; /* mask of attributes read (1 bit per scalar) */
 140       } vp;
 141       struct {
 142          uint8_t inputPatchSize;
 143          uint8_t outputPatchSize;
 144          uint8_t partitioning;    /* PIPE_TESS_PART */
 145          int8_t winding;          /* +1 (clockwise) / -1 (counter-clockwise) */
 146          uint8_t domain;          /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */
 147          uint8_t outputPrim;      /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */
 148       } tp;
 149       struct {
 150          uint8_t inputPrim;
 151          uint8_t outputPrim;
 152          unsigned instanceCount;
 153          unsigned maxVertices;
 154       } gp;
 155       struct {
 156          unsigned numColourResults;
 157          boolean writesDepth;
 158          boolean earlyFragTests;
 159          boolean separateFragData;
 160          boolean usesDiscard;
 161       } fp;
 162       struct {
 163          uint32_t inputOffset; /* base address for user args */
 164          uint32_t sharedOffset; /* reserved space in s[] */
 165          uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
 166       } cp;
 167    } prop;
 168
 169    uint8_t numBarriers;
 170
 171    struct {
 172       uint8_t clipDistance;      /* index of first clip distance output */
 173       uint8_t clipDistanceMask;  /* mask of clip distances defined */
 174       uint8_t cullDistanceMask;  /* clip distance mode (1 bit per output) */
 175       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 176       uint16_t ucpBase;          /* base address for UCPs */
 177       uint8_t ucpCBSlot;         /* constant buffer index of UCP data */
 178       uint8_t pointSize;         /* output index for PointSize */
 179       uint8_t instanceId;        /* system value index of InstanceID */
 180       uint8_t vertexId;          /* system value index of VertexID */
 181       uint8_t edgeFlagIn;
 182       uint8_t edgeFlagOut;
 183       uint8_t fragDepth;         /* output index of FragDepth */
 184       uint8_t sampleMask;        /* output index of SampleMask */
 185       uint8_t backFaceColor[2];  /* input/output indices of back face colour */
 186       uint8_t globalAccess;      /* 1 for read, 2 for wr, 3 for rw */
 187       boolean nv50styleSurfaces; /* generate gX[] access for raw buffers */
 188       uint8_t resInfoCBSlot;     /* cX[] used for tex handles, surface info */
 189       uint16_t texBindBase;      /* base address for tex handles (nve4) */
 190       uint16_t suInfoBase;       /* base address for surface info (nve4) */
 191       uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
 192       uint16_t msInfoBase;       /* base address for multisample info */
 193    } io;
 194
 195    /* driver callback to assign input/output locations */
 196    int (*assignSlots)(struct nv50_ir_prog_info *);
 197
 198    void *driverPriv;
 199 };
 200
 201 #ifdef __cplusplus
 202 extern "C" {
 203 #endif
 204
 205 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *);
 206
 207 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
 208                                   uint32_t codePos,
 209                                   uint32_t libPos,
 210                                   uint32_t dataPos);
 211
 212 /* obtain code that will be shared among programs */
 213 extern void nv50_ir_get_target_library(uint32_t chipset,
 214                                        const uint32_t **code, uint32_t *size);
 215
 216 #ifdef __cplusplus
 217 }
 218 #endif
 219
 220 #endif // __NV50_IR_DRIVER_H__