src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 extern "C" {
  24 #include "tgsi/tgsi_dump.h"
  25 #include "tgsi/tgsi_scan.h"
  26 }
  27
  28 #include "nv50_ir.h"
  29 #include "nv50_ir_util.h"
  30 #include "nv50_ir_build_util.h"
  31
  32 namespace tgsi {
  33
  34 class Source;
  35
  36 static nv50_ir::operation translateOpcode(uint opcode);
  37 static nv50_ir::DataFile translateFile(uint file);
  38 static nv50_ir::TexTarget translateTexture(uint texTarg);
  39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  40
  41 class Instruction
  42 {
  43 public:
  44    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  45
  46    class SrcRegister
  47    {
  48    public:
  49       SrcRegister(const struct tgsi_full_src_register *src)
  50          : reg(src->Register),
  51            fsr(src)
  52       { }
  53
  54       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  55
  56       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  57       {
  58          struct tgsi_src_register reg;
  59          memset(&reg, 0, sizeof(reg));
  60          reg.Index = off.Index;
  61          reg.File = off.File;
  62          reg.SwizzleX = off.SwizzleX;
  63          reg.SwizzleY = off.SwizzleY;
  64          reg.SwizzleZ = off.SwizzleZ;
  65          return reg;
  66       }
  67
  68       SrcRegister(const struct tgsi_texture_offset& off) :
  69          reg(offsetToSrc(off)),
  70          fsr(NULL)
  71       { }
  72
  73       uint getFile() const { return reg.File; }
  74
  75       bool is2D() const { return reg.Dimension; }
  76
  77       bool isIndirect(int dim) const
  78       {
  79          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  80       }
  81
  82       int getIndex(int dim) const
  83       {
  84          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  85       }
  86
  87       int getSwizzle(int chan) const
  88       {
  89          return tgsi_util_get_src_register_swizzle(&reg, chan);
  90       }
  91
  92       nv50_ir::Modifier getMod(int chan) const;
  93
  94       SrcRegister getIndirect(int dim) const
  95       {
  96          assert(fsr && isIndirect(dim));
  97          if (dim)
  98             return SrcRegister(fsr->DimIndirect);
  99          return SrcRegister(fsr->Indirect);
 100       }
 101
 102       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 103       {
 104          assert(reg.File == TGSI_FILE_IMMEDIATE);
 105          assert(!reg.Absolute);
 106          assert(!reg.Negate);
 107          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 108       }
 109
 110    private:
 111       const struct tgsi_src_register reg;
 112       const struct tgsi_full_src_register *fsr;
 113    };
 114
 115    class DstRegister
 116    {
 117    public:
 118       DstRegister(const struct tgsi_full_dst_register *dst)
 119          : reg(dst->Register),
 120            fdr(dst)
 121       { }
 122
 123       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 124
 125       uint getFile() const { return reg.File; }
 126
 127       bool is2D() const { return reg.Dimension; }
 128
 129       bool isIndirect(int dim) const
 130       {
 131          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 132       }
 133
 134       int getIndex(int dim) const
 135       {
 136          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 137       }
 138
 139       unsigned int getMask() const { return reg.WriteMask; }
 140
 141       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 142
 143       SrcRegister getIndirect(int dim) const
 144       {
 145          assert(fdr && isIndirect(dim));
 146          if (dim)
 147             return SrcRegister(fdr->DimIndirect);
 148          return SrcRegister(fdr->Indirect);
 149       }
 150
 151    private:
 152       const struct tgsi_dst_register reg;
 153       const struct tgsi_full_dst_register *fdr;
 154    };
 155
 156    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 157
 158    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 159    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 160
 161    // mask of used components of source s
 162    unsigned int srcMask(unsigned int s) const;
 163
 164    SrcRegister getSrc(unsigned int s) const
 165    {
 166       assert(s < srcCount());
 167       return SrcRegister(&insn->Src[s]);
 168    }
 169
 170    DstRegister getDst(unsigned int d) const
 171    {
 172       assert(d < dstCount());
 173       return DstRegister(&insn->Dst[d]);
 174    }
 175
 176    SrcRegister getTexOffset(unsigned int i) const
 177    {
 178       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 179       return SrcRegister(insn->TexOffsets[i]);
 180    }
 181
 182    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 183
 184    bool checkDstSrcAliasing() const;
 185
 186    inline nv50_ir::operation getOP() const {
 187       return translateOpcode(getOpcode()); }
 188
 189    nv50_ir::DataType inferSrcType() const;
 190    nv50_ir::DataType inferDstType() const;
 191
 192    nv50_ir::CondCode getSetCond() const;
 193
 194    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 195
 196    inline uint getLabel() { return insn->Label.Label; }
 197
 198    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 199
 200    void print() const
 201    {
 202       tgsi_dump_instruction(insn, 1);
 203    }
 204
 205 private:
 206    const struct tgsi_full_instruction *insn;
 207 };
 208
 209 unsigned int Instruction::srcMask(unsigned int s) const
 210 {
 211    unsigned int mask = insn->Dst[0].Register.WriteMask;
 212
 213    switch (insn->Instruction.Opcode) {
 214    case TGSI_OPCODE_COS:
 215    case TGSI_OPCODE_SIN:
 216       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 217    case TGSI_OPCODE_DP3:
 218       return 0x7;
 219    case TGSI_OPCODE_DP4:
 220    case TGSI_OPCODE_DPH:
 221    case TGSI_OPCODE_KIL: /* WriteMask ignored */
 222       return 0xf;
 223    case TGSI_OPCODE_DST:
 224       return mask & (s ? 0xa : 0x6);
 225    case TGSI_OPCODE_EX2:
 226    case TGSI_OPCODE_EXP:
 227    case TGSI_OPCODE_LG2:
 228    case TGSI_OPCODE_LOG:
 229    case TGSI_OPCODE_POW:
 230    case TGSI_OPCODE_RCP:
 231    case TGSI_OPCODE_RSQ:
 232    case TGSI_OPCODE_SCS:
 233       return 0x1;
 234    case TGSI_OPCODE_IF:
 235       return 0x1;
 236    case TGSI_OPCODE_LIT:
 237       return 0xb;
 238    case TGSI_OPCODE_TEX:
 239    case TGSI_OPCODE_TXB:
 240    case TGSI_OPCODE_TXD:
 241    case TGSI_OPCODE_TXL:
 242    case TGSI_OPCODE_TXP:
 243    {
 244       const struct tgsi_instruction_texture *tex = &insn->Texture;
 245
 246       assert(insn->Instruction.Texture);
 247
 248       mask = 0x7;
 249       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 250           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 251          mask |= 0x8; /* bias, lod or proj */
 252
 253       switch (tex->Texture) {
 254       case TGSI_TEXTURE_1D:
 255          mask &= 0x9;
 256          break;
 257       case TGSI_TEXTURE_SHADOW1D:
 258          mask &= 0x5;
 259          break;
 260       case TGSI_TEXTURE_1D_ARRAY:
 261       case TGSI_TEXTURE_2D:
 262       case TGSI_TEXTURE_RECT:
 263          mask &= 0xb;
 264          break;
 265       default:
 266          break;
 267       }
 268    }
 269       return mask;
 270    case TGSI_OPCODE_XPD:
 271    {
 272       unsigned int x = 0;
 273       if (mask & 1) x |= 0x6;
 274       if (mask & 2) x |= 0x5;
 275       if (mask & 4) x |= 0x3;
 276       return x;
 277    }
 278    default:
 279       break;
 280    }
 281
 282    return mask;
 283 }
 284
 285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 286 {
 287    nv50_ir::Modifier m(0);
 288
 289    if (reg.Absolute)
 290       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 291    if (reg.Negate)
 292       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 293    return m;
 294 }
 295
 296 static nv50_ir::DataFile translateFile(uint file)
 297 {
 298    switch (file) {
 299    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 300    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 301    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 302    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 303    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 304    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 305    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 306    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 307    case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
 308    case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
 309    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 310    case TGSI_FILE_SAMPLER:
 311    case TGSI_FILE_NULL:
 312    default:
 313       return nv50_ir::FILE_NULL;
 314    }
 315 }
 316
 317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 318 {
 319    switch (sysval) {
 320    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 321    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 322    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 323    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 324    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 325    default:
 326       assert(0);
 327       return nv50_ir::SV_CLOCK;
 328    }
 329 }
 330
 331 #define NV50_IR_TEX_TARG_CASE(a, b) \
 332    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 333
 334 static nv50_ir::TexTarget translateTexture(uint tex)
 335 {
 336    switch (tex) {
 337    NV50_IR_TEX_TARG_CASE(1D, 1D);
 338    NV50_IR_TEX_TARG_CASE(2D, 2D);
 339    NV50_IR_TEX_TARG_CASE(3D, 3D);
 340    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 341    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 342    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 343    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 344    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 345    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 346    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 347    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 348    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 349    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 350
 351    case TGSI_TEXTURE_UNKNOWN:
 352    default:
 353       assert(!"invalid texture target");
 354       return nv50_ir::TEX_TARGET_2D;
 355    }
 356 }
 357
 358 nv50_ir::DataType Instruction::inferSrcType() const
 359 {
 360    switch (getOpcode()) {
 361    case TGSI_OPCODE_AND:
 362    case TGSI_OPCODE_OR:
 363    case TGSI_OPCODE_XOR:
 364    case TGSI_OPCODE_NOT:
 365    case TGSI_OPCODE_U2F:
 366    case TGSI_OPCODE_UADD:
 367    case TGSI_OPCODE_UDIV:
 368    case TGSI_OPCODE_UMOD:
 369    case TGSI_OPCODE_UMAD:
 370    case TGSI_OPCODE_UMUL:
 371    case TGSI_OPCODE_UMAX:
 372    case TGSI_OPCODE_UMIN:
 373    case TGSI_OPCODE_USEQ:
 374    case TGSI_OPCODE_USGE:
 375    case TGSI_OPCODE_USLT:
 376    case TGSI_OPCODE_USNE:
 377    case TGSI_OPCODE_USHR:
 378    case TGSI_OPCODE_UCMP:
 379       return nv50_ir::TYPE_U32;
 380    case TGSI_OPCODE_I2F:
 381    case TGSI_OPCODE_IDIV:
 382    case TGSI_OPCODE_IMAX:
 383    case TGSI_OPCODE_IMIN:
 384    case TGSI_OPCODE_IABS:
 385    case TGSI_OPCODE_INEG:
 386    case TGSI_OPCODE_ISGE:
 387    case TGSI_OPCODE_ISHR:
 388    case TGSI_OPCODE_ISLT:
 389    case TGSI_OPCODE_ISSG:
 390    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 391    case TGSI_OPCODE_MOD:
 392    case TGSI_OPCODE_UARL:
 393       return nv50_ir::TYPE_S32;
 394    default:
 395       return nv50_ir::TYPE_F32;
 396    }
 397 }
 398
 399 nv50_ir::DataType Instruction::inferDstType() const
 400 {
 401    switch (getOpcode()) {
 402    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 403    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 404    case TGSI_OPCODE_I2F:
 405    case TGSI_OPCODE_U2F:
 406       return nv50_ir::TYPE_F32;
 407    default:
 408       return inferSrcType();
 409    }
 410 }
 411
 412 nv50_ir::CondCode Instruction::getSetCond() const
 413 {
 414    using namespace nv50_ir;
 415
 416    switch (getOpcode()) {
 417    case TGSI_OPCODE_SLT:
 418    case TGSI_OPCODE_ISLT:
 419    case TGSI_OPCODE_USLT:
 420       return CC_LT;
 421    case TGSI_OPCODE_SLE:
 422       return CC_LE;
 423    case TGSI_OPCODE_SGE:
 424    case TGSI_OPCODE_ISGE:
 425    case TGSI_OPCODE_USGE:
 426       return CC_GE;
 427    case TGSI_OPCODE_SGT:
 428       return CC_GT;
 429    case TGSI_OPCODE_SEQ:
 430    case TGSI_OPCODE_USEQ:
 431       return CC_EQ;
 432    case TGSI_OPCODE_SNE:
 433       return CC_NEU;
 434    case TGSI_OPCODE_USNE:
 435       return CC_NE;
 436    case TGSI_OPCODE_SFL:
 437       return CC_NEVER;
 438    case TGSI_OPCODE_STR:
 439    default:
 440       return CC_ALWAYS;
 441    }
 442 }
 443
 444 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 445
 446 static nv50_ir::operation translateOpcode(uint opcode)
 447 {
 448    switch (opcode) {
 449    NV50_IR_OPCODE_CASE(ARL, SHL);
 450    NV50_IR_OPCODE_CASE(MOV, MOV);
 451
 452    NV50_IR_OPCODE_CASE(RCP, RCP);
 453    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 454
 455    NV50_IR_OPCODE_CASE(MUL, MUL);
 456    NV50_IR_OPCODE_CASE(ADD, ADD);
 457
 458    NV50_IR_OPCODE_CASE(MIN, MIN);
 459    NV50_IR_OPCODE_CASE(MAX, MAX);
 460    NV50_IR_OPCODE_CASE(SLT, SET);
 461    NV50_IR_OPCODE_CASE(SGE, SET);
 462    NV50_IR_OPCODE_CASE(MAD, MAD);
 463    NV50_IR_OPCODE_CASE(SUB, SUB);
 464
 465    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 466    NV50_IR_OPCODE_CASE(ROUND, CVT);
 467    NV50_IR_OPCODE_CASE(EX2, EX2);
 468    NV50_IR_OPCODE_CASE(LG2, LG2);
 469    NV50_IR_OPCODE_CASE(POW, POW);
 470
 471    NV50_IR_OPCODE_CASE(ABS, ABS);
 472
 473    NV50_IR_OPCODE_CASE(COS, COS);
 474    NV50_IR_OPCODE_CASE(DDX, DFDX);
 475    NV50_IR_OPCODE_CASE(DDY, DFDY);
 476    NV50_IR_OPCODE_CASE(KILP, DISCARD);
 477
 478    NV50_IR_OPCODE_CASE(SEQ, SET);
 479    NV50_IR_OPCODE_CASE(SFL, SET);
 480    NV50_IR_OPCODE_CASE(SGT, SET);
 481    NV50_IR_OPCODE_CASE(SIN, SIN);
 482    NV50_IR_OPCODE_CASE(SLE, SET);
 483    NV50_IR_OPCODE_CASE(SNE, SET);
 484    NV50_IR_OPCODE_CASE(STR, SET);
 485    NV50_IR_OPCODE_CASE(TEX, TEX);
 486    NV50_IR_OPCODE_CASE(TXD, TXD);
 487    NV50_IR_OPCODE_CASE(TXP, TEX);
 488
 489    NV50_IR_OPCODE_CASE(BRA, BRA);
 490    NV50_IR_OPCODE_CASE(CAL, CALL);
 491    NV50_IR_OPCODE_CASE(RET, RET);
 492    NV50_IR_OPCODE_CASE(CMP, SLCT);
 493
 494    NV50_IR_OPCODE_CASE(TXB, TXB);
 495
 496    NV50_IR_OPCODE_CASE(DIV, DIV);
 497
 498    NV50_IR_OPCODE_CASE(TXL, TXL);
 499
 500    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 501    NV50_IR_OPCODE_CASE(I2F, CVT);
 502    NV50_IR_OPCODE_CASE(NOT, NOT);
 503    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 504    NV50_IR_OPCODE_CASE(SHL, SHL);
 505
 506    NV50_IR_OPCODE_CASE(AND, AND);
 507    NV50_IR_OPCODE_CASE(OR, OR);
 508    NV50_IR_OPCODE_CASE(MOD, MOD);
 509    NV50_IR_OPCODE_CASE(XOR, XOR);
 510    NV50_IR_OPCODE_CASE(SAD, SAD);
 511    NV50_IR_OPCODE_CASE(TXF, TXF);
 512    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 513
 514    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 515    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 516
 517    NV50_IR_OPCODE_CASE(KIL, DISCARD);
 518
 519    NV50_IR_OPCODE_CASE(F2I, CVT);
 520    NV50_IR_OPCODE_CASE(IDIV, DIV);
 521    NV50_IR_OPCODE_CASE(IMAX, MAX);
 522    NV50_IR_OPCODE_CASE(IMIN, MIN);
 523    NV50_IR_OPCODE_CASE(IABS, ABS);
 524    NV50_IR_OPCODE_CASE(INEG, NEG);
 525    NV50_IR_OPCODE_CASE(ISGE, SET);
 526    NV50_IR_OPCODE_CASE(ISHR, SHR);
 527    NV50_IR_OPCODE_CASE(ISLT, SET);
 528    NV50_IR_OPCODE_CASE(F2U, CVT);
 529    NV50_IR_OPCODE_CASE(U2F, CVT);
 530    NV50_IR_OPCODE_CASE(UADD, ADD);
 531    NV50_IR_OPCODE_CASE(UDIV, DIV);
 532    NV50_IR_OPCODE_CASE(UMAD, MAD);
 533    NV50_IR_OPCODE_CASE(UMAX, MAX);
 534    NV50_IR_OPCODE_CASE(UMIN, MIN);
 535    NV50_IR_OPCODE_CASE(UMOD, MOD);
 536    NV50_IR_OPCODE_CASE(UMUL, MUL);
 537    NV50_IR_OPCODE_CASE(USEQ, SET);
 538    NV50_IR_OPCODE_CASE(USGE, SET);
 539    NV50_IR_OPCODE_CASE(USHR, SHR);
 540    NV50_IR_OPCODE_CASE(USLT, SET);
 541    NV50_IR_OPCODE_CASE(USNE, SET);
 542
 543    NV50_IR_OPCODE_CASE(LOAD, TXF);
 544    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 545    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 546    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 547    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 548    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 549    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 550    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 551    NV50_IR_OPCODE_CASE(RESINFO, TXQ);
 552
 553    NV50_IR_OPCODE_CASE(END, EXIT);
 554
 555    default:
 556       return nv50_ir::OP_NOP;
 557    }
 558 }
 559
 560 bool Instruction::checkDstSrcAliasing() const
 561 {
 562    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 563       return false;
 564
 565    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 566       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 567          break;
 568       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 569           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 570          return true;
 571    }
 572    return false;
 573 }
 574
 575 class Source
 576 {
 577 public:
 578    Source(struct nv50_ir_prog_info *);
 579    ~Source();
 580
 581 public:
 582    bool scanSource();
 583    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 584
 585 public:
 586    struct tgsi_shader_info scan;
 587    struct tgsi_full_instruction *insns;
 588    const struct tgsi_token *tokens;
 589    struct nv50_ir_prog_info *info;
 590
 591    nv50_ir::DynArray tempArrays;
 592    nv50_ir::DynArray immdArrays;
 593    int tempArrayCount;
 594    int immdArrayCount;
 595
 596    bool mainTempsInLMem;
 597
 598    int clipVertexOutput;
 599
 600    uint8_t *resourceTargets; // TGSI_TEXTURE_*
 601    unsigned resourceCount;
 602
 603 private:
 604    int inferSysValDirection(unsigned sn) const;
 605    bool scanDeclaration(const struct tgsi_full_declaration *);
 606    bool scanInstruction(const struct tgsi_full_instruction *);
 607    void scanProperty(const struct tgsi_full_property *);
 608    void scanImmediate(const struct tgsi_full_immediate *);
 609
 610    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 611 };
 612
 613 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 614 {
 615    tokens = (const struct tgsi_token *)info->bin.source;
 616
 617    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 618       tgsi_dump(tokens, 0);
 619
 620    resourceTargets = NULL;
 621
 622    mainTempsInLMem = FALSE;
 623 }
 624
 625 Source::~Source()
 626 {
 627    if (insns)
 628       FREE(insns);
 629
 630    if (info->immd.data)
 631       FREE(info->immd.data);
 632    if (info->immd.type)
 633       FREE(info->immd.type);
 634
 635    if (resourceTargets)
 636       delete[] resourceTargets;
 637 }
 638
 639 bool Source::scanSource()
 640 {
 641    unsigned insnCount = 0;
 642    struct tgsi_parse_context parse;
 643
 644    tgsi_scan_shader(tokens, &scan);
 645
 646    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 647                                                   sizeof(insns[0]));
 648    if (!insns)
 649       return false;
 650
 651    clipVertexOutput = -1;
 652
 653    resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
 654    resourceTargets = new uint8_t[resourceCount];
 655
 656    info->immd.bufSize = 0;
 657    tempArrayCount = 0;
 658    immdArrayCount = 0;
 659
 660    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 661    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 662    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 663
 664    if (info->type == PIPE_SHADER_FRAGMENT) {
 665       info->prop.fp.writesDepth = scan.writes_z;
 666       info->prop.fp.usesDiscard = scan.uses_kill;
 667    } else
 668    if (info->type == PIPE_SHADER_GEOMETRY) {
 669       info->prop.gp.instanceCount = 1; // default value
 670    }
 671
 672    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 673    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 674
 675    tgsi_parse_init(&parse, tokens);
 676    while (!tgsi_parse_end_of_tokens(&parse)) {
 677       tgsi_parse_token(&parse);
 678
 679       switch (parse.FullToken.Token.Type) {
 680       case TGSI_TOKEN_TYPE_IMMEDIATE:
 681          scanImmediate(&parse.FullToken.FullImmediate);
 682          break;
 683       case TGSI_TOKEN_TYPE_DECLARATION:
 684          scanDeclaration(&parse.FullToken.FullDeclaration);
 685          break;
 686       case TGSI_TOKEN_TYPE_INSTRUCTION:
 687          insns[insnCount++] = parse.FullToken.FullInstruction;
 688          scanInstruction(&parse.FullToken.FullInstruction);
 689          break;
 690       case TGSI_TOKEN_TYPE_PROPERTY:
 691          scanProperty(&parse.FullToken.FullProperty);
 692          break;
 693       default:
 694          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 695          break;
 696       }
 697    }
 698    tgsi_parse_free(&parse);
 699
 700    if (mainTempsInLMem)
 701       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 702
 703    if (info->io.genUserClip > 0) {
 704       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 705
 706       for (unsigned int n = 0; n < ((info->io.genUserClip + 3) / 4); ++n) {
 707          unsigned int i = info->numOutputs++;
 708          info->out[i].id = i;
 709          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 710          info->out[i].si = n;
 711          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 712       }
 713    }
 714
 715    return info->assignSlots(info) == 0;
 716 }
 717
 718 void Source::scanProperty(const struct tgsi_full_property *prop)
 719 {
 720    switch (prop->Property.PropertyName) {
 721    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 722       info->prop.gp.outputPrim = prop->u[0].Data;
 723       break;
 724    case TGSI_PROPERTY_GS_INPUT_PRIM:
 725       info->prop.gp.inputPrim = prop->u[0].Data;
 726       break;
 727    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 728       info->prop.gp.maxVertices = prop->u[0].Data;
 729       break;
 730 #if 0
 731    case TGSI_PROPERTY_GS_INSTANCE_COUNT:
 732       info->prop.gp.instanceCount = prop->u[0].Data;
 733       break;
 734 #endif
 735    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 736       info->prop.fp.separateFragData = TRUE;
 737       break;
 738    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 739    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 740       // we don't care
 741       break;
 742    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 743       info->io.genUserClip = -1;
 744       break;
 745    default:
 746       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 747       break;
 748    }
 749 }
 750
 751 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 752 {
 753    const unsigned n = info->immd.count++;
 754
 755    assert(n < scan.immediate_count);
 756
 757    for (int c = 0; c < 4; ++c)
 758       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 759
 760    info->immd.type[n] = imm->Immediate.DataType;
 761 }
 762
 763 int Source::inferSysValDirection(unsigned sn) const
 764 {
 765    switch (sn) {
 766    case TGSI_SEMANTIC_INSTANCEID:
 767    case TGSI_SEMANTIC_VERTEXID:
 768       return 1;
 769 #if 0
 770    case TGSI_SEMANTIC_LAYER:
 771    case TGSI_SEMANTIC_VIEWPORTINDEX:
 772       return 0;
 773 #endif
 774    case TGSI_SEMANTIC_PRIMID:
 775       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
 776    default:
 777       return 0;
 778    }
 779 }
 780
 781 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
 782 {
 783    unsigned i;
 784    unsigned sn = TGSI_SEMANTIC_GENERIC;
 785    unsigned si = 0;
 786    const unsigned first = decl->Range.First, last = decl->Range.Last;
 787
 788    if (decl->Declaration.Semantic) {
 789       sn = decl->Semantic.Name;
 790       si = decl->Semantic.Index;
 791    }
 792
 793    switch (decl->Declaration.File) {
 794    case TGSI_FILE_INPUT:
 795       if (info->type == PIPE_SHADER_VERTEX) {
 796          // all vertex attributes are equal
 797          for (i = first; i <= last; ++i) {
 798             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
 799             info->in[i].si = i;
 800          }
 801       } else {
 802          for (i = first; i <= last; ++i, ++si) {
 803             info->in[i].id = i;
 804             info->in[i].sn = sn;
 805             info->in[i].si = si;
 806             if (info->type == PIPE_SHADER_FRAGMENT) {
 807                // translate interpolation mode
 808                switch (decl->Declaration.Interpolate) {
 809                case TGSI_INTERPOLATE_CONSTANT:
 810                   info->in[i].flat = 1;
 811                   break;
 812                case TGSI_INTERPOLATE_COLOR:
 813                   info->in[i].sc = 1;
 814                   break;
 815                case TGSI_INTERPOLATE_LINEAR:
 816                   info->in[i].linear = 1;
 817                   break;
 818                default:
 819                   break;
 820                }
 821                if (decl->Declaration.Centroid)
 822                   info->in[i].centroid = 1;
 823             }
 824          }
 825       }
 826       break;
 827    case TGSI_FILE_OUTPUT:
 828       for (i = first; i <= last; ++i, ++si) {
 829          switch (sn) {
 830          case TGSI_SEMANTIC_POSITION:
 831             if (info->type == PIPE_SHADER_FRAGMENT)
 832                info->io.fragDepth = i;
 833             else
 834             if (clipVertexOutput < 0)
 835                clipVertexOutput = i;
 836             break;
 837          case TGSI_SEMANTIC_COLOR:
 838             if (info->type == PIPE_SHADER_FRAGMENT)
 839                info->prop.fp.numColourResults++;
 840             break;
 841          case TGSI_SEMANTIC_EDGEFLAG:
 842             info->io.edgeFlagOut = i;
 843             break;
 844          case TGSI_SEMANTIC_CLIPVERTEX:
 845             clipVertexOutput = i;
 846             break;
 847          case TGSI_SEMANTIC_CLIPDIST:
 848             info->io.clipDistanceMask |=
 849                decl->Declaration.UsageMask << (si * 4);
 850             info->io.genUserClip = -1;
 851             break;
 852          default:
 853             break;
 854          }
 855          info->out[i].id = i;
 856          info->out[i].sn = sn;
 857          info->out[i].si = si;
 858       }
 859       break;
 860    case TGSI_FILE_SYSTEM_VALUE:
 861       switch (sn) {
 862       case TGSI_SEMANTIC_VERTEXID:
 863          info->io.vertexId = first;
 864          break;
 865       default:
 866          break;
 867       }
 868       for (i = first; i <= last; ++i, ++si) {
 869          info->sv[i].sn = sn;
 870          info->sv[i].si = si;
 871          info->sv[i].input = inferSysValDirection(sn);
 872       }
 873       break;
 874    case TGSI_FILE_RESOURCE:
 875       for (i = first; i <= last; ++i)
 876          resourceTargets[i] = decl->Resource.Resource;
 877       break;
 878    case TGSI_FILE_IMMEDIATE_ARRAY:
 879    {
 880       if (decl->Dim.Index2D >= immdArrayCount)
 881          immdArrayCount = decl->Dim.Index2D + 1;
 882       immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
 883       int c;
 884       uint32_t base, count;
 885       switch (decl->Declaration.UsageMask) {
 886       case 0x1: c = 1; break;
 887       case 0x3: c = 2; break;
 888       default:
 889          c = 4;
 890          break;
 891       }
 892       immdArrays[decl->Dim.Index2D].u32 |= c;
 893       count = (last + 1) * c;
 894       base = info->immd.bufSize / 4;
 895       info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
 896       info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
 897                                            info->immd.bufSize);
 898       // NOTE: this assumes array declarations are ordered by Dim.Index2D
 899       for (i = 0; i < count; ++i)
 900          info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
 901    }
 902       break;
 903    case TGSI_FILE_TEMPORARY_ARRAY:
 904    {
 905       if (decl->Dim.Index2D >= tempArrayCount)
 906          tempArrayCount = decl->Dim.Index2D + 1;
 907       tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
 908       int c;
 909       uint32_t count;
 910       switch (decl->Declaration.UsageMask) {
 911       case 0x1: c = 1; break;
 912       case 0x3: c = 2; break;
 913       default:
 914          c = 4;
 915          break;
 916       }
 917       tempArrays[decl->Dim.Index2D].u32 |= c;
 918       count = (last + 1) * c;
 919       info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
 920    }
 921       break;
 922    case TGSI_FILE_NULL:
 923    case TGSI_FILE_TEMPORARY:
 924    case TGSI_FILE_ADDRESS:
 925    case TGSI_FILE_CONSTANT:
 926    case TGSI_FILE_IMMEDIATE:
 927    case TGSI_FILE_PREDICATE:
 928    case TGSI_FILE_SAMPLER:
 929       break;
 930    default:
 931       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
 932       return false;
 933    }
 934    return true;
 935 }
 936
 937 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
 938 {
 939    return insn.getOpcode() == TGSI_OPCODE_MOV &&
 940       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
 941       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
 942 }
 943
 944 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
 945 {
 946    Instruction insn(inst);
 947
 948    if (insn.dstCount()) {
 949       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
 950          Instruction::DstRegister dst = insn.getDst(0);
 951
 952          if (dst.isIndirect(0))
 953             for (unsigned i = 0; i < info->numOutputs; ++i)
 954                info->out[i].mask = 0xf;
 955          else
 956             info->out[dst.getIndex(0)].mask |= dst.getMask();
 957
 958          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE)
 959             info->out[dst.getIndex(0)].mask &= 1;
 960
 961          if (isEdgeFlagPassthrough(insn))
 962             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
 963       } else
 964       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
 965          if (insn.getDst(0).isIndirect(0))
 966             mainTempsInLMem = TRUE;
 967       }
 968    }
 969
 970    for (unsigned s = 0; s < insn.srcCount(); ++s) {
 971       Instruction::SrcRegister src = insn.getSrc(s);
 972       if (src.getFile() == TGSI_FILE_TEMPORARY)
 973          if (src.isIndirect(0))
 974             mainTempsInLMem = TRUE;
 975       if (src.getFile() != TGSI_FILE_INPUT)
 976          continue;
 977       unsigned mask = insn.srcMask(s);
 978
 979       if (src.isIndirect(0)) {
 980          for (unsigned i = 0; i < info->numInputs; ++i)
 981             info->in[i].mask = 0xf;
 982       } else {
 983          for (unsigned c = 0; c < 4; ++c) {
 984             if (!(mask & (1 << c)))
 985                continue;
 986             int k = src.getSwizzle(c);
 987             int i = src.getIndex(0);
 988             if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
 989                if (k <= TGSI_SWIZZLE_W)
 990                   info->in[i].mask |= 1 << k;
 991          }
 992       }
 993    }
 994    return true;
 995 }
 996
 997 nv50_ir::TexInstruction::Target
 998 Instruction::getTexture(const tgsi::Source *code, int s) const
 999 {
1000    if (insn->Instruction.Texture) {
1001       return translateTexture(insn->Texture.Texture);
1002    } else {
1003       // XXX: indirect access
1004       unsigned int r = getSrc(s).getIndex(0);
1005       assert(r < code->resourceCount);
1006       return translateTexture(code->resourceTargets[r]);
1007    }
1008 }
1009
1010 } // namespace tgsi
1011
1012 namespace {
1013
1014 using namespace nv50_ir;
1015
1016 class Converter : public BuildUtil
1017 {
1018 public:
1019    Converter(Program *, const tgsi::Source *);
1020    ~Converter();
1021
1022    bool run();
1023
1024 private:
1025    struct Subroutine
1026    {
1027       Subroutine(Function *f) : f(f) { }
1028       Function *f;
1029       ValueMap values;
1030    };
1031
1032    Value *getVertexBase(int s);
1033    DataArray *getArrayForFile(unsigned file, int idx);
1034    Value *fetchSrc(int s, int c);
1035    Value *acquireDst(int d, int c);
1036    void storeDst(int d, int c, Value *);
1037
1038    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1039    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1040                  Value *val, Value *ptr);
1041
1042    Value *applySrcMod(Value *, int s, int c);
1043
1044    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1045    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1046    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1047
1048    bool handleInstruction(const struct tgsi_full_instruction *);
1049    void exportOutputs();
1050    inline Subroutine *getSubroutine(unsigned ip);
1051    inline Subroutine *getSubroutine(Function *);
1052    inline bool isEndOfSubroutine(uint ip);
1053
1054    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1055
1056    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1057    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1058    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1059    void handleTXF(Value *dst0[4], int R);
1060    void handleTXQ(Value *dst0[4], enum TexQuery);
1061    void handleLIT(Value *dst0[4]);
1062    void handleUserClipPlanes();
1063
1064    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1065
1066    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1067
1068    Value *buildDot(int dim);
1069
1070    class BindArgumentsPass : public Pass {
1071    public:
1072       BindArgumentsPass(Converter &conv) : conv(conv) { }
1073
1074    private:
1075       Converter &conv;
1076       Subroutine *sub;
1077
1078       template<typename T> inline void
1079       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1080                      T (Function::*proto));
1081
1082       template<typename T> inline void
1083       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1084                       T (Function::*proto));
1085
1086    protected:
1087       bool visit(Function *);
1088       bool visit(BasicBlock *bb) { return false; }
1089    };
1090
1091 private:
1092    const struct tgsi::Source *code;
1093    const struct nv50_ir_prog_info *info;
1094
1095    struct {
1096       std::map<unsigned, Subroutine> map;
1097       Subroutine *cur;
1098    } sub;
1099
1100    uint ip; // instruction pointer
1101
1102    tgsi::Instruction tgsi;
1103
1104    DataType dstTy;
1105    DataType srcTy;
1106
1107    DataArray tData; // TGSI_FILE_TEMPORARY
1108    DataArray aData; // TGSI_FILE_ADDRESS
1109    DataArray pData; // TGSI_FILE_PREDICATE
1110    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1111    std::vector<DataArray> lData; // TGSI_FILE_TEMPORARY_ARRAY
1112    std::vector<DataArray> iData; // TGSI_FILE_IMMEDIATE_ARRAY
1113
1114    Value *zero;
1115    Value *fragCoord[4];
1116    Value *clipVtx[4];
1117
1118    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1119    uint8_t vtxBaseValid;
1120
1121    Stack condBBs;  // fork BB, then else clause BB
1122    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1123    Stack loopBBs;  // loop headers
1124    Stack breakBBs; // end of / after loop
1125 };
1126
1127 Symbol *
1128 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1129 {
1130    const int swz = src.getSwizzle(c);
1131
1132    return makeSym(src.getFile(),
1133                   src.is2D() ? src.getIndex(1) : 0,
1134                   src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1135                   src.getIndex(0) * 16 + swz * 4);
1136 }
1137
1138 Symbol *
1139 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1140 {
1141    return makeSym(dst.getFile(),
1142                   dst.is2D() ? dst.getIndex(1) : 0,
1143                   dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1144                   dst.getIndex(0) * 16 + c * 4);
1145 }
1146
1147 Symbol *
1148 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1149 {
1150    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1151
1152    sym->reg.fileIndex = fileIdx;
1153
1154    if (idx >= 0) {
1155       if (sym->reg.file == FILE_SHADER_INPUT)
1156          sym->setOffset(info->in[idx].slot[c] * 4);
1157       else
1158       if (sym->reg.file == FILE_SHADER_OUTPUT)
1159          sym->setOffset(info->out[idx].slot[c] * 4);
1160       else
1161       if (sym->reg.file == FILE_SYSTEM_VALUE)
1162          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1163       else
1164          sym->setOffset(address);
1165    } else {
1166       sym->setOffset(address);
1167    }
1168    return sym;
1169 }
1170
1171 static inline uint8_t
1172 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1173 {
1174    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1175
1176    if (var->flat)
1177       mode = NV50_IR_INTERP_FLAT;
1178    else
1179    if (var->linear)
1180       mode = NV50_IR_INTERP_LINEAR;
1181    else
1182    if (var->sc)
1183       mode = NV50_IR_INTERP_SC;
1184
1185    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1186       ? OP_PINTERP : OP_LINTERP;
1187
1188    if (var->centroid)
1189       mode |= NV50_IR_INTERP_CENTROID;
1190
1191    return mode;
1192 }
1193
1194 Value *
1195 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1196 {
1197    operation op;
1198
1199    // XXX: no way to know interpolation mode if we don't know what's accessed
1200    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1201                                                       src.getIndex(0)], op);
1202
1203    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1204
1205    insn->setDef(0, getScratch());
1206    insn->setSrc(0, srcToSym(src, c));
1207    if (op == OP_PINTERP)
1208       insn->setSrc(1, fragCoord[3]);
1209    if (ptr)
1210       insn->setIndirect(0, 0, ptr);
1211
1212    insn->setInterpolate(mode);
1213
1214    bb->insertTail(insn);
1215    return insn->getDef(0);
1216 }
1217
1218 Value *
1219 Converter::applySrcMod(Value *val, int s, int c)
1220 {
1221    Modifier m = tgsi.getSrc(s).getMod(c);
1222    DataType ty = tgsi.inferSrcType();
1223
1224    if (m & Modifier(NV50_IR_MOD_ABS))
1225       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1226
1227    if (m & Modifier(NV50_IR_MOD_NEG))
1228       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1229
1230    return val;
1231 }
1232
1233 Value *
1234 Converter::getVertexBase(int s)
1235 {
1236    assert(s < 5);
1237    if (!(vtxBaseValid & (1 << s))) {
1238       const int index = tgsi.getSrc(s).getIndex(1);
1239       Value *rel = NULL;
1240       if (tgsi.getSrc(s).isIndirect(1))
1241          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1242       vtxBaseValid |= 1 << s;
1243       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1244    }
1245    return vtxBase[s];
1246 }
1247
1248 Value *
1249 Converter::fetchSrc(int s, int c)
1250 {
1251    Value *res;
1252    Value *ptr = NULL, *dimRel = NULL;
1253
1254    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1255
1256    if (src.isIndirect(0))
1257       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1258
1259    if (src.is2D()) {
1260       switch (src.getFile()) {
1261       case TGSI_FILE_INPUT:
1262          dimRel = getVertexBase(s);
1263          break;
1264       case TGSI_FILE_CONSTANT:
1265          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1266          if (src.isIndirect(1))
1267             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1268          break;
1269       default:
1270          break;
1271       }
1272    }
1273
1274    res = fetchSrc(src, c, ptr);
1275
1276    if (dimRel)
1277       res->getInsn()->setIndirect(0, 1, dimRel);
1278
1279    return applySrcMod(res, s, c);
1280 }
1281
1282 Converter::DataArray *
1283 Converter::getArrayForFile(unsigned file, int idx)
1284 {
1285    switch (file) {
1286    case TGSI_FILE_TEMPORARY:
1287       return &tData;
1288    case TGSI_FILE_PREDICATE:
1289       return &pData;
1290    case TGSI_FILE_ADDRESS:
1291       return &aData;
1292    case TGSI_FILE_TEMPORARY_ARRAY:
1293       assert(idx < code->tempArrayCount);
1294       return &lData[idx];
1295    case TGSI_FILE_IMMEDIATE_ARRAY:
1296       assert(idx < code->immdArrayCount);
1297       return &iData[idx];
1298    case TGSI_FILE_OUTPUT:
1299       assert(prog->getType() == Program::TYPE_FRAGMENT);
1300       return &oData;
1301    default:
1302       assert(!"invalid/unhandled TGSI source file");
1303       return NULL;
1304    }
1305 }
1306
1307 Value *
1308 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1309 {
1310    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1311    const int idx = src.getIndex(0);
1312    const int swz = src.getSwizzle(c);
1313
1314    switch (src.getFile()) {
1315    case TGSI_FILE_IMMEDIATE:
1316       assert(!ptr);
1317       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1318    case TGSI_FILE_CONSTANT:
1319       return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1320    case TGSI_FILE_INPUT:
1321       if (prog->getType() == Program::TYPE_FRAGMENT) {
1322          // don't load masked inputs, won't be assigned a slot
1323          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1324             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1325          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1326             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1327          return interpolate(src, c, ptr);
1328       }
1329       return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1330    case TGSI_FILE_OUTPUT:
1331       assert(!"load from output file");
1332       return NULL;
1333    case TGSI_FILE_SYSTEM_VALUE:
1334       assert(!ptr);
1335       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1336    default:
1337       return getArrayForFile(src.getFile(), idx2d)->load(
1338          sub.cur->values, idx, swz, ptr);
1339    }
1340 }
1341
1342 Value *
1343 Converter::acquireDst(int d, int c)
1344 {
1345    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1346    const unsigned f = dst.getFile();
1347    const int idx = dst.getIndex(0);
1348    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1349
1350    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1351       return NULL;
1352
1353    if (dst.isIndirect(0) ||
1354        f == TGSI_FILE_TEMPORARY_ARRAY ||
1355        f == TGSI_FILE_SYSTEM_VALUE ||
1356        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1357       return getScratch();
1358
1359    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1360 }
1361
1362 void
1363 Converter::storeDst(int d, int c, Value *val)
1364 {
1365    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1366
1367    switch (tgsi.getSaturate()) {
1368    case TGSI_SAT_NONE:
1369       break;
1370    case TGSI_SAT_ZERO_ONE:
1371       mkOp1(OP_SAT, dstTy, val, val);
1372       break;
1373    case TGSI_SAT_MINUS_PLUS_ONE:
1374       mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1375       mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1376       break;
1377    default:
1378       assert(!"invalid saturation mode");
1379       break;
1380    }
1381
1382    Value *ptr = dst.isIndirect(0) ?
1383       fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1384
1385    if (info->io.genUserClip > 0 &&
1386        dst.getFile() == TGSI_FILE_OUTPUT &&
1387        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1388       mkMov(clipVtx[c], val);
1389       val = clipVtx[c];
1390    }
1391
1392    storeDst(dst, c, val, ptr);
1393 }
1394
1395 void
1396 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1397                     Value *val, Value *ptr)
1398 {
1399    const unsigned f = dst.getFile();
1400    const int idx = dst.getIndex(0);
1401    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1402
1403    if (f == TGSI_FILE_SYSTEM_VALUE) {
1404       assert(!ptr);
1405       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1406    } else
1407    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1408       if (ptr || (info->out[idx].mask & (1 << c)))
1409          mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1410    } else
1411    if (f == TGSI_FILE_TEMPORARY ||
1412        f == TGSI_FILE_TEMPORARY_ARRAY ||
1413        f == TGSI_FILE_PREDICATE ||
1414        f == TGSI_FILE_ADDRESS ||
1415        f == TGSI_FILE_OUTPUT) {
1416       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1417    } else {
1418       assert(!"invalid dst file");
1419    }
1420 }
1421
1422 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1423    for (chan = 0; chan < 4; ++chan)                 \
1424       if (!inst.getDst(d).isMasked(chan))
1425
1426 Value *
1427 Converter::buildDot(int dim)
1428 {
1429    assert(dim > 0);
1430
1431    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1432    Value *dotp = getScratch();
1433
1434    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1435
1436    for (int c = 1; c < dim; ++c) {
1437       src0 = fetchSrc(0, c);
1438       src1 = fetchSrc(1, c);
1439       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1440    }
1441    return dotp;
1442 }
1443
1444 void
1445 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1446 {
1447    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1448    join->fixed = 1;
1449    conv->insertHead(join);
1450
1451    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1452    fork->insertBefore(fork->getExit(), fork->joinAt);
1453 }
1454
1455 void
1456 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1457 {
1458    unsigned rIdx = 0, sIdx = 0;
1459
1460    if (R >= 0)
1461       rIdx = tgsi.getSrc(R).getIndex(0);
1462    if (S >= 0)
1463       sIdx = tgsi.getSrc(S).getIndex(0);
1464
1465    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1466
1467    if (tgsi.getSrc(R).isIndirect(0)) {
1468       tex->tex.rIndirectSrc = s;
1469       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1470    }
1471    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1472       tex->tex.sIndirectSrc = s;
1473       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1474    }
1475 }
1476
1477 void
1478 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1479 {
1480    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1481    tex->tex.query = query;
1482    unsigned int c, d;
1483
1484    for (d = 0, c = 0; c < 4; ++c) {
1485       if (!dst0[c])
1486          continue;
1487       tex->tex.mask |= 1 << c;
1488       tex->setDef(d++, dst0[c]);
1489    }
1490    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1491
1492    setTexRS(tex, c, 1, -1);
1493
1494    bb->insertTail(tex);
1495 }
1496
1497 void
1498 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1499 {
1500    Value *proj = fetchSrc(0, 3);
1501    Instruction *insn = proj->getUniqueInsn();
1502    int c;
1503
1504    if (insn->op == OP_PINTERP) {
1505       bb->insertTail(insn = cloneForward(func, insn));
1506       insn->op = OP_LINTERP;
1507       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1508       insn->setSrc(1, NULL);
1509       proj = insn->getDef(0);
1510    }
1511    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1512
1513    for (c = 0; c < 4; ++c) {
1514       if (!(mask & (1 << c)))
1515          continue;
1516       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1517          continue;
1518       mask &= ~(1 << c);
1519
1520       bb->insertTail(insn = cloneForward(func, insn));
1521       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1522       insn->setSrc(1, proj);
1523       dst[c] = insn->getDef(0);
1524    }
1525    if (!mask)
1526       return;
1527
1528    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1529
1530    for (c = 0; c < 4; ++c)
1531       if (mask & (1 << c))
1532          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1533 }
1534
1535 // order of nv50 ir sources: x y z layer lod/bias shadow
1536 // order of TGSI TEX sources: x y z layer shadow lod/bias
1537 //  lowering will finally set the hw specific order (like array first on nvc0)
1538 void
1539 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1540 {
1541    Value *val;
1542    Value *arg[4], *src[8];
1543    Value *lod = NULL, *shd = NULL;
1544    unsigned int s, c, d;
1545    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1546
1547    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1548
1549    for (s = 0; s < tgt.getArgCount(); ++s)
1550       arg[s] = src[s] = fetchSrc(0, s);
1551
1552    if (texi->op == OP_TXL || texi->op == OP_TXB)
1553       lod = fetchSrc(L >> 4, L & 3);
1554
1555    if (C == 0x0f)
1556       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1557
1558    if (tgt.isShadow())
1559       shd = fetchSrc(C >> 4, C & 3);
1560
1561    if (texi->op == OP_TXD) {
1562       for (c = 0; c < tgt.getDim(); ++c) {
1563          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1564          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1565       }
1566    }
1567
1568    // cube textures don't care about projection value, it's divided out
1569    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1570       unsigned int n = tgt.getDim();
1571       if (shd) {
1572          arg[n] = shd;
1573          ++n;
1574          assert(tgt.getDim() == tgt.getArgCount());
1575       }
1576       loadProjTexCoords(src, arg, (1 << n) - 1);
1577       if (shd)
1578          shd = src[n - 1];
1579    }
1580
1581    if (tgt.isCube()) {
1582       for (c = 0; c < 3; ++c)
1583          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1584       val = getScratch();
1585       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1586       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1587       mkOp1(OP_RCP, TYPE_F32, val, val);
1588       for (c = 0; c < 3; ++c)
1589          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1590    }
1591
1592    for (c = 0, d = 0; c < 4; ++c) {
1593       if (dst[c]) {
1594          texi->setDef(d++, dst[c]);
1595          texi->tex.mask |= 1 << c;
1596       } else {
1597          // NOTE: maybe hook up def too, for CSE
1598       }
1599    }
1600    for (s = 0; s < tgt.getArgCount(); ++s)
1601       texi->setSrc(s, src[s]);
1602    if (lod)
1603       texi->setSrc(s++, lod);
1604    if (shd)
1605       texi->setSrc(s++, shd);
1606
1607    setTexRS(texi, s, R, S);
1608
1609    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1610       texi->tex.levelZero = true;
1611
1612    bb->insertTail(texi);
1613 }
1614
1615 // 1st source: xyz = coordinates, w = lod
1616 // 2nd source: offset
1617 void
1618 Converter::handleTXF(Value *dst[4], int R)
1619 {
1620    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1621    unsigned int c, d, s;
1622
1623    texi->tex.target = tgsi.getTexture(code, R);
1624
1625    for (c = 0, d = 0; c < 4; ++c) {
1626       if (dst[c]) {
1627          texi->setDef(d++, dst[c]);
1628          texi->tex.mask |= 1 << c;
1629       }
1630    }
1631    for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1632       texi->setSrc(c, fetchSrc(0, c));
1633    texi->setSrc(c++, fetchSrc(0, 3)); // lod
1634
1635    setTexRS(texi, c, R, -1);
1636
1637    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1638       for (c = 0; c < 3; ++c) {
1639          texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1640          if (texi->tex.offset[s][c])
1641             texi->tex.useOffsets = s + 1;
1642       }
1643    }
1644
1645    bb->insertTail(texi);
1646 }
1647
1648 void
1649 Converter::handleLIT(Value *dst0[4])
1650 {
1651    Value *val0 = NULL;
1652    unsigned int mask = tgsi.getDst(0).getMask();
1653
1654    if (mask & (1 << 0))
1655       loadImm(dst0[0], 1.0f);
1656
1657    if (mask & (1 << 3))
1658       loadImm(dst0[3], 1.0f);
1659
1660    if (mask & (3 << 1)) {
1661       val0 = getScratch();
1662       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1663       if (mask & (1 << 1))
1664          mkMov(dst0[1], val0);
1665    }
1666
1667    if (mask & (1 << 2)) {
1668       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1669       Value *val1 = getScratch(), *val3 = getScratch();
1670
1671       Value *pos128 = loadImm(NULL, +127.999999f);
1672       Value *neg128 = loadImm(NULL, -127.999999f);
1673
1674       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1675       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1676       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1677       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1678
1679       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1680    }
1681 }
1682
1683 Converter::Subroutine *
1684 Converter::getSubroutine(unsigned ip)
1685 {
1686    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
1687
1688    if (it == sub.map.end())
1689       it = sub.map.insert(std::make_pair(
1690               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
1691
1692    return &it->second;
1693 }
1694
1695 Converter::Subroutine *
1696 Converter::getSubroutine(Function *f)
1697 {
1698    unsigned ip = f->getLabel();
1699    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
1700
1701    if (it == sub.map.end())
1702       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
1703
1704    return &it->second;
1705 }
1706
1707 bool
1708 Converter::isEndOfSubroutine(uint ip)
1709 {
1710    assert(ip < code->scan.num_instructions);
1711    tgsi::Instruction insn(&code->insns[ip]);
1712    return (insn.getOpcode() == TGSI_OPCODE_END ||
1713            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1714            // does END occur at end of main or the very end ?
1715            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1716 }
1717
1718 bool
1719 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1720 {
1721    Value *dst0[4], *rDst0[4];
1722    Value *src0, *src1, *src2;
1723    Value *val0, *val1;
1724    int c;
1725
1726    tgsi = tgsi::Instruction(insn);
1727
1728    bool useScratchDst = tgsi.checkDstSrcAliasing();
1729
1730    operation op = tgsi.getOP();
1731    dstTy = tgsi.inferDstType();
1732    srcTy = tgsi.inferSrcType();
1733
1734    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1735
1736    if (tgsi.dstCount()) {
1737       for (c = 0; c < 4; ++c) {
1738          rDst0[c] = acquireDst(0, c);
1739          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1740       }
1741    }
1742
1743    switch (tgsi.getOpcode()) {
1744    case TGSI_OPCODE_ADD:
1745    case TGSI_OPCODE_UADD:
1746    case TGSI_OPCODE_AND:
1747    case TGSI_OPCODE_DIV:
1748    case TGSI_OPCODE_IDIV:
1749    case TGSI_OPCODE_UDIV:
1750    case TGSI_OPCODE_MAX:
1751    case TGSI_OPCODE_MIN:
1752    case TGSI_OPCODE_IMAX:
1753    case TGSI_OPCODE_IMIN:
1754    case TGSI_OPCODE_UMAX:
1755    case TGSI_OPCODE_UMIN:
1756    case TGSI_OPCODE_MOD:
1757    case TGSI_OPCODE_UMOD:
1758    case TGSI_OPCODE_MUL:
1759    case TGSI_OPCODE_UMUL:
1760    case TGSI_OPCODE_OR:
1761    case TGSI_OPCODE_POW:
1762    case TGSI_OPCODE_SHL:
1763    case TGSI_OPCODE_ISHR:
1764    case TGSI_OPCODE_USHR:
1765    case TGSI_OPCODE_SUB:
1766    case TGSI_OPCODE_XOR:
1767       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1768          src0 = fetchSrc(0, c);
1769          src1 = fetchSrc(1, c);
1770          mkOp2(op, dstTy, dst0[c], src0, src1);
1771       }
1772       break;
1773    case TGSI_OPCODE_MAD:
1774    case TGSI_OPCODE_UMAD:
1775    case TGSI_OPCODE_SAD:
1776       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1777          src0 = fetchSrc(0, c);
1778          src1 = fetchSrc(1, c);
1779          src2 = fetchSrc(2, c);
1780          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1781       }
1782       break;
1783    case TGSI_OPCODE_MOV:
1784    case TGSI_OPCODE_ABS:
1785    case TGSI_OPCODE_CEIL:
1786    case TGSI_OPCODE_FLR:
1787    case TGSI_OPCODE_TRUNC:
1788    case TGSI_OPCODE_RCP:
1789    case TGSI_OPCODE_IABS:
1790    case TGSI_OPCODE_INEG:
1791    case TGSI_OPCODE_NOT:
1792    case TGSI_OPCODE_DDX:
1793    case TGSI_OPCODE_DDY:
1794       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1795          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1796       break;
1797    case TGSI_OPCODE_RSQ:
1798       src0 = fetchSrc(0, 0);
1799       val0 = getScratch();
1800       mkOp1(OP_ABS, TYPE_F32, val0, src0);
1801       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1802       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1803          mkMov(dst0[c], val0);
1804       break;
1805    case TGSI_OPCODE_ARL:
1806       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1807          src0 = fetchSrc(0, c);
1808          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1809          mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1810       }
1811       break;
1812    case TGSI_OPCODE_UARL:
1813       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1814          mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1815       break;
1816    case TGSI_OPCODE_EX2:
1817    case TGSI_OPCODE_LG2:
1818       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1819       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1820          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1821       break;
1822    case TGSI_OPCODE_COS:
1823    case TGSI_OPCODE_SIN:
1824       val0 = getScratch();
1825       if (mask & 7) {
1826          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1827          mkOp1(op, TYPE_F32, val0, val0);
1828          for (c = 0; c < 3; ++c)
1829             if (dst0[c])
1830                mkMov(dst0[c], val0);
1831       }
1832       if (dst0[3]) {
1833          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1834          mkOp1(op, TYPE_F32, dst0[3], val0);
1835       }
1836       break;
1837    case TGSI_OPCODE_SCS:
1838       if (mask & 3) {
1839          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1840          if (dst0[0])
1841             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1842          if (dst0[1])
1843             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1844       }
1845       if (dst0[2])
1846          loadImm(dst0[2], 0.0f);
1847       if (dst0[3])
1848          loadImm(dst0[3], 1.0f);
1849       break;
1850    case TGSI_OPCODE_EXP:
1851       src0 = fetchSrc(0, 0);
1852       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1853       if (dst0[1])
1854          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1855       if (dst0[0])
1856          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1857       if (dst0[2])
1858          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1859       if (dst0[3])
1860          loadImm(dst0[3], 1.0f);
1861       break;
1862    case TGSI_OPCODE_LOG:
1863       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1864       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1865       if (dst0[0] || dst0[1])
1866          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1867       if (dst0[1]) {
1868          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1869          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1870          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1871       }
1872       if (dst0[3])
1873          loadImm(dst0[3], 1.0f);
1874       break;
1875    case TGSI_OPCODE_DP2:
1876       val0 = buildDot(2);
1877       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1878          mkMov(dst0[c], val0);
1879       break;
1880    case TGSI_OPCODE_DP3:
1881       val0 = buildDot(3);
1882       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1883          mkMov(dst0[c], val0);
1884       break;
1885    case TGSI_OPCODE_DP4:
1886       val0 = buildDot(4);
1887       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1888          mkMov(dst0[c], val0);
1889       break;
1890    case TGSI_OPCODE_DPH:
1891       val0 = buildDot(3);
1892       src1 = fetchSrc(1, 3);
1893       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1894       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1895          mkMov(dst0[c], val0);
1896       break;
1897    case TGSI_OPCODE_DST:
1898       if (dst0[0])
1899          loadImm(dst0[0], 1.0f);
1900       if (dst0[1]) {
1901          src0 = fetchSrc(0, 1);
1902          src1 = fetchSrc(1, 1);
1903          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1904       }
1905       if (dst0[2])
1906          mkMov(dst0[2], fetchSrc(0, 2));
1907       if (dst0[3])
1908          mkMov(dst0[3], fetchSrc(1, 3));
1909       break;
1910    case TGSI_OPCODE_LRP:
1911       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1912          src0 = fetchSrc(0, c);
1913          src1 = fetchSrc(1, c);
1914          src2 = fetchSrc(2, c);
1915          mkOp3(OP_MAD, TYPE_F32, dst0[c],
1916                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1917       }
1918       break;
1919    case TGSI_OPCODE_LIT:
1920       handleLIT(dst0);
1921       break;
1922    case TGSI_OPCODE_XPD:
1923       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1924          if (c < 3) {
1925             val0 = getSSA();
1926             src0 = fetchSrc(1, (c + 1) % 3);
1927             src1 = fetchSrc(0, (c + 2) % 3);
1928             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1929             mkOp1(OP_NEG, TYPE_F32, val0, val0);
1930
1931             src0 = fetchSrc(0, (c + 1) % 3);
1932             src1 = fetchSrc(1, (c + 2) % 3);
1933             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1934          } else {
1935             loadImm(dst0[c], 1.0f);
1936          }
1937       }
1938       break;
1939    case TGSI_OPCODE_ISSG:
1940    case TGSI_OPCODE_SSG:
1941       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1942          src0 = fetchSrc(0, c);
1943          val0 = getScratch();
1944          val1 = getScratch();
1945          mkCmp(OP_SET, CC_GT, srcTy, val0, src0, zero);
1946          mkCmp(OP_SET, CC_LT, srcTy, val1, src0, zero);
1947          if (srcTy == TYPE_F32)
1948             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1949          else
1950             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
1951       }
1952       break;
1953    case TGSI_OPCODE_UCMP:
1954    case TGSI_OPCODE_CMP:
1955       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1956          src0 = fetchSrc(0, c);
1957          src1 = fetchSrc(1, c);
1958          src2 = fetchSrc(2, c);
1959          if (src1 == src2)
1960             mkMov(dst0[c], src1);
1961          else
1962             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1963                   srcTy, dst0[c], src1, src2, src0);
1964       }
1965       break;
1966    case TGSI_OPCODE_FRC:
1967       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1968          src0 = fetchSrc(0, c);
1969          val0 = getScratch();
1970          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1971          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1972       }
1973       break;
1974    case TGSI_OPCODE_ROUND:
1975       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1976          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1977          ->rnd = ROUND_NI;
1978       break;
1979    case TGSI_OPCODE_CLAMP:
1980       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1981          src0 = fetchSrc(0, c);
1982          src1 = fetchSrc(1, c);
1983          src2 = fetchSrc(2, c);
1984          val0 = getScratch();
1985          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1986          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1987       }
1988       break;
1989    case TGSI_OPCODE_SLT:
1990    case TGSI_OPCODE_SGE:
1991    case TGSI_OPCODE_SEQ:
1992    case TGSI_OPCODE_SFL:
1993    case TGSI_OPCODE_SGT:
1994    case TGSI_OPCODE_SLE:
1995    case TGSI_OPCODE_SNE:
1996    case TGSI_OPCODE_STR:
1997    case TGSI_OPCODE_ISGE:
1998    case TGSI_OPCODE_ISLT:
1999    case TGSI_OPCODE_USEQ:
2000    case TGSI_OPCODE_USGE:
2001    case TGSI_OPCODE_USLT:
2002    case TGSI_OPCODE_USNE:
2003       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2004          src0 = fetchSrc(0, c);
2005          src1 = fetchSrc(1, c);
2006          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
2007       }
2008       break;
2009    case TGSI_OPCODE_KIL:
2010       val0 = new_LValue(func, FILE_PREDICATE);
2011       for (c = 0; c < 4; ++c) {
2012          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
2013          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2014       }
2015       break;
2016    case TGSI_OPCODE_KILP:
2017       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2018       break;
2019    case TGSI_OPCODE_TEX:
2020    case TGSI_OPCODE_TXB:
2021    case TGSI_OPCODE_TXL:
2022    case TGSI_OPCODE_TXP:
2023       //              R  S     L     C    Dx    Dy
2024       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2025       break;
2026    case TGSI_OPCODE_TXD:
2027       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2028       break;
2029    case TGSI_OPCODE_SAMPLE:
2030    case TGSI_OPCODE_SAMPLE_B:
2031    case TGSI_OPCODE_SAMPLE_D:
2032    case TGSI_OPCODE_SAMPLE_L:
2033    case TGSI_OPCODE_SAMPLE_C:
2034    case TGSI_OPCODE_SAMPLE_C_LZ:
2035       handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
2036       break;
2037    case TGSI_OPCODE_TXF:
2038    case TGSI_OPCODE_LOAD:
2039       handleTXF(dst0, 1);
2040       break;
2041    case TGSI_OPCODE_TXQ:
2042    case TGSI_OPCODE_RESINFO:
2043       handleTXQ(dst0, TXQ_DIMS);
2044       break;
2045    case TGSI_OPCODE_F2I:
2046    case TGSI_OPCODE_F2U:
2047       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2048          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2049       break;
2050    case TGSI_OPCODE_I2F:
2051    case TGSI_OPCODE_U2F:
2052       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2053          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2054       break;
2055    case TGSI_OPCODE_EMIT:
2056    case TGSI_OPCODE_ENDPRIM:
2057       // get vertex stream if specified (must be immediate)
2058       src0 = tgsi.srcCount() ?
2059          mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2060       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2061       break;
2062    case TGSI_OPCODE_IF:
2063    {
2064       BasicBlock *ifBB = new BasicBlock(func);
2065
2066       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2067       condBBs.push(bb);
2068       joinBBs.push(bb);
2069
2070       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2071
2072       setPosition(ifBB, true);
2073    }
2074       break;
2075    case TGSI_OPCODE_ELSE:
2076    {
2077       BasicBlock *elseBB = new BasicBlock(func);
2078       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2079
2080       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2081       condBBs.push(bb);
2082
2083       forkBB->getExit()->asFlow()->target.bb = elseBB;
2084       if (!bb->isTerminated())
2085          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2086
2087       setPosition(elseBB, true);
2088    }
2089       break;
2090    case TGSI_OPCODE_ENDIF:
2091    {
2092       BasicBlock *convBB = new BasicBlock(func);
2093       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2094       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2095
2096       if (!bb->isTerminated()) {
2097          // we only want join if none of the clauses ended with CONT/BREAK/RET
2098          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2099             insertConvergenceOps(convBB, forkBB);
2100          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2101          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2102       }
2103
2104       if (prevBB->getExit()->op == OP_BRA) {
2105          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2106          prevBB->getExit()->asFlow()->target.bb = convBB;
2107       }
2108       setPosition(convBB, true);
2109    }
2110       break;
2111    case TGSI_OPCODE_BGNLOOP:
2112    {
2113       BasicBlock *lbgnBB = new BasicBlock(func);
2114       BasicBlock *lbrkBB = new BasicBlock(func);
2115
2116       loopBBs.push(lbgnBB);
2117       breakBBs.push(lbrkBB);
2118       if (loopBBs.getSize() > func->loopNestingBound)
2119          func->loopNestingBound++;
2120
2121       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2122
2123       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2124       setPosition(lbgnBB, true);
2125       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2126    }
2127       break;
2128    case TGSI_OPCODE_ENDLOOP:
2129    {
2130       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2131
2132       if (!bb->isTerminated()) {
2133          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2134          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2135       }
2136       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2137    }
2138       break;
2139    case TGSI_OPCODE_BRK:
2140    {
2141       if (bb->isTerminated())
2142          break;
2143       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2144       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2145       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2146    }
2147       break;
2148    case TGSI_OPCODE_CONT:
2149    {
2150       if (bb->isTerminated())
2151          break;
2152       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2153       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2154       contBB->explicitCont = true;
2155       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2156    }
2157       break;
2158    case TGSI_OPCODE_BGNSUB:
2159    {
2160       Subroutine *s = getSubroutine(ip);
2161       BasicBlock *entry = new BasicBlock(s->f);
2162       BasicBlock *leave = new BasicBlock(s->f);
2163
2164       // multiple entrypoints possible, keep the graph connected
2165       if (prog->getType() == Program::TYPE_COMPUTE)
2166          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2167
2168       sub.cur = s;
2169       s->f->setEntry(entry);
2170       s->f->setExit(leave);
2171       setPosition(entry, true);
2172       return true;
2173    }
2174    case TGSI_OPCODE_ENDSUB:
2175    {
2176       sub.cur = getSubroutine(prog->main);
2177       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2178       return true;
2179    }
2180    case TGSI_OPCODE_CAL:
2181    {
2182       Subroutine *s = getSubroutine(tgsi.getLabel());
2183       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2184       func->call.attach(&s->f->call, Graph::Edge::TREE);
2185       return true;
2186    }
2187    case TGSI_OPCODE_RET:
2188    {
2189       if (bb->isTerminated())
2190          return true;
2191       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2192
2193       if (!isEndOfSubroutine(ip + 1)) {
2194          // insert a PRERET at the entry if this is an early return
2195          // (only needed for sharing code in the epilogue)
2196          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2197          bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2198       } else {
2199          mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2200          bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2201       }
2202    }
2203       break;
2204    case TGSI_OPCODE_END:
2205    {
2206       // attach and generate epilogue code
2207       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2208       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2209       setPosition(epilogue, true);
2210       if (prog->getType() == Program::TYPE_FRAGMENT)
2211          exportOutputs();
2212       if (info->io.genUserClip > 0)
2213          handleUserClipPlanes();
2214       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2215    }
2216       break;
2217    case TGSI_OPCODE_SWITCH:
2218    case TGSI_OPCODE_CASE:
2219       ERROR("switch/case opcode encountered, should have been lowered\n");
2220       abort();
2221       break;
2222    default:
2223       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2224       assert(0);
2225       break;
2226    }
2227
2228    if (tgsi.dstCount()) {
2229       for (c = 0; c < 4; ++c) {
2230          if (!dst0[c])
2231             continue;
2232          if (dst0[c] != rDst0[c])
2233             mkMov(rDst0[c], dst0[c]);
2234          storeDst(0, c, rDst0[c]);
2235       }
2236    }
2237    vtxBaseValid = 0;
2238
2239    return true;
2240 }
2241
2242 void
2243 Converter::handleUserClipPlanes()
2244 {
2245    Value *res[8];
2246    int n, i, c;
2247
2248    for (c = 0; c < 4; ++c) {
2249       for (i = 0; i < info->io.genUserClip; ++i) {
2250          Value *ucp;
2251          ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2252                                          i * 16 + c * 4), NULL);
2253          if (c == 0)
2254             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2255          else
2256             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2257       }
2258    }
2259
2260    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2261
2262    for (i = 0; i < info->io.genUserClip; ++i) {
2263       n = i / 4 + first;
2264       c = i % 4;
2265       Symbol *sym =
2266          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2267       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2268    }
2269 }
2270
2271 void
2272 Converter::exportOutputs()
2273 {
2274    for (unsigned int i = 0; i < info->numOutputs; ++i) {
2275       for (unsigned int c = 0; c < 4; ++c) {
2276          if (!oData.exists(sub.cur->values, i, c))
2277             continue;
2278          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2279                                 info->out[i].slot[c] * 4);
2280          Value *val = oData.load(sub.cur->values, i, c, NULL);
2281          if (val)
2282             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2283       }
2284    }
2285 }
2286
2287 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2288      code(code),
2289      tgsi(NULL),
2290      tData(this), aData(this), pData(this), oData(this)
2291 {
2292    info = code->info;
2293
2294    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2295
2296    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2297    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2298    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2299    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2300
2301    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2302    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2303    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_ADDRESS, 0);
2304    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2305
2306    for (int vol = 0, i = 0; i < code->tempArrayCount; ++i) {
2307       int len = code->tempArrays[i].u32 >> 2;
2308       int dim = code->tempArrays[i].u32 & 3;
2309
2310       lData.push_back(DataArray(this));
2311       lData.back().setup(TGSI_FILE_TEMPORARY_ARRAY, i, vol, len, dim, 4,
2312                          FILE_MEMORY_LOCAL, 0);
2313
2314       vol += (len * dim * 4 + 0xf) & ~0xf;
2315    }
2316
2317    for (int vol = 0, i = 0; i < code->immdArrayCount; ++i) {
2318       int len = code->immdArrays[i].u32 >> 2;
2319       int dim = code->immdArrays[i].u32 & 3;
2320
2321       lData.push_back(DataArray(this));
2322       lData.back().setup(TGSI_FILE_IMMEDIATE_ARRAY, i, vol, len, dim, 4,
2323                          FILE_MEMORY_CONST, 14);
2324
2325       vol += (len * dim * 4 + 0xf) & ~0xf;
2326    }
2327
2328    zero = mkImm((uint32_t)0);
2329
2330    vtxBaseValid = 0;
2331 }
2332
2333 Converter::~Converter()
2334 {
2335 }
2336
2337 template<typename T> inline void
2338 Converter::BindArgumentsPass::updateCallArgs(
2339    Instruction *i, void (Instruction::*setArg)(int, Value *),
2340    T (Function::*proto))
2341 {
2342    Function *g = i->asFlow()->target.fn;
2343    Subroutine *subg = conv.getSubroutine(g);
2344
2345    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2346       Value *v = (g->*proto)[a].get();
2347       const Converter::Location &l = subg->values.l.find(v)->second;
2348       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2349
2350       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2351    }
2352 }
2353
2354 template<typename T> inline void
2355 Converter::BindArgumentsPass::updatePrototype(
2356    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2357 {
2358    (func->*updateSet)();
2359
2360    for (unsigned i = 0; i < set->getSize(); ++i) {
2361       Value *v = func->getLValue(i);
2362
2363       // only include values with a matching TGSI register
2364       if (set->test(i) && sub->values.l.find(v) != sub->values.l.end())
2365          (func->*proto).push_back(v);
2366    }
2367 }
2368
2369 bool
2370 Converter::BindArgumentsPass::visit(Function *f)
2371 {
2372    sub = conv.getSubroutine(f);
2373
2374    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2375         !bi.end(); bi.next()) {
2376       for (Instruction *i = BasicBlock::get(bi)->getFirst();
2377            i; i = i->next) {
2378          if (i->op == OP_CALL && !i->asFlow()->builtin) {
2379             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2380             updateCallArgs(i, &Instruction::setDef, &Function::outs);
2381          }
2382       }
2383    }
2384
2385    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2386       return true;
2387    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2388                    &Function::buildLiveSets, &Function::ins);
2389    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2390                    &Function::buildDefSets, &Function::outs);
2391
2392    return true;
2393 }
2394
2395 bool
2396 Converter::run()
2397 {
2398    BasicBlock *entry = new BasicBlock(prog->main);
2399    BasicBlock *leave = new BasicBlock(prog->main);
2400
2401    prog->main->setEntry(entry);
2402    prog->main->setExit(leave);
2403
2404    setPosition(entry, true);
2405    sub.cur = getSubroutine(prog->main);
2406
2407    if (info->io.genUserClip > 0) {
2408       for (int c = 0; c < 4; ++c)
2409          clipVtx[c] = getScratch();
2410    }
2411
2412    if (prog->getType() == Program::TYPE_FRAGMENT) {
2413       Symbol *sv = mkSysVal(SV_POSITION, 3);
2414       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2415       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2416    }
2417
2418    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2419       if (!handleInstruction(&code->insns[ip]))
2420          return false;
2421    }
2422
2423    if (!BindArgumentsPass(*this).run(prog))
2424       return false;
2425
2426    return true;
2427 }
2428
2429 } // unnamed namespace
2430
2431 namespace nv50_ir {
2432
2433 bool
2434 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2435 {
2436    tgsi::Source src(info);
2437    if (!src.scanSource())
2438       return false;
2439    tlsSize = info->bin.tlsSpace;
2440
2441    Converter builder(this, &src);
2442    return builder.run();
2443 }
2444
2445 } // namespace nv50_ir