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nv50: use larger arrays to silence warnings and fix buffer overflows
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
325 default:
326 assert(0);
327 return nv50_ir::SV_CLOCK;
328 }
329 }
330
331 #define NV50_IR_TEX_TARG_CASE(a, b) \
332 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
333
334 static nv50_ir::TexTarget translateTexture(uint tex)
335 {
336 switch (tex) {
337 NV50_IR_TEX_TARG_CASE(1D, 1D);
338 NV50_IR_TEX_TARG_CASE(2D, 2D);
339 NV50_IR_TEX_TARG_CASE(3D, 3D);
340 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
341 NV50_IR_TEX_TARG_CASE(RECT, RECT);
342 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
344 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
348 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
349 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
350
351 case TGSI_TEXTURE_UNKNOWN:
352 default:
353 assert(!"invalid texture target");
354 return nv50_ir::TEX_TARGET_2D;
355 }
356 }
357
358 nv50_ir::DataType Instruction::inferSrcType() const
359 {
360 switch (getOpcode()) {
361 case TGSI_OPCODE_AND:
362 case TGSI_OPCODE_OR:
363 case TGSI_OPCODE_XOR:
364 case TGSI_OPCODE_U2F:
365 case TGSI_OPCODE_UADD:
366 case TGSI_OPCODE_UDIV:
367 case TGSI_OPCODE_UMOD:
368 case TGSI_OPCODE_UMAD:
369 case TGSI_OPCODE_UMUL:
370 case TGSI_OPCODE_UMAX:
371 case TGSI_OPCODE_UMIN:
372 case TGSI_OPCODE_USEQ:
373 case TGSI_OPCODE_USGE:
374 case TGSI_OPCODE_USLT:
375 case TGSI_OPCODE_USNE:
376 case TGSI_OPCODE_USHR:
377 case TGSI_OPCODE_UCMP:
378 return nv50_ir::TYPE_U32;
379 case TGSI_OPCODE_I2F:
380 case TGSI_OPCODE_IDIV:
381 case TGSI_OPCODE_IMAX:
382 case TGSI_OPCODE_IMIN:
383 case TGSI_OPCODE_IABS:
384 case TGSI_OPCODE_INEG:
385 case TGSI_OPCODE_ISGE:
386 case TGSI_OPCODE_ISHR:
387 case TGSI_OPCODE_ISLT:
388 case TGSI_OPCODE_ISSG:
389 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
390 case TGSI_OPCODE_MOD:
391 case TGSI_OPCODE_UARL:
392 return nv50_ir::TYPE_S32;
393 default:
394 return nv50_ir::TYPE_F32;
395 }
396 }
397
398 nv50_ir::DataType Instruction::inferDstType() const
399 {
400 switch (getOpcode()) {
401 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
402 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
403 case TGSI_OPCODE_I2F:
404 case TGSI_OPCODE_U2F:
405 return nv50_ir::TYPE_F32;
406 default:
407 return inferSrcType();
408 }
409 }
410
411 nv50_ir::CondCode Instruction::getSetCond() const
412 {
413 using namespace nv50_ir;
414
415 switch (getOpcode()) {
416 case TGSI_OPCODE_SLT:
417 case TGSI_OPCODE_ISLT:
418 case TGSI_OPCODE_USLT:
419 return CC_LT;
420 case TGSI_OPCODE_SLE:
421 return CC_LE;
422 case TGSI_OPCODE_SGE:
423 case TGSI_OPCODE_ISGE:
424 case TGSI_OPCODE_USGE:
425 return CC_GE;
426 case TGSI_OPCODE_SGT:
427 return CC_GT;
428 case TGSI_OPCODE_SEQ:
429 case TGSI_OPCODE_USEQ:
430 return CC_EQ;
431 case TGSI_OPCODE_SNE:
432 return CC_NEU;
433 case TGSI_OPCODE_USNE:
434 return CC_NE;
435 case TGSI_OPCODE_SFL:
436 return CC_NEVER;
437 case TGSI_OPCODE_STR:
438 default:
439 return CC_ALWAYS;
440 }
441 }
442
443 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
444
445 static nv50_ir::operation translateOpcode(uint opcode)
446 {
447 switch (opcode) {
448 NV50_IR_OPCODE_CASE(ARL, SHL);
449 NV50_IR_OPCODE_CASE(MOV, MOV);
450
451 NV50_IR_OPCODE_CASE(RCP, RCP);
452 NV50_IR_OPCODE_CASE(RSQ, RSQ);
453
454 NV50_IR_OPCODE_CASE(MUL, MUL);
455 NV50_IR_OPCODE_CASE(ADD, ADD);
456
457 NV50_IR_OPCODE_CASE(MIN, MIN);
458 NV50_IR_OPCODE_CASE(MAX, MAX);
459 NV50_IR_OPCODE_CASE(SLT, SET);
460 NV50_IR_OPCODE_CASE(SGE, SET);
461 NV50_IR_OPCODE_CASE(MAD, MAD);
462 NV50_IR_OPCODE_CASE(SUB, SUB);
463
464 NV50_IR_OPCODE_CASE(FLR, FLOOR);
465 NV50_IR_OPCODE_CASE(ROUND, CVT);
466 NV50_IR_OPCODE_CASE(EX2, EX2);
467 NV50_IR_OPCODE_CASE(LG2, LG2);
468 NV50_IR_OPCODE_CASE(POW, POW);
469
470 NV50_IR_OPCODE_CASE(ABS, ABS);
471
472 NV50_IR_OPCODE_CASE(COS, COS);
473 NV50_IR_OPCODE_CASE(DDX, DFDX);
474 NV50_IR_OPCODE_CASE(DDY, DFDY);
475 NV50_IR_OPCODE_CASE(KILP, DISCARD);
476
477 NV50_IR_OPCODE_CASE(SEQ, SET);
478 NV50_IR_OPCODE_CASE(SFL, SET);
479 NV50_IR_OPCODE_CASE(SGT, SET);
480 NV50_IR_OPCODE_CASE(SIN, SIN);
481 NV50_IR_OPCODE_CASE(SLE, SET);
482 NV50_IR_OPCODE_CASE(SNE, SET);
483 NV50_IR_OPCODE_CASE(STR, SET);
484 NV50_IR_OPCODE_CASE(TEX, TEX);
485 NV50_IR_OPCODE_CASE(TXD, TXD);
486 NV50_IR_OPCODE_CASE(TXP, TEX);
487
488 NV50_IR_OPCODE_CASE(BRA, BRA);
489 NV50_IR_OPCODE_CASE(CAL, CALL);
490 NV50_IR_OPCODE_CASE(RET, RET);
491 NV50_IR_OPCODE_CASE(CMP, SLCT);
492
493 NV50_IR_OPCODE_CASE(TXB, TXB);
494
495 NV50_IR_OPCODE_CASE(DIV, DIV);
496
497 NV50_IR_OPCODE_CASE(TXL, TXL);
498
499 NV50_IR_OPCODE_CASE(CEIL, CEIL);
500 NV50_IR_OPCODE_CASE(I2F, CVT);
501 NV50_IR_OPCODE_CASE(NOT, NOT);
502 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
503 NV50_IR_OPCODE_CASE(SHL, SHL);
504
505 NV50_IR_OPCODE_CASE(AND, AND);
506 NV50_IR_OPCODE_CASE(OR, OR);
507 NV50_IR_OPCODE_CASE(MOD, MOD);
508 NV50_IR_OPCODE_CASE(XOR, XOR);
509 NV50_IR_OPCODE_CASE(SAD, SAD);
510 NV50_IR_OPCODE_CASE(TXF, TXF);
511 NV50_IR_OPCODE_CASE(TXQ, TXQ);
512
513 NV50_IR_OPCODE_CASE(EMIT, EMIT);
514 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
515
516 NV50_IR_OPCODE_CASE(KIL, DISCARD);
517
518 NV50_IR_OPCODE_CASE(F2I, CVT);
519 NV50_IR_OPCODE_CASE(IDIV, DIV);
520 NV50_IR_OPCODE_CASE(IMAX, MAX);
521 NV50_IR_OPCODE_CASE(IMIN, MIN);
522 NV50_IR_OPCODE_CASE(IABS, ABS);
523 NV50_IR_OPCODE_CASE(INEG, NEG);
524 NV50_IR_OPCODE_CASE(ISGE, SET);
525 NV50_IR_OPCODE_CASE(ISHR, SHR);
526 NV50_IR_OPCODE_CASE(ISLT, SET);
527 NV50_IR_OPCODE_CASE(F2U, CVT);
528 NV50_IR_OPCODE_CASE(U2F, CVT);
529 NV50_IR_OPCODE_CASE(UADD, ADD);
530 NV50_IR_OPCODE_CASE(UDIV, DIV);
531 NV50_IR_OPCODE_CASE(UMAD, MAD);
532 NV50_IR_OPCODE_CASE(UMAX, MAX);
533 NV50_IR_OPCODE_CASE(UMIN, MIN);
534 NV50_IR_OPCODE_CASE(UMOD, MOD);
535 NV50_IR_OPCODE_CASE(UMUL, MUL);
536 NV50_IR_OPCODE_CASE(USEQ, SET);
537 NV50_IR_OPCODE_CASE(USGE, SET);
538 NV50_IR_OPCODE_CASE(USHR, SHR);
539 NV50_IR_OPCODE_CASE(USLT, SET);
540 NV50_IR_OPCODE_CASE(USNE, SET);
541
542 NV50_IR_OPCODE_CASE(LOAD, TXF);
543 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
544 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
545 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
546 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
547 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
548 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
549 NV50_IR_OPCODE_CASE(GATHER4, TXG);
550 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
551
552 NV50_IR_OPCODE_CASE(END, EXIT);
553
554 default:
555 return nv50_ir::OP_NOP;
556 }
557 }
558
559 bool Instruction::checkDstSrcAliasing() const
560 {
561 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
562 return false;
563
564 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
565 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
566 break;
567 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
568 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
569 return true;
570 }
571 return false;
572 }
573
574 class Source
575 {
576 public:
577 Source(struct nv50_ir_prog_info *);
578 ~Source();
579
580 struct Subroutine
581 {
582 unsigned pc;
583 };
584
585 public:
586 bool scanSource();
587 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
588
589 public:
590 struct tgsi_shader_info scan;
591 struct tgsi_full_instruction *insns;
592 const struct tgsi_token *tokens;
593 struct nv50_ir_prog_info *info;
594
595 nv50_ir::DynArray tempArrays;
596 nv50_ir::DynArray immdArrays;
597 int tempArrayCount;
598 int immdArrayCount;
599
600 bool mainTempsInLMem;
601
602 int clipVertexOutput;
603
604 uint8_t *resourceTargets; // TGSI_TEXTURE_*
605 unsigned resourceCount;
606
607 Subroutine *subroutines;
608 unsigned subroutineCount;
609
610 private:
611 int inferSysValDirection(unsigned sn) const;
612 bool scanDeclaration(const struct tgsi_full_declaration *);
613 bool scanInstruction(const struct tgsi_full_instruction *);
614 void scanProperty(const struct tgsi_full_property *);
615 void scanImmediate(const struct tgsi_full_immediate *);
616
617 inline bool isEdgeFlagPassthrough(const Instruction&) const;
618 };
619
620 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
621 {
622 tokens = (const struct tgsi_token *)info->bin.source;
623
624 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
625 tgsi_dump(tokens, 0);
626
627 resourceTargets = NULL;
628 subroutines = NULL;
629
630 mainTempsInLMem = FALSE;
631 }
632
633 Source::~Source()
634 {
635 if (insns)
636 FREE(insns);
637
638 if (info->immd.data)
639 FREE(info->immd.data);
640 if (info->immd.type)
641 FREE(info->immd.type);
642
643 if (resourceTargets)
644 delete[] resourceTargets;
645 if (subroutines)
646 delete[] subroutines;
647 }
648
649 bool Source::scanSource()
650 {
651 unsigned insnCount = 0;
652 unsigned subrCount = 0;
653 struct tgsi_parse_context parse;
654
655 tgsi_scan_shader(tokens, &scan);
656
657 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
658 sizeof(insns[0]));
659 if (!insns)
660 return false;
661
662 clipVertexOutput = -1;
663
664 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
665 resourceTargets = new uint8_t[resourceCount];
666
667 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
668 subroutines = new Subroutine[subroutineCount];
669
670 info->immd.bufSize = 0;
671 tempArrayCount = 0;
672 immdArrayCount = 0;
673
674 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
675 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
676 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
677
678 if (info->type == PIPE_SHADER_FRAGMENT) {
679 info->prop.fp.writesDepth = scan.writes_z;
680 info->prop.fp.usesDiscard = scan.uses_kill;
681 } else
682 if (info->type == PIPE_SHADER_GEOMETRY) {
683 info->prop.gp.instanceCount = 1; // default value
684 }
685
686 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
687 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
688
689 tgsi_parse_init(&parse, tokens);
690 while (!tgsi_parse_end_of_tokens(&parse)) {
691 tgsi_parse_token(&parse);
692
693 switch (parse.FullToken.Token.Type) {
694 case TGSI_TOKEN_TYPE_IMMEDIATE:
695 scanImmediate(&parse.FullToken.FullImmediate);
696 break;
697 case TGSI_TOKEN_TYPE_DECLARATION:
698 scanDeclaration(&parse.FullToken.FullDeclaration);
699 break;
700 case TGSI_TOKEN_TYPE_INSTRUCTION:
701 insns[insnCount++] = parse.FullToken.FullInstruction;
702 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
703 subroutines[++subrCount].pc = insnCount - 1;
704 else
705 scanInstruction(&parse.FullToken.FullInstruction);
706 break;
707 case TGSI_TOKEN_TYPE_PROPERTY:
708 scanProperty(&parse.FullToken.FullProperty);
709 break;
710 default:
711 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
712 break;
713 }
714 }
715 tgsi_parse_free(&parse);
716
717 if (mainTempsInLMem)
718 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
719
720 if (info->io.genUserClip > 0)
721 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
722
723 return info->assignSlots(info) == 0;
724 }
725
726 void Source::scanProperty(const struct tgsi_full_property *prop)
727 {
728 switch (prop->Property.PropertyName) {
729 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
730 info->prop.gp.outputPrim = prop->u[0].Data;
731 break;
732 case TGSI_PROPERTY_GS_INPUT_PRIM:
733 info->prop.gp.inputPrim = prop->u[0].Data;
734 break;
735 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
736 info->prop.gp.maxVertices = prop->u[0].Data;
737 break;
738 #if 0
739 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
740 info->prop.gp.instanceCount = prop->u[0].Data;
741 break;
742 #endif
743 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
744 info->prop.fp.separateFragData = TRUE;
745 break;
746 case TGSI_PROPERTY_FS_COORD_ORIGIN:
747 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
748 // we don't care
749 break;
750 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
751 info->io.genUserClip = -1;
752 break;
753 default:
754 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
755 break;
756 }
757 }
758
759 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
760 {
761 const unsigned n = info->immd.count++;
762
763 assert(n < scan.immediate_count);
764
765 for (int c = 0; c < 4; ++c)
766 info->immd.data[n * 4 + c] = imm->u[c].Uint;
767
768 info->immd.type[n] = imm->Immediate.DataType;
769 }
770
771 int Source::inferSysValDirection(unsigned sn) const
772 {
773 switch (sn) {
774 case TGSI_SEMANTIC_INSTANCEID:
775 case TGSI_SEMANTIC_VERTEXID:
776 return 1;
777 #if 0
778 case TGSI_SEMANTIC_LAYER:
779 case TGSI_SEMANTIC_VIEWPORTINDEX:
780 return 0;
781 #endif
782 case TGSI_SEMANTIC_PRIMID:
783 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
784 default:
785 return 0;
786 }
787 }
788
789 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
790 {
791 unsigned i;
792 unsigned sn = TGSI_SEMANTIC_GENERIC;
793 unsigned si = 0;
794 const unsigned first = decl->Range.First, last = decl->Range.Last;
795
796 if (decl->Declaration.Semantic) {
797 sn = decl->Semantic.Name;
798 si = decl->Semantic.Index;
799 }
800
801 switch (decl->Declaration.File) {
802 case TGSI_FILE_INPUT:
803 if (info->type == PIPE_SHADER_VERTEX) {
804 // all vertex attributes are equal
805 for (i = first; i <= last; ++i) {
806 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
807 info->in[i].si = i;
808 }
809 } else {
810 for (i = first; i <= last; ++i, ++si) {
811 info->in[i].id = i;
812 info->in[i].sn = sn;
813 info->in[i].si = si;
814 if (info->type == PIPE_SHADER_FRAGMENT) {
815 // translate interpolation mode
816 switch (decl->Declaration.Interpolate) {
817 case TGSI_INTERPOLATE_CONSTANT:
818 info->in[i].flat = 1;
819 break;
820 case TGSI_INTERPOLATE_COLOR:
821 info->in[i].sc = 1;
822 break;
823 case TGSI_INTERPOLATE_LINEAR:
824 info->in[i].linear = 1;
825 break;
826 default:
827 break;
828 }
829 if (decl->Declaration.Centroid)
830 info->in[i].centroid = 1;
831 }
832 }
833 }
834 break;
835 case TGSI_FILE_OUTPUT:
836 for (i = first; i <= last; ++i, ++si) {
837 switch (sn) {
838 case TGSI_SEMANTIC_POSITION:
839 if (info->type == PIPE_SHADER_FRAGMENT)
840 info->io.fragDepth = i;
841 else
842 if (clipVertexOutput < 0)
843 clipVertexOutput = i;
844 break;
845 case TGSI_SEMANTIC_COLOR:
846 if (info->type == PIPE_SHADER_FRAGMENT)
847 info->prop.fp.numColourResults++;
848 break;
849 case TGSI_SEMANTIC_EDGEFLAG:
850 info->io.edgeFlagOut = i;
851 break;
852 case TGSI_SEMANTIC_CLIPVERTEX:
853 clipVertexOutput = i;
854 break;
855 case TGSI_SEMANTIC_CLIPDIST:
856 info->io.clipDistanceMask |=
857 decl->Declaration.UsageMask << (si * 4);
858 info->io.genUserClip = -1;
859 break;
860 default:
861 break;
862 }
863 info->out[i].id = i;
864 info->out[i].sn = sn;
865 info->out[i].si = si;
866 }
867 break;
868 case TGSI_FILE_SYSTEM_VALUE:
869 switch (sn) {
870 case TGSI_SEMANTIC_VERTEXID:
871 info->io.vertexId = first;
872 break;
873 default:
874 break;
875 }
876 for (i = first; i <= last; ++i, ++si) {
877 info->sv[i].sn = sn;
878 info->sv[i].si = si;
879 info->sv[i].input = inferSysValDirection(sn);
880 }
881 break;
882 case TGSI_FILE_RESOURCE:
883 for (i = first; i <= last; ++i)
884 resourceTargets[i] = decl->Resource.Resource;
885 break;
886 case TGSI_FILE_IMMEDIATE_ARRAY:
887 {
888 if (decl->Dim.Index2D >= immdArrayCount)
889 immdArrayCount = decl->Dim.Index2D + 1;
890 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
891 int c;
892 uint32_t base, count;
893 switch (decl->Declaration.UsageMask) {
894 case 0x1: c = 1; break;
895 case 0x3: c = 2; break;
896 default:
897 c = 4;
898 break;
899 }
900 immdArrays[decl->Dim.Index2D].u32 |= c;
901 count = (last + 1) * c;
902 base = info->immd.bufSize / 4;
903 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
904 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
905 info->immd.bufSize);
906 // NOTE: this assumes array declarations are ordered by Dim.Index2D
907 for (i = 0; i < count; ++i)
908 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
909 }
910 break;
911 case TGSI_FILE_TEMPORARY_ARRAY:
912 {
913 if (decl->Dim.Index2D >= tempArrayCount)
914 tempArrayCount = decl->Dim.Index2D + 1;
915 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
916 int c;
917 uint32_t count;
918 switch (decl->Declaration.UsageMask) {
919 case 0x1: c = 1; break;
920 case 0x3: c = 2; break;
921 default:
922 c = 4;
923 break;
924 }
925 tempArrays[decl->Dim.Index2D].u32 |= c;
926 count = (last + 1) * c;
927 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
928 }
929 break;
930 case TGSI_FILE_NULL:
931 case TGSI_FILE_TEMPORARY:
932 case TGSI_FILE_ADDRESS:
933 case TGSI_FILE_CONSTANT:
934 case TGSI_FILE_IMMEDIATE:
935 case TGSI_FILE_PREDICATE:
936 case TGSI_FILE_SAMPLER:
937 break;
938 default:
939 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
940 return false;
941 }
942 return true;
943 }
944
945 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
946 {
947 return insn.getOpcode() == TGSI_OPCODE_MOV &&
948 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
949 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
950 }
951
952 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
953 {
954 Instruction insn(inst);
955
956 if (insn.dstCount()) {
957 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
958 Instruction::DstRegister dst = insn.getDst(0);
959
960 if (dst.isIndirect(0))
961 for (unsigned i = 0; i < info->numOutputs; ++i)
962 info->out[i].mask = 0xf;
963 else
964 info->out[dst.getIndex(0)].mask |= dst.getMask();
965
966 if (isEdgeFlagPassthrough(insn))
967 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
968 } else
969 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
970 if (insn.getDst(0).isIndirect(0))
971 mainTempsInLMem = TRUE;
972 }
973 }
974
975 for (unsigned s = 0; s < insn.srcCount(); ++s) {
976 Instruction::SrcRegister src = insn.getSrc(s);
977 if (src.getFile() == TGSI_FILE_TEMPORARY)
978 if (src.isIndirect(0))
979 mainTempsInLMem = TRUE;
980 if (src.getFile() != TGSI_FILE_INPUT)
981 continue;
982 unsigned mask = insn.srcMask(s);
983
984 if (src.isIndirect(0)) {
985 for (unsigned i = 0; i < info->numInputs; ++i)
986 info->in[i].mask = 0xf;
987 } else {
988 for (unsigned c = 0; c < 4; ++c) {
989 if (!(mask & (1 << c)))
990 continue;
991 int k = src.getSwizzle(c);
992 int i = src.getIndex(0);
993 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
994 if (k <= TGSI_SWIZZLE_W)
995 info->in[i].mask |= 1 << k;
996 }
997 }
998 }
999 return true;
1000 }
1001
1002 nv50_ir::TexInstruction::Target
1003 Instruction::getTexture(const tgsi::Source *code, int s) const
1004 {
1005 if (insn->Instruction.Texture) {
1006 return translateTexture(insn->Texture.Texture);
1007 } else {
1008 // XXX: indirect access
1009 unsigned int r = getSrc(s).getIndex(0);
1010 assert(r < code->resourceCount);
1011 return translateTexture(code->resourceTargets[r]);
1012 }
1013 }
1014
1015 } // namespace tgsi
1016
1017 namespace {
1018
1019 using namespace nv50_ir;
1020
1021 class Converter : public BuildUtil
1022 {
1023 public:
1024 Converter(Program *, const tgsi::Source *);
1025 ~Converter();
1026
1027 bool run();
1028
1029 private:
1030 Value *getVertexBase(int s);
1031 Value *fetchSrc(int s, int c);
1032 Value *acquireDst(int d, int c);
1033 void storeDst(int d, int c, Value *);
1034
1035 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1036 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1037 Value *val, Value *ptr);
1038
1039 Value *applySrcMod(Value *, int s, int c);
1040
1041 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1042 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1043 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1044
1045 bool handleInstruction(const struct tgsi_full_instruction *);
1046 void exportOutputs();
1047 inline bool isEndOfSubroutine(uint ip);
1048
1049 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1050
1051 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1052 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1053 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1054 void handleTXF(Value *dst0[4], int R);
1055 void handleTXQ(Value *dst0[4], enum TexQuery);
1056 void handleLIT(Value *dst0[4]);
1057 void handleUserClipPlanes();
1058
1059 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1060
1061 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1062
1063 Value *buildDot(int dim);
1064
1065 private:
1066 const struct tgsi::Source *code;
1067 const struct nv50_ir_prog_info *info;
1068
1069 uint ip; // instruction pointer
1070
1071 tgsi::Instruction tgsi;
1072
1073 DataType dstTy;
1074 DataType srcTy;
1075
1076 DataArray tData; // TGSI_FILE_TEMPORARY
1077 DataArray aData; // TGSI_FILE_ADDRESS
1078 DataArray pData; // TGSI_FILE_PREDICATE
1079 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1080 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1081 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1082
1083 Value *zero;
1084 Value *fragCoord[4];
1085 Value *clipVtx[4];
1086
1087 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1088 uint8_t vtxBaseValid;
1089
1090 Stack condBBs; // fork BB, then else clause BB
1091 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1092 Stack loopBBs; // loop headers
1093 Stack breakBBs; // end of / after loop
1094 Stack entryBBs; // start of current (inlined) subroutine
1095 Stack leaveBBs; // end of current (inlined) subroutine
1096 Stack retIPs; // return instruction pointer
1097 };
1098
1099 Symbol *
1100 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1101 {
1102 const int swz = src.getSwizzle(c);
1103
1104 return makeSym(src.getFile(),
1105 src.is2D() ? src.getIndex(1) : 0,
1106 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1107 src.getIndex(0) * 16 + swz * 4);
1108 }
1109
1110 Symbol *
1111 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1112 {
1113 return makeSym(dst.getFile(),
1114 dst.is2D() ? dst.getIndex(1) : 0,
1115 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1116 dst.getIndex(0) * 16 + c * 4);
1117 }
1118
1119 Symbol *
1120 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1121 {
1122 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1123
1124 sym->reg.fileIndex = fileIdx;
1125
1126 if (idx >= 0) {
1127 if (sym->reg.file == FILE_SHADER_INPUT)
1128 sym->setOffset(info->in[idx].slot[c] * 4);
1129 else
1130 if (sym->reg.file == FILE_SHADER_OUTPUT)
1131 sym->setOffset(info->out[idx].slot[c] * 4);
1132 else
1133 if (sym->reg.file == FILE_SYSTEM_VALUE)
1134 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1135 else
1136 sym->setOffset(address);
1137 } else {
1138 sym->setOffset(address);
1139 }
1140 return sym;
1141 }
1142
1143 static inline uint8_t
1144 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1145 {
1146 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1147
1148 if (var->flat)
1149 mode = NV50_IR_INTERP_FLAT;
1150 else
1151 if (var->linear)
1152 mode = NV50_IR_INTERP_LINEAR;
1153 else
1154 if (var->sc)
1155 mode = NV50_IR_INTERP_SC;
1156
1157 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1158 ? OP_PINTERP : OP_LINTERP;
1159
1160 if (var->centroid)
1161 mode |= NV50_IR_INTERP_CENTROID;
1162
1163 return mode;
1164 }
1165
1166 Value *
1167 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1168 {
1169 operation op;
1170
1171 // XXX: no way to know interpolation mode if we don't know what's accessed
1172 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1173 src.getIndex(0)], op);
1174
1175 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1176
1177 insn->setDef(0, getScratch());
1178 insn->setSrc(0, srcToSym(src, c));
1179 if (op == OP_PINTERP)
1180 insn->setSrc(1, fragCoord[3]);
1181 if (ptr)
1182 insn->setIndirect(0, 0, ptr);
1183
1184 insn->setInterpolate(mode);
1185
1186 bb->insertTail(insn);
1187 return insn->getDef(0);
1188 }
1189
1190 Value *
1191 Converter::applySrcMod(Value *val, int s, int c)
1192 {
1193 Modifier m = tgsi.getSrc(s).getMod(c);
1194 DataType ty = tgsi.inferSrcType();
1195
1196 if (m & Modifier(NV50_IR_MOD_ABS))
1197 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1198
1199 if (m & Modifier(NV50_IR_MOD_NEG))
1200 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1201
1202 return val;
1203 }
1204
1205 Value *
1206 Converter::getVertexBase(int s)
1207 {
1208 assert(s < 5);
1209 if (!(vtxBaseValid & (1 << s))) {
1210 const int index = tgsi.getSrc(s).getIndex(1);
1211 Value *rel = NULL;
1212 if (tgsi.getSrc(s).isIndirect(1))
1213 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1214 vtxBaseValid |= 1 << s;
1215 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1216 }
1217 return vtxBase[s];
1218 }
1219
1220 Value *
1221 Converter::fetchSrc(int s, int c)
1222 {
1223 Value *res;
1224 Value *ptr = NULL, *dimRel = NULL;
1225
1226 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1227
1228 if (src.isIndirect(0))
1229 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1230
1231 if (src.is2D()) {
1232 switch (src.getFile()) {
1233 case TGSI_FILE_INPUT:
1234 dimRel = getVertexBase(s);
1235 break;
1236 case TGSI_FILE_CONSTANT:
1237 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1238 if (src.isIndirect(1))
1239 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1240 break;
1241 default:
1242 break;
1243 }
1244 }
1245
1246 res = fetchSrc(src, c, ptr);
1247
1248 if (dimRel)
1249 res->getInsn()->setIndirect(0, 1, dimRel);
1250
1251 return applySrcMod(res, s, c);
1252 }
1253
1254 Value *
1255 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1256 {
1257 const int idx = src.getIndex(0);
1258 const int swz = src.getSwizzle(c);
1259
1260 switch (src.getFile()) {
1261 case TGSI_FILE_TEMPORARY:
1262 return tData.load(idx, swz, ptr);
1263 case TGSI_FILE_PREDICATE:
1264 return pData.load(idx, swz, ptr);
1265 case TGSI_FILE_ADDRESS:
1266 return aData.load(idx, swz, ptr);
1267
1268 case TGSI_FILE_TEMPORARY_ARRAY:
1269 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1270 return lData[src.getIndex(1)].load(idx, swz, ptr);
1271 case TGSI_FILE_IMMEDIATE_ARRAY:
1272 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1273 return iData[src.getIndex(1)].load(idx, swz, ptr);
1274
1275 case TGSI_FILE_IMMEDIATE:
1276 assert(!ptr);
1277 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1278
1279 case TGSI_FILE_CONSTANT:
1280 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1281
1282 case TGSI_FILE_INPUT:
1283 if (prog->getType() == Program::TYPE_FRAGMENT) {
1284 // don't load masked inputs, won't be assigned a slot
1285 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1286 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1287 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1288 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1289 return interpolate(src, c, ptr);
1290 }
1291 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1292
1293 case TGSI_FILE_SYSTEM_VALUE:
1294 assert(!ptr);
1295 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1296
1297 case TGSI_FILE_OUTPUT:
1298 case TGSI_FILE_RESOURCE:
1299 case TGSI_FILE_SAMPLER:
1300 case TGSI_FILE_NULL:
1301 default:
1302 assert(!"invalid/unhandled TGSI source file");
1303 return NULL;
1304 }
1305 }
1306
1307 Value *
1308 Converter::acquireDst(int d, int c)
1309 {
1310 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1311
1312 if (dst.isMasked(c))
1313 return NULL;
1314 if (dst.isIndirect(0))
1315 return getScratch();
1316
1317 const int idx = dst.getIndex(0);
1318
1319 switch (dst.getFile()) {
1320 case TGSI_FILE_TEMPORARY:
1321 return tData.acquire(idx, c);
1322 case TGSI_FILE_TEMPORARY_ARRAY:
1323 return getScratch();
1324 case TGSI_FILE_PREDICATE:
1325 return pData.acquire(idx, c);
1326 case TGSI_FILE_ADDRESS:
1327 return aData.acquire(idx, c);
1328
1329 case TGSI_FILE_OUTPUT:
1330 if (prog->getType() == Program::TYPE_FRAGMENT)
1331 return oData.acquire(idx, c);
1332 // fall through
1333 case TGSI_FILE_SYSTEM_VALUE:
1334 return getScratch();
1335
1336 default:
1337 assert(!"invalid dst file");
1338 return NULL;
1339 }
1340 }
1341
1342 void
1343 Converter::storeDst(int d, int c, Value *val)
1344 {
1345 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1346
1347 switch (tgsi.getSaturate()) {
1348 case TGSI_SAT_NONE:
1349 break;
1350 case TGSI_SAT_ZERO_ONE:
1351 mkOp1(OP_SAT, dstTy, val, val);
1352 break;
1353 case TGSI_SAT_MINUS_PLUS_ONE:
1354 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1355 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1356 break;
1357 default:
1358 assert(!"invalid saturation mode");
1359 break;
1360 }
1361
1362 Value *ptr = dst.isIndirect(0) ?
1363 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1364
1365 if (info->io.genUserClip > 0 &&
1366 dst.getFile() == TGSI_FILE_OUTPUT &&
1367 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1368 mkMov(clipVtx[c], val);
1369 val = clipVtx[c];
1370 }
1371
1372 storeDst(dst, c, val, ptr);
1373 }
1374
1375 void
1376 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1377 Value *val, Value *ptr)
1378 {
1379 const int idx = dst.getIndex(0);
1380
1381 switch (dst.getFile()) {
1382 case TGSI_FILE_TEMPORARY:
1383 tData.store(idx, c, ptr, val);
1384 break;
1385 case TGSI_FILE_TEMPORARY_ARRAY:
1386 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1387 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1388 break;
1389 case TGSI_FILE_PREDICATE:
1390 pData.store(idx, c, ptr, val);
1391 break;
1392 case TGSI_FILE_ADDRESS:
1393 aData.store(idx, c, ptr, val);
1394 break;
1395
1396 case TGSI_FILE_OUTPUT:
1397 if (prog->getType() == Program::TYPE_FRAGMENT)
1398 oData.store(idx, c, ptr, val);
1399 else
1400 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1401 break;
1402
1403 case TGSI_FILE_SYSTEM_VALUE:
1404 assert(!ptr);
1405 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1406 break;
1407
1408 default:
1409 assert(!"invalid dst file");
1410 break;
1411 }
1412 }
1413
1414 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1415 for (chan = 0; chan < 4; ++chan) \
1416 if (!inst.getDst(d).isMasked(chan))
1417
1418 Value *
1419 Converter::buildDot(int dim)
1420 {
1421 assert(dim > 0);
1422
1423 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1424 Value *dotp = getScratch();
1425
1426 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1427
1428 for (int c = 1; c < dim; ++c) {
1429 src0 = fetchSrc(0, c);
1430 src1 = fetchSrc(1, c);
1431 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1432 }
1433 return dotp;
1434 }
1435
1436 void
1437 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1438 {
1439 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1440 join->fixed = 1;
1441 conv->insertHead(join);
1442
1443 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1444 fork->insertBefore(fork->getExit(), fork->joinAt);
1445 }
1446
1447 void
1448 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1449 {
1450 unsigned rIdx = 0, sIdx = 0;
1451
1452 if (R >= 0)
1453 rIdx = tgsi.getSrc(R).getIndex(0);
1454 if (S >= 0)
1455 sIdx = tgsi.getSrc(S).getIndex(0);
1456
1457 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1458
1459 if (tgsi.getSrc(R).isIndirect(0)) {
1460 tex->tex.rIndirectSrc = s;
1461 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1462 }
1463 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1464 tex->tex.sIndirectSrc = s;
1465 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1466 }
1467 }
1468
1469 void
1470 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1471 {
1472 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1473 tex->tex.query = query;
1474 unsigned int c, d;
1475
1476 for (d = 0, c = 0; c < 4; ++c) {
1477 if (!dst0[c])
1478 continue;
1479 tex->tex.mask |= 1 << c;
1480 tex->setDef(d++, dst0[c]);
1481 }
1482 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1483
1484 setTexRS(tex, c, 1, -1);
1485
1486 bb->insertTail(tex);
1487 }
1488
1489 void
1490 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1491 {
1492 Value *proj = fetchSrc(0, 3);
1493 Instruction *insn = proj->getUniqueInsn();
1494 int c;
1495
1496 if (insn->op == OP_PINTERP) {
1497 bb->insertTail(insn = insn->clone(true));
1498 insn->op = OP_LINTERP;
1499 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1500 insn->setSrc(1, NULL);
1501 proj = insn->getDef(0);
1502 }
1503 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1504
1505 for (c = 0; c < 4; ++c) {
1506 if (!(mask & (1 << c)))
1507 continue;
1508 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1509 continue;
1510 mask &= ~(1 << c);
1511
1512 bb->insertTail(insn = insn->clone(true));
1513 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1514 insn->setSrc(1, proj);
1515 dst[c] = insn->getDef(0);
1516 }
1517 if (!mask)
1518 return;
1519
1520 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1521
1522 for (c = 0; c < 4; ++c)
1523 if (mask & (1 << c))
1524 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1525 }
1526
1527 // order of nv50 ir sources: x y z layer lod/bias shadow
1528 // order of TGSI TEX sources: x y z layer shadow lod/bias
1529 // lowering will finally set the hw specific order (like array first on nvc0)
1530 void
1531 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1532 {
1533 Value *val;
1534 Value *arg[4], *src[8];
1535 Value *lod = NULL, *shd = NULL;
1536 unsigned int s, c, d;
1537 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1538
1539 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1540
1541 for (s = 0; s < tgt.getArgCount(); ++s)
1542 arg[s] = src[s] = fetchSrc(0, s);
1543
1544 if (texi->op == OP_TXL || texi->op == OP_TXB)
1545 lod = fetchSrc(L >> 4, L & 3);
1546
1547 if (C == 0x0f)
1548 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1549
1550 if (tgt.isShadow())
1551 shd = fetchSrc(C >> 4, C & 3);
1552
1553 if (texi->op == OP_TXD) {
1554 for (c = 0; c < tgt.getDim(); ++c) {
1555 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1556 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1557 }
1558 }
1559
1560 // cube textures don't care about projection value, it's divided out
1561 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1562 unsigned int n = tgt.getDim();
1563 if (shd) {
1564 arg[n] = shd;
1565 ++n;
1566 assert(tgt.getDim() == tgt.getArgCount());
1567 }
1568 loadProjTexCoords(src, arg, (1 << n) - 1);
1569 if (shd)
1570 shd = src[n - 1];
1571 }
1572
1573 if (tgt.isCube()) {
1574 for (c = 0; c < 3; ++c)
1575 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1576 val = getScratch();
1577 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1578 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1579 mkOp1(OP_RCP, TYPE_F32, val, val);
1580 for (c = 0; c < 3; ++c)
1581 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1582 }
1583
1584 for (c = 0, d = 0; c < 4; ++c) {
1585 if (dst[c]) {
1586 texi->setDef(d++, dst[c]);
1587 texi->tex.mask |= 1 << c;
1588 } else {
1589 // NOTE: maybe hook up def too, for CSE
1590 }
1591 }
1592 for (s = 0; s < tgt.getArgCount(); ++s)
1593 texi->setSrc(s, src[s]);
1594 if (lod)
1595 texi->setSrc(s++, lod);
1596 if (shd)
1597 texi->setSrc(s++, shd);
1598
1599 setTexRS(texi, s, R, S);
1600
1601 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1602 texi->tex.levelZero = true;
1603
1604 bb->insertTail(texi);
1605 }
1606
1607 // 1st source: xyz = coordinates, w = lod
1608 // 2nd source: offset
1609 void
1610 Converter::handleTXF(Value *dst[4], int R)
1611 {
1612 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1613 unsigned int c, d, s;
1614
1615 texi->tex.target = tgsi.getTexture(code, R);
1616
1617 for (c = 0, d = 0; c < 4; ++c) {
1618 if (dst[c]) {
1619 texi->setDef(d++, dst[c]);
1620 texi->tex.mask |= 1 << c;
1621 }
1622 }
1623 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1624 texi->setSrc(c, fetchSrc(0, c));
1625 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1626
1627 setTexRS(texi, c, R, -1);
1628
1629 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1630 for (c = 0; c < 3; ++c) {
1631 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1632 if (texi->tex.offset[s][c])
1633 texi->tex.useOffsets = s + 1;
1634 }
1635 }
1636
1637 bb->insertTail(texi);
1638 }
1639
1640 void
1641 Converter::handleLIT(Value *dst0[4])
1642 {
1643 Value *val0 = NULL;
1644 unsigned int mask = tgsi.getDst(0).getMask();
1645
1646 if (mask & (1 << 0))
1647 loadImm(dst0[0], 1.0f);
1648
1649 if (mask & (1 << 3))
1650 loadImm(dst0[3], 1.0f);
1651
1652 if (mask & (3 << 1)) {
1653 val0 = getScratch();
1654 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1655 if (mask & (1 << 1))
1656 mkMov(dst0[1], val0);
1657 }
1658
1659 if (mask & (1 << 2)) {
1660 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1661 Value *val1 = getScratch(), *val3 = getScratch();
1662
1663 Value *pos128 = loadImm(NULL, +127.999999f);
1664 Value *neg128 = loadImm(NULL, -127.999999f);
1665
1666 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1667 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1668 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1669 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1670
1671 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1672 }
1673 }
1674
1675 bool
1676 Converter::isEndOfSubroutine(uint ip)
1677 {
1678 assert(ip < code->scan.num_instructions);
1679 tgsi::Instruction insn(&code->insns[ip]);
1680 return (insn.getOpcode() == TGSI_OPCODE_END ||
1681 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1682 // does END occur at end of main or the very end ?
1683 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1684 }
1685
1686 bool
1687 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1688 {
1689 Value *dst0[4], *rDst0[4];
1690 Value *src0, *src1, *src2;
1691 Value *val0, *val1;
1692 int c;
1693
1694 tgsi = tgsi::Instruction(insn);
1695
1696 bool useScratchDst = tgsi.checkDstSrcAliasing();
1697
1698 operation op = tgsi.getOP();
1699 dstTy = tgsi.inferDstType();
1700 srcTy = tgsi.inferSrcType();
1701
1702 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1703
1704 if (tgsi.dstCount()) {
1705 for (c = 0; c < 4; ++c) {
1706 rDst0[c] = acquireDst(0, c);
1707 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1708 }
1709 }
1710
1711 switch (tgsi.getOpcode()) {
1712 case TGSI_OPCODE_ADD:
1713 case TGSI_OPCODE_UADD:
1714 case TGSI_OPCODE_AND:
1715 case TGSI_OPCODE_DIV:
1716 case TGSI_OPCODE_IDIV:
1717 case TGSI_OPCODE_UDIV:
1718 case TGSI_OPCODE_MAX:
1719 case TGSI_OPCODE_MIN:
1720 case TGSI_OPCODE_IMAX:
1721 case TGSI_OPCODE_IMIN:
1722 case TGSI_OPCODE_UMAX:
1723 case TGSI_OPCODE_UMIN:
1724 case TGSI_OPCODE_MOD:
1725 case TGSI_OPCODE_UMOD:
1726 case TGSI_OPCODE_MUL:
1727 case TGSI_OPCODE_UMUL:
1728 case TGSI_OPCODE_OR:
1729 case TGSI_OPCODE_POW:
1730 case TGSI_OPCODE_SHL:
1731 case TGSI_OPCODE_ISHR:
1732 case TGSI_OPCODE_USHR:
1733 case TGSI_OPCODE_SUB:
1734 case TGSI_OPCODE_XOR:
1735 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1736 src0 = fetchSrc(0, c);
1737 src1 = fetchSrc(1, c);
1738 mkOp2(op, dstTy, dst0[c], src0, src1);
1739 }
1740 break;
1741 case TGSI_OPCODE_MAD:
1742 case TGSI_OPCODE_UMAD:
1743 case TGSI_OPCODE_SAD:
1744 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1745 src0 = fetchSrc(0, c);
1746 src1 = fetchSrc(1, c);
1747 src2 = fetchSrc(2, c);
1748 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1749 }
1750 break;
1751 case TGSI_OPCODE_MOV:
1752 case TGSI_OPCODE_ABS:
1753 case TGSI_OPCODE_CEIL:
1754 case TGSI_OPCODE_FLR:
1755 case TGSI_OPCODE_TRUNC:
1756 case TGSI_OPCODE_RCP:
1757 case TGSI_OPCODE_IABS:
1758 case TGSI_OPCODE_INEG:
1759 case TGSI_OPCODE_NOT:
1760 case TGSI_OPCODE_DDX:
1761 case TGSI_OPCODE_DDY:
1762 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1763 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1764 break;
1765 case TGSI_OPCODE_RSQ:
1766 src0 = fetchSrc(0, 0);
1767 val0 = getScratch();
1768 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1769 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1770 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1771 mkMov(dst0[c], val0);
1772 break;
1773 case TGSI_OPCODE_ARL:
1774 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1775 src0 = fetchSrc(0, c);
1776 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1777 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1778 }
1779 break;
1780 case TGSI_OPCODE_UARL:
1781 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1782 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1783 break;
1784 case TGSI_OPCODE_EX2:
1785 case TGSI_OPCODE_LG2:
1786 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1787 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1788 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1789 break;
1790 case TGSI_OPCODE_COS:
1791 case TGSI_OPCODE_SIN:
1792 val0 = getScratch();
1793 if (mask & 7) {
1794 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1795 mkOp1(op, TYPE_F32, val0, val0);
1796 for (c = 0; c < 3; ++c)
1797 if (dst0[c])
1798 mkMov(dst0[c], val0);
1799 }
1800 if (dst0[3]) {
1801 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1802 mkOp1(op, TYPE_F32, dst0[3], val0);
1803 }
1804 break;
1805 case TGSI_OPCODE_SCS:
1806 if (mask & 3) {
1807 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1808 if (dst0[0])
1809 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1810 if (dst0[1])
1811 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1812 }
1813 if (dst0[2])
1814 loadImm(dst0[2], 0.0f);
1815 if (dst0[3])
1816 loadImm(dst0[3], 1.0f);
1817 break;
1818 case TGSI_OPCODE_EXP:
1819 src0 = fetchSrc(0, 0);
1820 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1821 if (dst0[1])
1822 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1823 if (dst0[0])
1824 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1825 if (dst0[2])
1826 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1827 if (dst0[3])
1828 loadImm(dst0[3], 1.0f);
1829 break;
1830 case TGSI_OPCODE_LOG:
1831 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1832 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1833 if (dst0[0] || dst0[1])
1834 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1835 if (dst0[1]) {
1836 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1837 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1838 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1839 }
1840 if (dst0[3])
1841 loadImm(dst0[3], 1.0f);
1842 break;
1843 case TGSI_OPCODE_DP2:
1844 val0 = buildDot(2);
1845 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1846 mkMov(dst0[c], val0);
1847 break;
1848 case TGSI_OPCODE_DP3:
1849 val0 = buildDot(3);
1850 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1851 mkMov(dst0[c], val0);
1852 break;
1853 case TGSI_OPCODE_DP4:
1854 val0 = buildDot(4);
1855 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1856 mkMov(dst0[c], val0);
1857 break;
1858 case TGSI_OPCODE_DPH:
1859 val0 = buildDot(3);
1860 src1 = fetchSrc(1, 3);
1861 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1862 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1863 mkMov(dst0[c], val0);
1864 break;
1865 case TGSI_OPCODE_DST:
1866 if (dst0[0])
1867 loadImm(dst0[0], 1.0f);
1868 if (dst0[1]) {
1869 src0 = fetchSrc(0, 1);
1870 src1 = fetchSrc(1, 1);
1871 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1872 }
1873 if (dst0[2])
1874 mkMov(dst0[2], fetchSrc(0, 2));
1875 if (dst0[3])
1876 mkMov(dst0[3], fetchSrc(1, 3));
1877 break;
1878 case TGSI_OPCODE_LRP:
1879 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1880 src0 = fetchSrc(0, c);
1881 src1 = fetchSrc(1, c);
1882 src2 = fetchSrc(2, c);
1883 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1884 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1885 }
1886 break;
1887 case TGSI_OPCODE_LIT:
1888 handleLIT(dst0);
1889 break;
1890 case TGSI_OPCODE_XPD:
1891 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1892 if (c < 3) {
1893 val0 = getSSA();
1894 src0 = fetchSrc(1, (c + 1) % 3);
1895 src1 = fetchSrc(0, (c + 2) % 3);
1896 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1897 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1898
1899 src0 = fetchSrc(0, (c + 1) % 3);
1900 src1 = fetchSrc(1, (c + 2) % 3);
1901 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1902 } else {
1903 loadImm(dst0[c], 1.0f);
1904 }
1905 }
1906 break;
1907 case TGSI_OPCODE_ISSG:
1908 case TGSI_OPCODE_SSG:
1909 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1910 src0 = fetchSrc(0, c);
1911 val0 = getScratch();
1912 val1 = getScratch();
1913 mkCmp(OP_SET, CC_GT, srcTy, val0, src0, zero);
1914 mkCmp(OP_SET, CC_LT, srcTy, val1, src0, zero);
1915 if (srcTy == TYPE_F32)
1916 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1917 else
1918 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
1919 }
1920 break;
1921 case TGSI_OPCODE_UCMP:
1922 case TGSI_OPCODE_CMP:
1923 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1924 src0 = fetchSrc(0, c);
1925 src1 = fetchSrc(1, c);
1926 src2 = fetchSrc(2, c);
1927 if (src1 == src2)
1928 mkMov(dst0[c], src1);
1929 else
1930 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1931 srcTy, dst0[c], src1, src2, src0);
1932 }
1933 break;
1934 case TGSI_OPCODE_FRC:
1935 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1936 src0 = fetchSrc(0, c);
1937 val0 = getScratch();
1938 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1939 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1940 }
1941 break;
1942 case TGSI_OPCODE_ROUND:
1943 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1944 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1945 ->rnd = ROUND_NI;
1946 break;
1947 case TGSI_OPCODE_CLAMP:
1948 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1949 src0 = fetchSrc(0, c);
1950 src1 = fetchSrc(1, c);
1951 src2 = fetchSrc(2, c);
1952 val0 = getScratch();
1953 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1954 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1955 }
1956 break;
1957 case TGSI_OPCODE_SLT:
1958 case TGSI_OPCODE_SGE:
1959 case TGSI_OPCODE_SEQ:
1960 case TGSI_OPCODE_SFL:
1961 case TGSI_OPCODE_SGT:
1962 case TGSI_OPCODE_SLE:
1963 case TGSI_OPCODE_SNE:
1964 case TGSI_OPCODE_STR:
1965 case TGSI_OPCODE_ISGE:
1966 case TGSI_OPCODE_ISLT:
1967 case TGSI_OPCODE_USEQ:
1968 case TGSI_OPCODE_USGE:
1969 case TGSI_OPCODE_USLT:
1970 case TGSI_OPCODE_USNE:
1971 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1972 src0 = fetchSrc(0, c);
1973 src1 = fetchSrc(1, c);
1974 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1975 }
1976 break;
1977 case TGSI_OPCODE_KIL:
1978 val0 = new_LValue(func, FILE_PREDICATE);
1979 for (c = 0; c < 4; ++c) {
1980 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1981 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1982 }
1983 break;
1984 case TGSI_OPCODE_KILP:
1985 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1986 break;
1987 case TGSI_OPCODE_TEX:
1988 case TGSI_OPCODE_TXB:
1989 case TGSI_OPCODE_TXL:
1990 case TGSI_OPCODE_TXP:
1991 // R S L C Dx Dy
1992 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1993 break;
1994 case TGSI_OPCODE_TXD:
1995 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1996 break;
1997 case TGSI_OPCODE_SAMPLE:
1998 case TGSI_OPCODE_SAMPLE_B:
1999 case TGSI_OPCODE_SAMPLE_D:
2000 case TGSI_OPCODE_SAMPLE_L:
2001 case TGSI_OPCODE_SAMPLE_C:
2002 case TGSI_OPCODE_SAMPLE_C_LZ:
2003 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
2004 break;
2005 case TGSI_OPCODE_TXF:
2006 case TGSI_OPCODE_LOAD:
2007 handleTXF(dst0, 1);
2008 break;
2009 case TGSI_OPCODE_TXQ:
2010 case TGSI_OPCODE_RESINFO:
2011 handleTXQ(dst0, TXQ_DIMS);
2012 break;
2013 case TGSI_OPCODE_F2I:
2014 case TGSI_OPCODE_F2U:
2015 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2016 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2017 break;
2018 case TGSI_OPCODE_I2F:
2019 case TGSI_OPCODE_U2F:
2020 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2021 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2022 break;
2023 case TGSI_OPCODE_EMIT:
2024 case TGSI_OPCODE_ENDPRIM:
2025 // get vertex stream if specified (must be immediate)
2026 src0 = tgsi.srcCount() ?
2027 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2028 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2029 break;
2030 case TGSI_OPCODE_IF:
2031 {
2032 BasicBlock *ifBB = new BasicBlock(func);
2033
2034 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2035 condBBs.push(bb);
2036 joinBBs.push(bb);
2037
2038 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2039
2040 setPosition(ifBB, true);
2041 }
2042 break;
2043 case TGSI_OPCODE_ELSE:
2044 {
2045 BasicBlock *elseBB = new BasicBlock(func);
2046 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2047
2048 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2049 condBBs.push(bb);
2050
2051 forkBB->getExit()->asFlow()->target.bb = elseBB;
2052 if (!bb->isTerminated())
2053 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2054
2055 setPosition(elseBB, true);
2056 }
2057 break;
2058 case TGSI_OPCODE_ENDIF:
2059 {
2060 BasicBlock *convBB = new BasicBlock(func);
2061 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2062 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2063
2064 if (!bb->isTerminated()) {
2065 // we only want join if none of the clauses ended with CONT/BREAK/RET
2066 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2067 insertConvergenceOps(convBB, forkBB);
2068 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2069 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2070 }
2071
2072 if (prevBB->getExit()->op == OP_BRA) {
2073 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2074 prevBB->getExit()->asFlow()->target.bb = convBB;
2075 }
2076 setPosition(convBB, true);
2077 }
2078 break;
2079 case TGSI_OPCODE_BGNLOOP:
2080 {
2081 BasicBlock *lbgnBB = new BasicBlock(func);
2082 BasicBlock *lbrkBB = new BasicBlock(func);
2083
2084 loopBBs.push(lbgnBB);
2085 breakBBs.push(lbrkBB);
2086 if (loopBBs.getSize() > func->loopNestingBound)
2087 func->loopNestingBound++;
2088
2089 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2090
2091 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2092 setPosition(lbgnBB, true);
2093 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2094 }
2095 break;
2096 case TGSI_OPCODE_ENDLOOP:
2097 {
2098 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2099
2100 if (!bb->isTerminated()) {
2101 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2102 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2103 }
2104 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2105 }
2106 break;
2107 case TGSI_OPCODE_BRK:
2108 {
2109 if (bb->isTerminated())
2110 break;
2111 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2112 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2113 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2114 }
2115 break;
2116 case TGSI_OPCODE_CONT:
2117 {
2118 if (bb->isTerminated())
2119 break;
2120 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2121 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2122 contBB->explicitCont = true;
2123 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2124 }
2125 break;
2126 case TGSI_OPCODE_BGNSUB:
2127 {
2128 if (!retIPs.getSize()) {
2129 // end of main function
2130 ip = code->scan.num_instructions - 2; // goto END
2131 return true;
2132 }
2133 BasicBlock *entry = new BasicBlock(func);
2134 BasicBlock *leave = new BasicBlock(func);
2135 entryBBs.push(entry);
2136 leaveBBs.push(leave);
2137 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2138 setPosition(entry, true);
2139 }
2140 return true;
2141 case TGSI_OPCODE_ENDSUB:
2142 {
2143 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2144 entryBBs.pop();
2145 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2146 setPosition(leave, true);
2147 ip = retIPs.pop().u.u;
2148 }
2149 return true;
2150 case TGSI_OPCODE_CAL:
2151 // we don't have function declarations, so inline everything
2152 retIPs.push(ip);
2153 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2154 return true;
2155 case TGSI_OPCODE_RET:
2156 {
2157 if (bb->isTerminated())
2158 return true;
2159 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2160 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2161 if (!isEndOfSubroutine(ip + 1)) {
2162 // insert a PRERET at the entry if this is an early return
2163 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2164 preRet->fixed = 1;
2165 entry->insertHead(preRet);
2166 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2167 }
2168 // everything inlined so RET serves only to wrap up the stack
2169 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2170 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2171 }
2172 break;
2173 case TGSI_OPCODE_END:
2174 {
2175 // attach and generate epilogue code
2176 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2177 entryBBs.pop();
2178 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2179 setPosition(epilogue, true);
2180 if (prog->getType() == Program::TYPE_FRAGMENT)
2181 exportOutputs();
2182 if (info->io.genUserClip > 0)
2183 handleUserClipPlanes();
2184 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2185 }
2186 break;
2187 case TGSI_OPCODE_SWITCH:
2188 case TGSI_OPCODE_CASE:
2189 ERROR("switch/case opcode encountered, should have been lowered\n");
2190 abort();
2191 break;
2192 default:
2193 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2194 assert(0);
2195 break;
2196 }
2197
2198 if (tgsi.dstCount()) {
2199 for (c = 0; c < 4; ++c) {
2200 if (!dst0[c])
2201 continue;
2202 if (dst0[c] != rDst0[c])
2203 mkMov(rDst0[c], dst0[c]);
2204 storeDst(0, c, rDst0[c]);
2205 }
2206 }
2207 vtxBaseValid = 0;
2208
2209 return true;
2210 }
2211
2212 void
2213 Converter::handleUserClipPlanes()
2214 {
2215 Value *res[8];
2216 int i, c;
2217
2218 for (c = 0; c < 4; ++c) {
2219 for (i = 0; i < info->io.genUserClip; ++i) {
2220 Value *ucp;
2221 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2222 i * 16 + c * 4), NULL);
2223 if (c == 0)
2224 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2225 else
2226 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2227 }
2228 }
2229
2230 for (i = 0; i < info->io.genUserClip; ++i)
2231 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2232 }
2233
2234 void
2235 Converter::exportOutputs()
2236 {
2237 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2238 for (unsigned int c = 0; c < 4; ++c) {
2239 if (!oData.exists(i, c))
2240 continue;
2241 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2242 info->out[i].slot[c] * 4);
2243 Value *val = oData.load(i, c, NULL);
2244 if (val)
2245 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2246 }
2247 }
2248 }
2249
2250 Converter::Converter(Program *ir, const tgsi::Source *src)
2251 : code(src),
2252 tgsi(NULL),
2253 tData(this), aData(this), pData(this), oData(this)
2254 {
2255 prog = ir;
2256 info = code->info;
2257
2258 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2259
2260 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2261 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2262 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2263 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2264
2265 lData = NULL;
2266 iData = NULL;
2267
2268 zero = mkImm((uint32_t)0);
2269
2270 vtxBaseValid = 0;
2271 }
2272
2273 Converter::~Converter()
2274 {
2275 if (lData)
2276 delete[] lData;
2277 if (iData)
2278 delete[] iData;
2279 }
2280
2281 bool
2282 Converter::run()
2283 {
2284 BasicBlock *entry = new BasicBlock(prog->main);
2285 BasicBlock *leave = new BasicBlock(prog->main);
2286
2287 if (code->tempArrayCount && !lData) {
2288 uint32_t volume = 0;
2289 lData = new DataArray[code->tempArrayCount];
2290 if (!lData)
2291 return false;
2292 for (int i = 0; i < code->tempArrayCount; ++i) {
2293 int len = code->tempArrays[i].u32 >> 2;
2294 int dim = code->tempArrays[i].u32 & 3;
2295 lData[i].setParent(this);
2296 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2297 volume += (len * dim * 4 + 0xf) & ~0xf;
2298 }
2299 }
2300 if (code->immdArrayCount && !iData) {
2301 uint32_t volume = 0;
2302 iData = new DataArray[code->immdArrayCount];
2303 if (!iData)
2304 return false;
2305 for (int i = 0; i < code->immdArrayCount; ++i) {
2306 int len = code->immdArrays[i].u32 >> 2;
2307 int dim = code->immdArrays[i].u32 & 3;
2308 iData[i].setParent(this);
2309 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2310 volume += (len * dim * 4 + 0xf) & ~0xf;
2311 }
2312 }
2313
2314 prog->main->setEntry(entry);
2315 prog->main->setExit(leave);
2316
2317 setPosition(entry, true);
2318 entryBBs.push(entry);
2319 leaveBBs.push(leave);
2320
2321 if (info->io.genUserClip > 0) {
2322 for (int c = 0; c < 4; ++c)
2323 clipVtx[c] = getScratch();
2324 }
2325
2326 if (prog->getType() == Program::TYPE_FRAGMENT) {
2327 Symbol *sv = mkSysVal(SV_POSITION, 3);
2328 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2329 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2330 }
2331
2332 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2333 if (!handleInstruction(&code->insns[ip]))
2334 return false;
2335 }
2336 return true;
2337 }
2338
2339 } // unnamed namespace
2340
2341 namespace nv50_ir {
2342
2343 bool
2344 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2345 {
2346 tgsi::Source src(info);
2347 if (!src.scanSource())
2348 return false;
2349
2350 Converter builder(this, &src);
2351 return builder.run();
2352 }
2353
2354 } // namespace nv50_ir