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nv50/ir/ra: don't coalesce contraint-moves
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 default:
325 assert(0);
326 return nv50_ir::SV_CLOCK;
327 }
328 }
329
330 #define NV50_IR_TEX_TARG_CASE(a, b) \
331 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
332
333 static nv50_ir::TexTarget translateTexture(uint tex)
334 {
335 switch (tex) {
336 NV50_IR_TEX_TARG_CASE(1D, 1D);
337 NV50_IR_TEX_TARG_CASE(2D, 2D);
338 NV50_IR_TEX_TARG_CASE(3D, 3D);
339 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
340 NV50_IR_TEX_TARG_CASE(RECT, RECT);
341 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
342 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
344 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
348
349 case TGSI_TEXTURE_UNKNOWN:
350 default:
351 assert(!"invalid texture target");
352 return nv50_ir::TEX_TARGET_2D;
353 }
354 }
355
356 nv50_ir::DataType Instruction::inferSrcType() const
357 {
358 switch (getOpcode()) {
359 case TGSI_OPCODE_AND:
360 case TGSI_OPCODE_OR:
361 case TGSI_OPCODE_XOR:
362 case TGSI_OPCODE_U2F:
363 case TGSI_OPCODE_UADD:
364 case TGSI_OPCODE_UDIV:
365 case TGSI_OPCODE_UMOD:
366 case TGSI_OPCODE_UMAD:
367 case TGSI_OPCODE_UMUL:
368 case TGSI_OPCODE_UMAX:
369 case TGSI_OPCODE_UMIN:
370 case TGSI_OPCODE_USEQ:
371 case TGSI_OPCODE_USGE:
372 case TGSI_OPCODE_USLT:
373 case TGSI_OPCODE_USNE:
374 case TGSI_OPCODE_USHR:
375 case TGSI_OPCODE_UCMP:
376 return nv50_ir::TYPE_U32;
377 case TGSI_OPCODE_I2F:
378 case TGSI_OPCODE_IDIV:
379 case TGSI_OPCODE_IMAX:
380 case TGSI_OPCODE_IMIN:
381 case TGSI_OPCODE_IABS:
382 case TGSI_OPCODE_INEG:
383 case TGSI_OPCODE_ISGE:
384 case TGSI_OPCODE_ISHR:
385 case TGSI_OPCODE_ISLT:
386 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
387 case TGSI_OPCODE_MOD:
388 case TGSI_OPCODE_UARL:
389 return nv50_ir::TYPE_S32;
390 default:
391 return nv50_ir::TYPE_F32;
392 }
393 }
394
395 nv50_ir::DataType Instruction::inferDstType() const
396 {
397 switch (getOpcode()) {
398 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
399 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
400 case TGSI_OPCODE_I2F:
401 case TGSI_OPCODE_U2F:
402 return nv50_ir::TYPE_F32;
403 default:
404 return inferSrcType();
405 }
406 }
407
408 nv50_ir::CondCode Instruction::getSetCond() const
409 {
410 using namespace nv50_ir;
411
412 switch (getOpcode()) {
413 case TGSI_OPCODE_SLT:
414 case TGSI_OPCODE_ISLT:
415 case TGSI_OPCODE_USLT:
416 return CC_LT;
417 case TGSI_OPCODE_SLE:
418 return CC_LE;
419 case TGSI_OPCODE_SGE:
420 case TGSI_OPCODE_ISGE:
421 case TGSI_OPCODE_USGE:
422 return CC_GE;
423 case TGSI_OPCODE_SGT:
424 return CC_GT;
425 case TGSI_OPCODE_SEQ:
426 case TGSI_OPCODE_USEQ:
427 return CC_EQ;
428 case TGSI_OPCODE_SNE:
429 case TGSI_OPCODE_USNE:
430 return CC_NE;
431 case TGSI_OPCODE_SFL:
432 return CC_NEVER;
433 case TGSI_OPCODE_STR:
434 default:
435 return CC_ALWAYS;
436 }
437 }
438
439 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
440
441 static nv50_ir::operation translateOpcode(uint opcode)
442 {
443 switch (opcode) {
444 NV50_IR_OPCODE_CASE(ARL, SHL);
445 NV50_IR_OPCODE_CASE(MOV, MOV);
446
447 NV50_IR_OPCODE_CASE(RCP, RCP);
448 NV50_IR_OPCODE_CASE(RSQ, RSQ);
449
450 NV50_IR_OPCODE_CASE(MUL, MUL);
451 NV50_IR_OPCODE_CASE(ADD, ADD);
452
453 NV50_IR_OPCODE_CASE(MIN, MIN);
454 NV50_IR_OPCODE_CASE(MAX, MAX);
455 NV50_IR_OPCODE_CASE(SLT, SET);
456 NV50_IR_OPCODE_CASE(SGE, SET);
457 NV50_IR_OPCODE_CASE(MAD, MAD);
458 NV50_IR_OPCODE_CASE(SUB, SUB);
459
460 NV50_IR_OPCODE_CASE(FLR, FLOOR);
461 NV50_IR_OPCODE_CASE(ROUND, CVT);
462 NV50_IR_OPCODE_CASE(EX2, EX2);
463 NV50_IR_OPCODE_CASE(LG2, LG2);
464 NV50_IR_OPCODE_CASE(POW, POW);
465
466 NV50_IR_OPCODE_CASE(ABS, ABS);
467
468 NV50_IR_OPCODE_CASE(COS, COS);
469 NV50_IR_OPCODE_CASE(DDX, DFDX);
470 NV50_IR_OPCODE_CASE(DDY, DFDY);
471 NV50_IR_OPCODE_CASE(KILP, DISCARD);
472
473 NV50_IR_OPCODE_CASE(SEQ, SET);
474 NV50_IR_OPCODE_CASE(SFL, SET);
475 NV50_IR_OPCODE_CASE(SGT, SET);
476 NV50_IR_OPCODE_CASE(SIN, SIN);
477 NV50_IR_OPCODE_CASE(SLE, SET);
478 NV50_IR_OPCODE_CASE(SNE, SET);
479 NV50_IR_OPCODE_CASE(STR, SET);
480 NV50_IR_OPCODE_CASE(TEX, TEX);
481 NV50_IR_OPCODE_CASE(TXD, TXD);
482 NV50_IR_OPCODE_CASE(TXP, TEX);
483
484 NV50_IR_OPCODE_CASE(BRA, BRA);
485 NV50_IR_OPCODE_CASE(CAL, CALL);
486 NV50_IR_OPCODE_CASE(RET, RET);
487 NV50_IR_OPCODE_CASE(CMP, SLCT);
488
489 NV50_IR_OPCODE_CASE(TXB, TXB);
490
491 NV50_IR_OPCODE_CASE(DIV, DIV);
492
493 NV50_IR_OPCODE_CASE(TXL, TXL);
494
495 NV50_IR_OPCODE_CASE(CEIL, CEIL);
496 NV50_IR_OPCODE_CASE(I2F, CVT);
497 NV50_IR_OPCODE_CASE(NOT, NOT);
498 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
499 NV50_IR_OPCODE_CASE(SHL, SHL);
500
501 NV50_IR_OPCODE_CASE(AND, AND);
502 NV50_IR_OPCODE_CASE(OR, OR);
503 NV50_IR_OPCODE_CASE(MOD, MOD);
504 NV50_IR_OPCODE_CASE(XOR, XOR);
505 NV50_IR_OPCODE_CASE(SAD, SAD);
506 NV50_IR_OPCODE_CASE(TXF, TXF);
507 NV50_IR_OPCODE_CASE(TXQ, TXQ);
508
509 NV50_IR_OPCODE_CASE(EMIT, EMIT);
510 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
511
512 NV50_IR_OPCODE_CASE(KIL, DISCARD);
513
514 NV50_IR_OPCODE_CASE(F2I, CVT);
515 NV50_IR_OPCODE_CASE(IDIV, DIV);
516 NV50_IR_OPCODE_CASE(IMAX, MAX);
517 NV50_IR_OPCODE_CASE(IMIN, MIN);
518 NV50_IR_OPCODE_CASE(IABS, ABS);
519 NV50_IR_OPCODE_CASE(INEG, NEG);
520 NV50_IR_OPCODE_CASE(ISGE, SET);
521 NV50_IR_OPCODE_CASE(ISHR, SHR);
522 NV50_IR_OPCODE_CASE(ISLT, SET);
523 NV50_IR_OPCODE_CASE(F2U, CVT);
524 NV50_IR_OPCODE_CASE(U2F, CVT);
525 NV50_IR_OPCODE_CASE(UADD, ADD);
526 NV50_IR_OPCODE_CASE(UDIV, DIV);
527 NV50_IR_OPCODE_CASE(UMAD, MAD);
528 NV50_IR_OPCODE_CASE(UMAX, MAX);
529 NV50_IR_OPCODE_CASE(UMIN, MIN);
530 NV50_IR_OPCODE_CASE(UMOD, MOD);
531 NV50_IR_OPCODE_CASE(UMUL, MUL);
532 NV50_IR_OPCODE_CASE(USEQ, SET);
533 NV50_IR_OPCODE_CASE(USGE, SET);
534 NV50_IR_OPCODE_CASE(USHR, SHR);
535 NV50_IR_OPCODE_CASE(USLT, SET);
536 NV50_IR_OPCODE_CASE(USNE, SET);
537
538 NV50_IR_OPCODE_CASE(LOAD, TXF);
539 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
540 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
541 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
542 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
543 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
544 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
545 NV50_IR_OPCODE_CASE(GATHER4, TXG);
546 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
547
548 NV50_IR_OPCODE_CASE(END, EXIT);
549
550 default:
551 return nv50_ir::OP_NOP;
552 }
553 }
554
555 bool Instruction::checkDstSrcAliasing() const
556 {
557 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
558 return false;
559
560 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
561 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
562 break;
563 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
564 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
565 return true;
566 }
567 return false;
568 }
569
570 class Source
571 {
572 public:
573 Source(struct nv50_ir_prog_info *);
574 ~Source();
575
576 struct Subroutine
577 {
578 unsigned pc;
579 };
580
581 public:
582 bool scanSource();
583 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
584
585 public:
586 struct tgsi_shader_info scan;
587 struct tgsi_full_instruction *insns;
588 const struct tgsi_token *tokens;
589 struct nv50_ir_prog_info *info;
590
591 nv50_ir::DynArray tempArrays;
592 nv50_ir::DynArray immdArrays;
593 int tempArrayCount;
594 int immdArrayCount;
595
596 bool mainTempsInLMem;
597
598 int clipVertexOutput;
599
600 uint8_t *resourceTargets; // TGSI_TEXTURE_*
601 unsigned resourceCount;
602
603 Subroutine *subroutines;
604 unsigned subroutineCount;
605
606 private:
607 int inferSysValDirection(unsigned sn) const;
608 bool scanDeclaration(const struct tgsi_full_declaration *);
609 bool scanInstruction(const struct tgsi_full_instruction *);
610 void scanProperty(const struct tgsi_full_property *);
611 void scanImmediate(const struct tgsi_full_immediate *);
612
613 inline bool isEdgeFlagPassthrough(const Instruction&) const;
614 };
615
616 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
617 {
618 tokens = (const struct tgsi_token *)info->bin.source;
619
620 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
621 tgsi_dump(tokens, 0);
622
623 resourceTargets = NULL;
624 subroutines = NULL;
625
626 mainTempsInLMem = FALSE;
627 }
628
629 Source::~Source()
630 {
631 if (insns)
632 FREE(insns);
633
634 if (info->immd.data)
635 FREE(info->immd.data);
636 if (info->immd.type)
637 FREE(info->immd.type);
638
639 if (resourceTargets)
640 delete[] resourceTargets;
641 if (subroutines)
642 delete[] subroutines;
643 }
644
645 bool Source::scanSource()
646 {
647 unsigned insnCount = 0;
648 unsigned subrCount = 0;
649 struct tgsi_parse_context parse;
650
651 tgsi_scan_shader(tokens, &scan);
652
653 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
654 sizeof(insns[0]));
655 if (!insns)
656 return false;
657
658 clipVertexOutput = -1;
659
660 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
661 resourceTargets = new uint8_t[resourceCount];
662
663 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
664 subroutines = new Subroutine[subroutineCount];
665
666 info->immd.bufSize = 0;
667 tempArrayCount = 0;
668 immdArrayCount = 0;
669
670 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
671 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
672 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
673
674 if (info->type == PIPE_SHADER_FRAGMENT) {
675 info->prop.fp.writesDepth = scan.writes_z;
676 info->prop.fp.usesDiscard = scan.uses_kill;
677 } else
678 if (info->type == PIPE_SHADER_GEOMETRY) {
679 info->prop.gp.instanceCount = 1; // default value
680 }
681
682 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
683 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
684
685 tgsi_parse_init(&parse, tokens);
686 while (!tgsi_parse_end_of_tokens(&parse)) {
687 tgsi_parse_token(&parse);
688
689 switch (parse.FullToken.Token.Type) {
690 case TGSI_TOKEN_TYPE_IMMEDIATE:
691 scanImmediate(&parse.FullToken.FullImmediate);
692 break;
693 case TGSI_TOKEN_TYPE_DECLARATION:
694 scanDeclaration(&parse.FullToken.FullDeclaration);
695 break;
696 case TGSI_TOKEN_TYPE_INSTRUCTION:
697 insns[insnCount++] = parse.FullToken.FullInstruction;
698 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
699 subroutines[++subrCount].pc = insnCount - 1;
700 else
701 scanInstruction(&parse.FullToken.FullInstruction);
702 break;
703 case TGSI_TOKEN_TYPE_PROPERTY:
704 scanProperty(&parse.FullToken.FullProperty);
705 break;
706 default:
707 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
708 break;
709 }
710 }
711 tgsi_parse_free(&parse);
712
713 if (mainTempsInLMem)
714 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
715
716 if (info->io.genUserClip > 0)
717 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
718
719 return info->assignSlots(info) == 0;
720 }
721
722 void Source::scanProperty(const struct tgsi_full_property *prop)
723 {
724 switch (prop->Property.PropertyName) {
725 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
726 info->prop.gp.outputPrim = prop->u[0].Data;
727 break;
728 case TGSI_PROPERTY_GS_INPUT_PRIM:
729 info->prop.gp.inputPrim = prop->u[0].Data;
730 break;
731 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
732 info->prop.gp.maxVertices = prop->u[0].Data;
733 break;
734 #if 0
735 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
736 info->prop.gp.instanceCount = prop->u[0].Data;
737 break;
738 #endif
739 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
740 info->prop.fp.separateFragData = TRUE;
741 break;
742 case TGSI_PROPERTY_FS_COORD_ORIGIN:
743 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
744 // we don't care
745 break;
746 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
747 info->io.genUserClip = -1;
748 break;
749 default:
750 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
751 break;
752 }
753 }
754
755 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
756 {
757 const unsigned n = info->immd.count++;
758
759 assert(n < scan.immediate_count);
760
761 for (int c = 0; c < 4; ++c)
762 info->immd.data[n * 4 + c] = imm->u[c].Uint;
763
764 info->immd.type[n] = imm->Immediate.DataType;
765 }
766
767 int Source::inferSysValDirection(unsigned sn) const
768 {
769 switch (sn) {
770 case TGSI_SEMANTIC_INSTANCEID:
771 // case TGSI_SEMANTIC_VERTEXID:
772 return 1;
773 #if 0
774 case TGSI_SEMANTIC_LAYER:
775 case TGSI_SEMANTIC_VIEWPORTINDEX:
776 return 0;
777 #endif
778 case TGSI_SEMANTIC_PRIMID:
779 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
780 default:
781 return 0;
782 }
783 }
784
785 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
786 {
787 unsigned i;
788 unsigned sn = TGSI_SEMANTIC_GENERIC;
789 unsigned si = 0;
790 const unsigned first = decl->Range.First, last = decl->Range.Last;
791
792 if (decl->Declaration.Semantic) {
793 sn = decl->Semantic.Name;
794 si = decl->Semantic.Index;
795 }
796
797 switch (decl->Declaration.File) {
798 case TGSI_FILE_INPUT:
799 if (info->type == PIPE_SHADER_VERTEX) {
800 // all vertex attributes are equal
801 for (i = first; i <= last; ++i) {
802 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
803 info->in[i].si = i;
804 }
805 } else {
806 for (i = first; i <= last; ++i, ++si) {
807 info->in[i].id = i;
808 info->in[i].sn = sn;
809 info->in[i].si = si;
810 if (info->type == PIPE_SHADER_FRAGMENT) {
811 // translate interpolation mode
812 switch (decl->Declaration.Interpolate) {
813 case TGSI_INTERPOLATE_CONSTANT:
814 info->in[i].flat = 1;
815 break;
816 case TGSI_INTERPOLATE_LINEAR:
817 if (sn != TGSI_SEMANTIC_COLOR) // GL_NICEST
818 info->in[i].linear = 1;
819 break;
820 default:
821 break;
822 }
823 if (decl->Declaration.Centroid)
824 info->in[i].centroid = 1;
825 }
826 }
827 }
828 break;
829 case TGSI_FILE_OUTPUT:
830 for (i = first; i <= last; ++i, ++si) {
831 switch (sn) {
832 case TGSI_SEMANTIC_POSITION:
833 if (info->type == PIPE_SHADER_FRAGMENT)
834 info->io.fragDepth = i;
835 else
836 if (clipVertexOutput < 0)
837 clipVertexOutput = i;
838 break;
839 case TGSI_SEMANTIC_COLOR:
840 if (info->type == PIPE_SHADER_FRAGMENT)
841 info->prop.fp.numColourResults++;
842 break;
843 case TGSI_SEMANTIC_EDGEFLAG:
844 info->io.edgeFlagOut = i;
845 break;
846 case TGSI_SEMANTIC_CLIPVERTEX:
847 clipVertexOutput = i;
848 break;
849 case TGSI_SEMANTIC_CLIPDIST:
850 info->io.clipDistanceMask |=
851 decl->Declaration.UsageMask << (si * 4);
852 info->io.genUserClip = -1;
853 break;
854 default:
855 break;
856 }
857 info->out[i].id = i;
858 info->out[i].sn = sn;
859 info->out[i].si = si;
860 }
861 break;
862 case TGSI_FILE_SYSTEM_VALUE:
863 for (i = first; i <= last; ++i, ++si) {
864 info->sv[i].sn = sn;
865 info->sv[i].si = si;
866 info->sv[i].input = inferSysValDirection(sn);
867 }
868 break;
869 case TGSI_FILE_RESOURCE:
870 for (i = first; i <= last; ++i)
871 resourceTargets[i] = decl->Resource.Resource;
872 break;
873 case TGSI_FILE_IMMEDIATE_ARRAY:
874 {
875 if (decl->Dim.Index2D >= immdArrayCount)
876 immdArrayCount = decl->Dim.Index2D + 1;
877 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
878 int c;
879 uint32_t base, count;
880 switch (decl->Declaration.UsageMask) {
881 case 0x1: c = 1; break;
882 case 0x3: c = 2; break;
883 default:
884 c = 4;
885 break;
886 }
887 immdArrays[decl->Dim.Index2D].u32 |= c;
888 count = (last + 1) * c;
889 base = info->immd.bufSize / 4;
890 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
891 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
892 info->immd.bufSize);
893 // NOTE: this assumes array declarations are ordered by Dim.Index2D
894 for (i = 0; i < count; ++i)
895 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
896 }
897 break;
898 case TGSI_FILE_TEMPORARY_ARRAY:
899 {
900 if (decl->Dim.Index2D >= tempArrayCount)
901 tempArrayCount = decl->Dim.Index2D + 1;
902 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
903 int c;
904 uint32_t count;
905 switch (decl->Declaration.UsageMask) {
906 case 0x1: c = 1; break;
907 case 0x3: c = 2; break;
908 default:
909 c = 4;
910 break;
911 }
912 tempArrays[decl->Dim.Index2D].u32 |= c;
913 count = (last + 1) * c;
914 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
915 }
916 break;
917 case TGSI_FILE_NULL:
918 case TGSI_FILE_TEMPORARY:
919 case TGSI_FILE_ADDRESS:
920 case TGSI_FILE_CONSTANT:
921 case TGSI_FILE_IMMEDIATE:
922 case TGSI_FILE_PREDICATE:
923 case TGSI_FILE_SAMPLER:
924 break;
925 default:
926 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
927 return false;
928 }
929 return true;
930 }
931
932 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
933 {
934 return insn.getOpcode() == TGSI_OPCODE_MOV &&
935 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
936 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
937 }
938
939 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
940 {
941 Instruction insn(inst);
942
943 if (insn.dstCount()) {
944 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
945 Instruction::DstRegister dst = insn.getDst(0);
946
947 if (dst.isIndirect(0))
948 for (unsigned i = 0; i < info->numOutputs; ++i)
949 info->out[i].mask = 0xf;
950 else
951 info->out[dst.getIndex(0)].mask |= dst.getMask();
952
953 if (isEdgeFlagPassthrough(insn))
954 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
955 } else
956 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
957 if (insn.getDst(0).isIndirect(0))
958 mainTempsInLMem = TRUE;
959 }
960 }
961
962 for (unsigned s = 0; s < insn.srcCount(); ++s) {
963 Instruction::SrcRegister src = insn.getSrc(s);
964 if (src.getFile() == TGSI_FILE_TEMPORARY)
965 if (src.isIndirect(0))
966 mainTempsInLMem = TRUE;
967 if (src.getFile() != TGSI_FILE_INPUT)
968 continue;
969 unsigned mask = insn.srcMask(s);
970
971 if (src.isIndirect(0)) {
972 for (unsigned i = 0; i < info->numInputs; ++i)
973 info->in[i].mask = 0xf;
974 } else {
975 for (unsigned c = 0; c < 4; ++c) {
976 if (!(mask & (1 << c)))
977 continue;
978 int k = src.getSwizzle(c);
979 int i = src.getIndex(0);
980 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
981 if (k <= TGSI_SWIZZLE_W)
982 info->in[i].mask |= 1 << k;
983 }
984 }
985 }
986 return true;
987 }
988
989 nv50_ir::TexInstruction::Target
990 Instruction::getTexture(const tgsi::Source *code, int s) const
991 {
992 if (insn->Instruction.Texture) {
993 return translateTexture(insn->Texture.Texture);
994 } else {
995 // XXX: indirect access
996 unsigned int r = getSrc(s).getIndex(0);
997 assert(r < code->resourceCount);
998 return translateTexture(code->resourceTargets[r]);
999 }
1000 }
1001
1002 } // namespace tgsi
1003
1004 namespace {
1005
1006 using namespace nv50_ir;
1007
1008 class Converter : public BuildUtil
1009 {
1010 public:
1011 Converter(Program *, const tgsi::Source *);
1012 ~Converter();
1013
1014 bool run();
1015
1016 private:
1017 Value *getVertexBase(int s);
1018 Value *fetchSrc(int s, int c);
1019 Value *acquireDst(int d, int c);
1020 void storeDst(int d, int c, Value *);
1021
1022 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1023 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1024 Value *val, Value *ptr);
1025
1026 Value *applySrcMod(Value *, int s, int c);
1027
1028 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1029 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1030 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1031
1032 bool handleInstruction(const struct tgsi_full_instruction *);
1033 void exportOutputs();
1034 inline bool isEndOfSubroutine(uint ip);
1035
1036 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1037
1038 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1039 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1040 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1041 void handleTXF(Value *dst0[4], int R);
1042 void handleTXQ(Value *dst0[4], enum TexQuery);
1043 void handleLIT(Value *dst0[4]);
1044 void handleUserClipPlanes();
1045
1046 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1047
1048 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1049
1050 Value *buildDot(int dim);
1051
1052 private:
1053 const struct tgsi::Source *code;
1054 const struct nv50_ir_prog_info *info;
1055
1056 uint ip; // instruction pointer
1057
1058 tgsi::Instruction tgsi;
1059
1060 DataType dstTy;
1061 DataType srcTy;
1062
1063 DataArray tData; // TGSI_FILE_TEMPORARY
1064 DataArray aData; // TGSI_FILE_ADDRESS
1065 DataArray pData; // TGSI_FILE_PREDICATE
1066 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1067 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1068 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1069
1070 Value *zero;
1071 Value *fragCoord[4];
1072 Value *clipVtx[4];
1073
1074 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1075 uint8_t vtxBaseValid;
1076
1077 Stack condBBs; // fork BB, then else clause BB
1078 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1079 Stack loopBBs; // loop headers
1080 Stack breakBBs; // end of / after loop
1081 Stack entryBBs; // start of current (inlined) subroutine
1082 Stack leaveBBs; // end of current (inlined) subroutine
1083 Stack retIPs; // return instruction pointer
1084 };
1085
1086 Symbol *
1087 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1088 {
1089 const int swz = src.getSwizzle(c);
1090
1091 return makeSym(src.getFile(),
1092 src.is2D() ? src.getIndex(1) : 0,
1093 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1094 src.getIndex(0) * 16 + swz * 4);
1095 }
1096
1097 Symbol *
1098 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1099 {
1100 return makeSym(dst.getFile(),
1101 dst.is2D() ? dst.getIndex(1) : 0,
1102 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1103 dst.getIndex(0) * 16 + c * 4);
1104 }
1105
1106 Symbol *
1107 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1108 {
1109 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1110
1111 sym->reg.fileIndex = fileIdx;
1112
1113 if (idx >= 0) {
1114 if (sym->reg.file == FILE_SHADER_INPUT)
1115 sym->setOffset(info->in[idx].slot[c] * 4);
1116 else
1117 if (sym->reg.file == FILE_SHADER_OUTPUT)
1118 sym->setOffset(info->out[idx].slot[c] * 4);
1119 else
1120 if (sym->reg.file == FILE_SYSTEM_VALUE)
1121 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1122 else
1123 sym->setOffset(address);
1124 } else {
1125 sym->setOffset(address);
1126 }
1127 return sym;
1128 }
1129
1130 static inline uint8_t
1131 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1132 {
1133 uint8_t mode;
1134
1135 if (var->flat)
1136 mode = NV50_IR_INTERP_FLAT;
1137 else
1138 if (var->linear)
1139 mode = NV50_IR_INTERP_LINEAR;
1140 else
1141 mode = NV50_IR_INTERP_PERSPECTIVE;
1142
1143 op = (mode == NV50_IR_INTERP_PERSPECTIVE) ? OP_PINTERP : OP_LINTERP;
1144
1145 if (var->centroid)
1146 mode |= NV50_IR_INTERP_CENTROID;
1147
1148 return mode;
1149 }
1150
1151 Value *
1152 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1153 {
1154 operation op;
1155
1156 // XXX: no way to know interpolation mode if we don't know what's accessed
1157 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1158 src.getIndex(0)], op);
1159
1160 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1161
1162 insn->setDef(0, getScratch());
1163 insn->setSrc(0, srcToSym(src, c));
1164 if (op == OP_PINTERP)
1165 insn->setSrc(1, fragCoord[3]);
1166 if (ptr)
1167 insn->setIndirect(0, 0, ptr);
1168
1169 insn->setInterpolate(mode);
1170
1171 bb->insertTail(insn);
1172 return insn->getDef(0);
1173 }
1174
1175 Value *
1176 Converter::applySrcMod(Value *val, int s, int c)
1177 {
1178 Modifier m = tgsi.getSrc(s).getMod(c);
1179 DataType ty = tgsi.inferSrcType();
1180
1181 if (m & Modifier(NV50_IR_MOD_ABS))
1182 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1183
1184 if (m & Modifier(NV50_IR_MOD_NEG))
1185 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1186
1187 return val;
1188 }
1189
1190 Value *
1191 Converter::getVertexBase(int s)
1192 {
1193 assert(s < 5);
1194 if (!(vtxBaseValid & (1 << s))) {
1195 const int index = tgsi.getSrc(s).getIndex(1);
1196 Value *rel = NULL;
1197 if (tgsi.getSrc(s).isIndirect(1))
1198 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1199 vtxBaseValid |= 1 << s;
1200 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1201 }
1202 return vtxBase[s];
1203 }
1204
1205 Value *
1206 Converter::fetchSrc(int s, int c)
1207 {
1208 Value *res;
1209 Value *ptr = NULL, *dimRel = NULL;
1210
1211 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1212
1213 if (src.isIndirect(0))
1214 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1215
1216 if (src.is2D()) {
1217 switch (src.getFile()) {
1218 case TGSI_FILE_INPUT:
1219 dimRel = getVertexBase(s);
1220 break;
1221 case TGSI_FILE_CONSTANT:
1222 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1223 if (src.isIndirect(1))
1224 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1225 break;
1226 default:
1227 break;
1228 }
1229 }
1230
1231 res = fetchSrc(src, c, ptr);
1232
1233 if (dimRel)
1234 res->getInsn()->setIndirect(0, 1, dimRel);
1235
1236 return applySrcMod(res, s, c);
1237 }
1238
1239 Value *
1240 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1241 {
1242 const int idx = src.getIndex(0);
1243 const int swz = src.getSwizzle(c);
1244
1245 switch (src.getFile()) {
1246 case TGSI_FILE_TEMPORARY:
1247 return tData.load(idx, swz, ptr);
1248 case TGSI_FILE_PREDICATE:
1249 return pData.load(idx, swz, ptr);
1250 case TGSI_FILE_ADDRESS:
1251 return aData.load(idx, swz, ptr);
1252
1253 case TGSI_FILE_TEMPORARY_ARRAY:
1254 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1255 return lData[src.getIndex(1)].load(idx, swz, ptr);
1256 case TGSI_FILE_IMMEDIATE_ARRAY:
1257 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1258 return iData[src.getIndex(1)].load(idx, swz, ptr);
1259
1260 case TGSI_FILE_IMMEDIATE:
1261 assert(!ptr);
1262 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1263
1264 case TGSI_FILE_CONSTANT:
1265 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1266
1267 case TGSI_FILE_INPUT:
1268 if (prog->getType() == Program::TYPE_FRAGMENT) {
1269 // don't load masked inputs, won't be assigned a slot
1270 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1271 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1272 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1273 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1274 return interpolate(src, c, ptr);
1275 }
1276 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1277
1278 case TGSI_FILE_SYSTEM_VALUE:
1279 assert(!ptr);
1280 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1281
1282 case TGSI_FILE_OUTPUT:
1283 case TGSI_FILE_RESOURCE:
1284 case TGSI_FILE_SAMPLER:
1285 case TGSI_FILE_NULL:
1286 default:
1287 assert(!"invalid/unhandled TGSI source file");
1288 return NULL;
1289 }
1290 }
1291
1292 Value *
1293 Converter::acquireDst(int d, int c)
1294 {
1295 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1296
1297 if (dst.isMasked(c))
1298 return NULL;
1299 if (dst.isIndirect(0))
1300 return getScratch();
1301
1302 const int idx = dst.getIndex(0);
1303
1304 switch (dst.getFile()) {
1305 case TGSI_FILE_TEMPORARY:
1306 return tData.acquire(idx, c);
1307 case TGSI_FILE_TEMPORARY_ARRAY:
1308 return getScratch();
1309 case TGSI_FILE_PREDICATE:
1310 return pData.acquire(idx, c);
1311 case TGSI_FILE_ADDRESS:
1312 return aData.acquire(idx, c);
1313
1314 case TGSI_FILE_OUTPUT:
1315 if (prog->getType() == Program::TYPE_FRAGMENT)
1316 return oData.acquire(idx, c);
1317 // fall through
1318 case TGSI_FILE_SYSTEM_VALUE:
1319 return getScratch();
1320
1321 default:
1322 assert(!"invalid dst file");
1323 return NULL;
1324 }
1325 }
1326
1327 void
1328 Converter::storeDst(int d, int c, Value *val)
1329 {
1330 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1331
1332 switch (tgsi.getSaturate()) {
1333 case TGSI_SAT_NONE:
1334 break;
1335 case TGSI_SAT_ZERO_ONE:
1336 mkOp1(OP_SAT, dstTy, val, val);
1337 break;
1338 case TGSI_SAT_MINUS_PLUS_ONE:
1339 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1340 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1341 break;
1342 default:
1343 assert(!"invalid saturation mode");
1344 break;
1345 }
1346
1347 Value *ptr = dst.isIndirect(0) ?
1348 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1349
1350 if (info->io.genUserClip > 0 &&
1351 dst.getFile() == TGSI_FILE_OUTPUT &&
1352 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1353 mkMov(clipVtx[c], val);
1354 val = clipVtx[c];
1355 }
1356
1357 storeDst(dst, c, val, ptr);
1358 }
1359
1360 void
1361 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1362 Value *val, Value *ptr)
1363 {
1364 const int idx = dst.getIndex(0);
1365
1366 switch (dst.getFile()) {
1367 case TGSI_FILE_TEMPORARY:
1368 tData.store(idx, c, ptr, val);
1369 break;
1370 case TGSI_FILE_TEMPORARY_ARRAY:
1371 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1372 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1373 break;
1374 case TGSI_FILE_PREDICATE:
1375 pData.store(idx, c, ptr, val);
1376 break;
1377 case TGSI_FILE_ADDRESS:
1378 aData.store(idx, c, ptr, val);
1379 break;
1380
1381 case TGSI_FILE_OUTPUT:
1382 if (prog->getType() == Program::TYPE_FRAGMENT)
1383 oData.store(idx, c, ptr, val);
1384 else
1385 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1386 break;
1387
1388 case TGSI_FILE_SYSTEM_VALUE:
1389 assert(!ptr);
1390 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1391 break;
1392
1393 default:
1394 assert(!"invalid dst file");
1395 break;
1396 }
1397 }
1398
1399 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1400 for (chan = 0; chan < 4; ++chan) \
1401 if (!inst.getDst(d).isMasked(chan))
1402
1403 Value *
1404 Converter::buildDot(int dim)
1405 {
1406 assert(dim > 0);
1407
1408 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1409 Value *dotp = getScratch();
1410
1411 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1412
1413 for (int c = 1; c < dim; ++c) {
1414 src0 = fetchSrc(0, c);
1415 src1 = fetchSrc(1, c);
1416 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1417 }
1418 return dotp;
1419 }
1420
1421 void
1422 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1423 {
1424 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1425 join->fixed = 1;
1426 conv->insertHead(join);
1427
1428 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1429 fork->insertBefore(fork->getExit(), fork->joinAt);
1430 }
1431
1432 void
1433 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1434 {
1435 unsigned rIdx = 0, sIdx = 0;
1436
1437 if (R >= 0)
1438 rIdx = tgsi.getSrc(R).getIndex(0);
1439 if (S >= 0)
1440 sIdx = tgsi.getSrc(S).getIndex(0);
1441
1442 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1443
1444 if (tgsi.getSrc(R).isIndirect(0)) {
1445 tex->tex.rIndirectSrc = s;
1446 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1447 }
1448 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1449 tex->tex.sIndirectSrc = s;
1450 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1451 }
1452 }
1453
1454 void
1455 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1456 {
1457 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1458 tex->tex.query = query;
1459 unsigned int c, d;
1460
1461 for (d = 0, c = 0; c < 4; ++c) {
1462 if (!dst0[c])
1463 continue;
1464 tex->tex.mask |= 1 << c;
1465 tex->setDef(d++, dst0[c]);
1466 }
1467 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1468
1469 setTexRS(tex, c, 1, -1);
1470
1471 bb->insertTail(tex);
1472 }
1473
1474 void
1475 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1476 {
1477 Value *proj = fetchSrc(0, 3);
1478 Instruction *insn = proj->getUniqueInsn();
1479 int c;
1480
1481 if (insn->op == OP_PINTERP) {
1482 bb->insertTail(insn = insn->clone(true));
1483 insn->op = OP_LINTERP;
1484 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1485 insn->setSrc(1, NULL);
1486 proj = insn->getDef(0);
1487 }
1488 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1489
1490 for (c = 0; c < 4; ++c) {
1491 if (!(mask & (1 << c)))
1492 continue;
1493 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1494 continue;
1495 mask &= ~(1 << c);
1496
1497 bb->insertTail(insn = insn->clone(true));
1498 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1499 insn->setSrc(1, proj);
1500 dst[c] = insn->getDef(0);
1501 }
1502 if (!mask)
1503 return;
1504
1505 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1506
1507 for (c = 0; c < 4; ++c)
1508 if (mask & (1 << c))
1509 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1510 }
1511
1512 // order of nv50 ir sources: x y z layer lod/bias shadow
1513 // order of TGSI TEX sources: x y z layer shadow lod/bias
1514 // lowering will finally set the hw specific order (like array first on nvc0)
1515 void
1516 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1517 {
1518 Value *val;
1519 Value *arg[4], *src[8];
1520 Value *lod = NULL, *shd = NULL;
1521 unsigned int s, c, d;
1522 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1523
1524 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1525
1526 for (s = 0; s < tgt.getArgCount(); ++s)
1527 arg[s] = src[s] = fetchSrc(0, s);
1528
1529 if (texi->op == OP_TXL || texi->op == OP_TXB)
1530 lod = fetchSrc(L >> 4, L & 3);
1531
1532 if (C == 0x0f)
1533 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1534
1535 if (tgt.isShadow())
1536 shd = fetchSrc(C >> 4, C & 3);
1537
1538 if (texi->op == OP_TXD) {
1539 for (c = 0; c < tgt.getDim(); ++c) {
1540 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1541 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1542 }
1543 }
1544
1545 // cube textures don't care about projection value, it's divided out
1546 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1547 unsigned int n = tgt.getDim();
1548 if (shd) {
1549 arg[n] = shd;
1550 ++n;
1551 assert(tgt.getDim() == tgt.getArgCount());
1552 }
1553 loadProjTexCoords(src, arg, (1 << n) - 1);
1554 if (shd)
1555 shd = src[n - 1];
1556 }
1557
1558 if (tgt.isCube()) {
1559 for (c = 0; c < 3; ++c)
1560 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1561 val = getScratch();
1562 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1563 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1564 mkOp1(OP_RCP, TYPE_F32, val, val);
1565 for (c = 0; c < 3; ++c)
1566 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1567 }
1568
1569 for (c = 0, d = 0; c < 4; ++c) {
1570 if (dst[c]) {
1571 texi->setDef(d++, dst[c]);
1572 texi->tex.mask |= 1 << c;
1573 } else {
1574 // NOTE: maybe hook up def too, for CSE
1575 }
1576 }
1577 for (s = 0; s < tgt.getArgCount(); ++s)
1578 texi->setSrc(s, src[s]);
1579 if (lod)
1580 texi->setSrc(s++, lod);
1581 if (shd)
1582 texi->setSrc(s++, shd);
1583
1584 setTexRS(texi, s, R, S);
1585
1586 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1587 texi->tex.levelZero = true;
1588
1589 bb->insertTail(texi);
1590 }
1591
1592 // 1st source: xyz = coordinates, w = lod
1593 // 2nd source: offset
1594 void
1595 Converter::handleTXF(Value *dst[4], int R)
1596 {
1597 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1598 unsigned int c, d, s;
1599
1600 texi->tex.target = tgsi.getTexture(code, R);
1601
1602 for (c = 0, d = 0; c < 4; ++c) {
1603 if (dst[c]) {
1604 texi->setDef(d++, dst[c]);
1605 texi->tex.mask |= 1 << c;
1606 }
1607 }
1608 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1609 texi->setSrc(c, fetchSrc(0, c));
1610 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1611
1612 setTexRS(texi, c, R, -1);
1613
1614 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1615 for (c = 0; c < 3; ++c) {
1616 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1617 if (texi->tex.offset[s][c])
1618 texi->tex.useOffsets = s + 1;
1619 }
1620 }
1621
1622 bb->insertTail(texi);
1623 }
1624
1625 void
1626 Converter::handleLIT(Value *dst0[4])
1627 {
1628 Value *val0 = NULL;
1629 unsigned int mask = tgsi.getDst(0).getMask();
1630
1631 if (mask & (1 << 0))
1632 loadImm(dst0[0], 1.0f);
1633
1634 if (mask & (1 << 3))
1635 loadImm(dst0[3], 1.0f);
1636
1637 if (mask & (3 << 1)) {
1638 val0 = getScratch();
1639 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1640 if (mask & (1 << 1))
1641 mkMov(dst0[1], val0);
1642 }
1643
1644 if (mask & (1 << 2)) {
1645 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1646 Value *val1 = getScratch(), *val3 = getScratch();
1647
1648 Value *pos128 = loadImm(NULL, +127.999999f);
1649 Value *neg128 = loadImm(NULL, -127.999999f);
1650
1651 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1652 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1653 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1654 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1655
1656 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1657 }
1658 }
1659
1660 bool
1661 Converter::isEndOfSubroutine(uint ip)
1662 {
1663 assert(ip < code->scan.num_instructions);
1664 tgsi::Instruction insn(&code->insns[ip]);
1665 return (insn.getOpcode() == TGSI_OPCODE_END ||
1666 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1667 // does END occur at end of main or the very end ?
1668 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1669 }
1670
1671 bool
1672 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1673 {
1674 Value *dst0[4], *rDst0[4];
1675 Value *src0, *src1, *src2;
1676 Value *val0, *val1;
1677 int c;
1678
1679 tgsi = tgsi::Instruction(insn);
1680
1681 bool useScratchDst = tgsi.checkDstSrcAliasing();
1682
1683 operation op = tgsi.getOP();
1684 dstTy = tgsi.inferDstType();
1685 srcTy = tgsi.inferSrcType();
1686
1687 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1688
1689 if (tgsi.dstCount()) {
1690 for (c = 0; c < 4; ++c) {
1691 rDst0[c] = acquireDst(0, c);
1692 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1693 }
1694 }
1695
1696 switch (tgsi.getOpcode()) {
1697 case TGSI_OPCODE_ADD:
1698 case TGSI_OPCODE_UADD:
1699 case TGSI_OPCODE_AND:
1700 case TGSI_OPCODE_DIV:
1701 case TGSI_OPCODE_IDIV:
1702 case TGSI_OPCODE_UDIV:
1703 case TGSI_OPCODE_MAX:
1704 case TGSI_OPCODE_MIN:
1705 case TGSI_OPCODE_IMAX:
1706 case TGSI_OPCODE_IMIN:
1707 case TGSI_OPCODE_UMAX:
1708 case TGSI_OPCODE_UMIN:
1709 case TGSI_OPCODE_MOD:
1710 case TGSI_OPCODE_UMOD:
1711 case TGSI_OPCODE_MUL:
1712 case TGSI_OPCODE_UMUL:
1713 case TGSI_OPCODE_OR:
1714 case TGSI_OPCODE_POW:
1715 case TGSI_OPCODE_SHL:
1716 case TGSI_OPCODE_ISHR:
1717 case TGSI_OPCODE_USHR:
1718 case TGSI_OPCODE_SUB:
1719 case TGSI_OPCODE_XOR:
1720 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1721 src0 = fetchSrc(0, c);
1722 src1 = fetchSrc(1, c);
1723 mkOp2(op, dstTy, dst0[c], src0, src1);
1724 }
1725 break;
1726 case TGSI_OPCODE_MAD:
1727 case TGSI_OPCODE_UMAD:
1728 case TGSI_OPCODE_SAD:
1729 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1730 src0 = fetchSrc(0, c);
1731 src1 = fetchSrc(1, c);
1732 src2 = fetchSrc(2, c);
1733 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1734 }
1735 break;
1736 case TGSI_OPCODE_MOV:
1737 case TGSI_OPCODE_ABS:
1738 case TGSI_OPCODE_CEIL:
1739 case TGSI_OPCODE_FLR:
1740 case TGSI_OPCODE_TRUNC:
1741 case TGSI_OPCODE_RCP:
1742 case TGSI_OPCODE_IABS:
1743 case TGSI_OPCODE_INEG:
1744 case TGSI_OPCODE_NOT:
1745 case TGSI_OPCODE_DDX:
1746 case TGSI_OPCODE_DDY:
1747 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1748 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1749 break;
1750 case TGSI_OPCODE_RSQ:
1751 src0 = fetchSrc(0, 0);
1752 val0 = getScratch();
1753 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1754 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1755 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1756 mkMov(dst0[c], val0);
1757 break;
1758 case TGSI_OPCODE_ARL:
1759 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1760 src0 = fetchSrc(0, c);
1761 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1762 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1763 }
1764 break;
1765 case TGSI_OPCODE_UARL:
1766 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1767 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1768 break;
1769 case TGSI_OPCODE_EX2:
1770 case TGSI_OPCODE_LG2:
1771 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1772 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1773 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1774 break;
1775 case TGSI_OPCODE_COS:
1776 case TGSI_OPCODE_SIN:
1777 val0 = getScratch();
1778 if (mask & 7) {
1779 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1780 mkOp1(op, TYPE_F32, val0, val0);
1781 for (c = 0; c < 3; ++c)
1782 if (dst0[c])
1783 mkMov(dst0[c], val0);
1784 }
1785 if (dst0[3]) {
1786 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1787 mkOp1(op, TYPE_F32, dst0[3], val0);
1788 }
1789 break;
1790 case TGSI_OPCODE_SCS:
1791 if (mask & 3) {
1792 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1793 if (dst0[0])
1794 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1795 if (dst0[1])
1796 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1797 }
1798 if (dst0[2])
1799 loadImm(dst0[2], 0.0f);
1800 if (dst0[3])
1801 loadImm(dst0[3], 1.0f);
1802 break;
1803 case TGSI_OPCODE_EXP:
1804 src0 = fetchSrc(0, 0);
1805 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1806 if (dst0[1])
1807 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1808 if (dst0[0])
1809 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1810 if (dst0[2])
1811 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1812 if (dst0[3])
1813 loadImm(dst0[3], 1.0f);
1814 break;
1815 case TGSI_OPCODE_LOG:
1816 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1817 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1818 if (dst0[0] || dst0[1])
1819 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1820 if (dst0[1]) {
1821 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1822 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1823 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1824 }
1825 if (dst0[3])
1826 loadImm(dst0[3], 1.0f);
1827 break;
1828 case TGSI_OPCODE_DP2:
1829 val0 = buildDot(2);
1830 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1831 mkMov(dst0[c], val0);
1832 break;
1833 case TGSI_OPCODE_DP3:
1834 val0 = buildDot(3);
1835 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1836 mkMov(dst0[c], val0);
1837 break;
1838 case TGSI_OPCODE_DP4:
1839 val0 = buildDot(4);
1840 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1841 mkMov(dst0[c], val0);
1842 break;
1843 case TGSI_OPCODE_DPH:
1844 val0 = buildDot(3);
1845 src1 = fetchSrc(1, 3);
1846 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1847 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1848 mkMov(dst0[c], val0);
1849 break;
1850 case TGSI_OPCODE_DST:
1851 if (dst0[0])
1852 loadImm(dst0[0], 1.0f);
1853 if (dst0[1]) {
1854 src0 = fetchSrc(0, 1);
1855 src1 = fetchSrc(1, 1);
1856 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1857 }
1858 if (dst0[2])
1859 mkMov(dst0[2], fetchSrc(0, 2));
1860 if (dst0[3])
1861 mkMov(dst0[3], fetchSrc(1, 3));
1862 break;
1863 case TGSI_OPCODE_LRP:
1864 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1865 src0 = fetchSrc(0, c);
1866 src1 = fetchSrc(1, c);
1867 src2 = fetchSrc(2, c);
1868 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1869 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1870 }
1871 break;
1872 case TGSI_OPCODE_LIT:
1873 handleLIT(dst0);
1874 break;
1875 case TGSI_OPCODE_XPD:
1876 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1877 if (c < 3) {
1878 val0 = getSSA();
1879 src0 = fetchSrc(1, (c + 1) % 3);
1880 src1 = fetchSrc(0, (c + 2) % 3);
1881 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1882 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1883
1884 src0 = fetchSrc(0, (c + 1) % 3);
1885 src1 = fetchSrc(1, (c + 2) % 3);
1886 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1887 } else {
1888 loadImm(dst0[c], 1.0f);
1889 }
1890 }
1891 break;
1892 case TGSI_OPCODE_SSG:
1893 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1894 src0 = fetchSrc(0, c);
1895 val0 = getScratch();
1896 val1 = getScratch();
1897 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, src0, zero);
1898 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, src0, zero);
1899 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1900 }
1901 break;
1902 case TGSI_OPCODE_UCMP:
1903 case TGSI_OPCODE_CMP:
1904 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1905 src0 = fetchSrc(0, c);
1906 src1 = fetchSrc(1, c);
1907 src2 = fetchSrc(2, c);
1908 if (src1 == src2)
1909 mkMov(dst0[c], src1);
1910 else
1911 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1912 srcTy, dst0[c], src1, src2, src0);
1913 }
1914 break;
1915 case TGSI_OPCODE_FRC:
1916 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1917 src0 = fetchSrc(0, c);
1918 val0 = getScratch();
1919 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1920 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1921 }
1922 break;
1923 case TGSI_OPCODE_ROUND:
1924 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1925 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1926 ->rnd = ROUND_NI;
1927 break;
1928 case TGSI_OPCODE_CLAMP:
1929 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1930 src0 = fetchSrc(0, c);
1931 src1 = fetchSrc(1, c);
1932 src2 = fetchSrc(2, c);
1933 val0 = getScratch();
1934 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1935 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1936 }
1937 break;
1938 case TGSI_OPCODE_SLT:
1939 case TGSI_OPCODE_SGE:
1940 case TGSI_OPCODE_SEQ:
1941 case TGSI_OPCODE_SFL:
1942 case TGSI_OPCODE_SGT:
1943 case TGSI_OPCODE_SLE:
1944 case TGSI_OPCODE_SNE:
1945 case TGSI_OPCODE_STR:
1946 case TGSI_OPCODE_ISGE:
1947 case TGSI_OPCODE_ISLT:
1948 case TGSI_OPCODE_USEQ:
1949 case TGSI_OPCODE_USGE:
1950 case TGSI_OPCODE_USLT:
1951 case TGSI_OPCODE_USNE:
1952 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1953 src0 = fetchSrc(0, c);
1954 src1 = fetchSrc(1, c);
1955 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1956 }
1957 break;
1958 case TGSI_OPCODE_KIL:
1959 val0 = new_LValue(func, FILE_PREDICATE);
1960 for (c = 0; c < 4; ++c) {
1961 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1962 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1963 }
1964 break;
1965 case TGSI_OPCODE_KILP:
1966 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1967 break;
1968 case TGSI_OPCODE_TEX:
1969 case TGSI_OPCODE_TXB:
1970 case TGSI_OPCODE_TXL:
1971 case TGSI_OPCODE_TXP:
1972 // R S L C Dx Dy
1973 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1974 break;
1975 case TGSI_OPCODE_TXD:
1976 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1977 break;
1978 case TGSI_OPCODE_SAMPLE:
1979 case TGSI_OPCODE_SAMPLE_B:
1980 case TGSI_OPCODE_SAMPLE_D:
1981 case TGSI_OPCODE_SAMPLE_L:
1982 case TGSI_OPCODE_SAMPLE_C:
1983 case TGSI_OPCODE_SAMPLE_C_LZ:
1984 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
1985 break;
1986 case TGSI_OPCODE_TXF:
1987 case TGSI_OPCODE_LOAD:
1988 handleTXF(dst0, 1);
1989 break;
1990 case TGSI_OPCODE_TXQ:
1991 case TGSI_OPCODE_RESINFO:
1992 handleTXQ(dst0, TXQ_DIMS);
1993 break;
1994 case TGSI_OPCODE_F2I:
1995 case TGSI_OPCODE_F2U:
1996 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1997 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
1998 break;
1999 case TGSI_OPCODE_I2F:
2000 case TGSI_OPCODE_U2F:
2001 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2002 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2003 break;
2004 case TGSI_OPCODE_EMIT:
2005 case TGSI_OPCODE_ENDPRIM:
2006 // get vertex stream if specified (must be immediate)
2007 src0 = tgsi.srcCount() ?
2008 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2009 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2010 break;
2011 case TGSI_OPCODE_IF:
2012 {
2013 BasicBlock *ifBB = new BasicBlock(func);
2014
2015 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2016 condBBs.push(bb);
2017 joinBBs.push(bb);
2018
2019 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2020
2021 setPosition(ifBB, true);
2022 }
2023 break;
2024 case TGSI_OPCODE_ELSE:
2025 {
2026 BasicBlock *elseBB = new BasicBlock(func);
2027 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2028
2029 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2030 condBBs.push(bb);
2031
2032 forkBB->getExit()->asFlow()->target.bb = elseBB;
2033 if (!bb->isTerminated())
2034 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2035
2036 setPosition(elseBB, true);
2037 }
2038 break;
2039 case TGSI_OPCODE_ENDIF:
2040 {
2041 BasicBlock *convBB = new BasicBlock(func);
2042 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2043 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2044
2045 if (!bb->isTerminated()) {
2046 // we only want join if none of the clauses ended with CONT/BREAK/RET
2047 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2048 insertConvergenceOps(convBB, forkBB);
2049 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2050 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2051 }
2052
2053 if (prevBB->getExit()->op == OP_BRA) {
2054 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2055 prevBB->getExit()->asFlow()->target.bb = convBB;
2056 }
2057 setPosition(convBB, true);
2058 }
2059 break;
2060 case TGSI_OPCODE_BGNLOOP:
2061 {
2062 BasicBlock *lbgnBB = new BasicBlock(func);
2063 BasicBlock *lbrkBB = new BasicBlock(func);
2064
2065 loopBBs.push(lbgnBB);
2066 breakBBs.push(lbrkBB);
2067 if (loopBBs.getSize() > func->loopNestingBound)
2068 func->loopNestingBound++;
2069
2070 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2071
2072 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2073 setPosition(lbgnBB, true);
2074 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2075 }
2076 break;
2077 case TGSI_OPCODE_ENDLOOP:
2078 {
2079 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2080
2081 if (!bb->isTerminated()) {
2082 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2083 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2084 }
2085 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2086 }
2087 break;
2088 case TGSI_OPCODE_BRK:
2089 {
2090 if (bb->isTerminated())
2091 break;
2092 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2093 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2094 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2095 }
2096 break;
2097 case TGSI_OPCODE_CONT:
2098 {
2099 if (bb->isTerminated())
2100 break;
2101 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2102 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2103 contBB->explicitCont = true;
2104 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2105 }
2106 break;
2107 case TGSI_OPCODE_BGNSUB:
2108 {
2109 if (!retIPs.getSize()) {
2110 // end of main function
2111 ip = code->scan.num_instructions - 2; // goto END
2112 return true;
2113 }
2114 BasicBlock *entry = new BasicBlock(func);
2115 BasicBlock *leave = new BasicBlock(func);
2116 entryBBs.push(entry);
2117 leaveBBs.push(leave);
2118 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2119 setPosition(entry, true);
2120 }
2121 return true;
2122 case TGSI_OPCODE_ENDSUB:
2123 {
2124 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2125 entryBBs.pop();
2126 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2127 setPosition(leave, true);
2128 ip = retIPs.pop().u.u;
2129 }
2130 return true;
2131 case TGSI_OPCODE_CAL:
2132 // we don't have function declarations, so inline everything
2133 retIPs.push(ip);
2134 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2135 return true;
2136 case TGSI_OPCODE_RET:
2137 {
2138 if (bb->isTerminated())
2139 return true;
2140 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2141 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2142 if (!isEndOfSubroutine(ip + 1)) {
2143 // insert a PRERET at the entry if this is an early return
2144 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2145 preRet->fixed = 1;
2146 entry->insertHead(preRet);
2147 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2148 }
2149 // everything inlined so RET serves only to wrap up the stack
2150 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2151 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2152 }
2153 break;
2154 case TGSI_OPCODE_END:
2155 {
2156 // attach and generate epilogue code
2157 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2158 entryBBs.pop();
2159 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2160 setPosition(epilogue, true);
2161 if (prog->getType() == Program::TYPE_FRAGMENT)
2162 exportOutputs();
2163 if (info->io.genUserClip > 0)
2164 handleUserClipPlanes();
2165 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2166 }
2167 break;
2168 case TGSI_OPCODE_SWITCH:
2169 case TGSI_OPCODE_CASE:
2170 ERROR("switch/case opcode encountered, should have been lowered\n");
2171 abort();
2172 break;
2173 default:
2174 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2175 assert(0);
2176 break;
2177 }
2178
2179 if (tgsi.dstCount()) {
2180 for (c = 0; c < 4; ++c) {
2181 if (!dst0[c])
2182 continue;
2183 if (dst0[c] != rDst0[c])
2184 mkMov(rDst0[c], dst0[c]);
2185 storeDst(0, c, rDst0[c]);
2186 }
2187 }
2188 vtxBaseValid = 0;
2189
2190 return true;
2191 }
2192
2193 void
2194 Converter::handleUserClipPlanes()
2195 {
2196 Value *res[8];
2197 int i, c;
2198
2199 for (c = 0; c < 4; ++c) {
2200 for (i = 0; i < info->io.genUserClip; ++i) {
2201 Value *ucp;
2202 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2203 i * 16 + c * 4), NULL);
2204 if (c == 0)
2205 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2206 else
2207 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2208 }
2209 }
2210
2211 for (i = 0; i < info->io.genUserClip; ++i)
2212 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2213 }
2214
2215 void
2216 Converter::exportOutputs()
2217 {
2218 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2219 for (unsigned int c = 0; c < 4; ++c) {
2220 if (!oData.exists(i, c))
2221 continue;
2222 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2223 info->out[i].slot[c] * 4);
2224 Value *val = oData.load(i, c, NULL);
2225 if (val)
2226 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2227 }
2228 }
2229 }
2230
2231 Converter::Converter(Program *ir, const tgsi::Source *src)
2232 : code(src),
2233 tgsi(NULL),
2234 tData(this), aData(this), pData(this), oData(this)
2235 {
2236 prog = ir;
2237 info = code->info;
2238
2239 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2240
2241 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2242 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2243 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2244 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2245
2246 lData = NULL;
2247 iData = NULL;
2248
2249 zero = mkImm((uint32_t)0);
2250
2251 vtxBaseValid = 0;
2252 }
2253
2254 Converter::~Converter()
2255 {
2256 if (lData)
2257 delete[] lData;
2258 if (iData)
2259 delete[] iData;
2260 }
2261
2262 bool
2263 Converter::run()
2264 {
2265 BasicBlock *entry = new BasicBlock(prog->main);
2266 BasicBlock *leave = new BasicBlock(prog->main);
2267
2268 if (code->tempArrayCount && !lData) {
2269 uint32_t volume = 0;
2270 lData = new DataArray[code->tempArrayCount];
2271 if (!lData)
2272 return false;
2273 for (int i = 0; i < code->tempArrayCount; ++i) {
2274 int len = code->tempArrays[i].u32 >> 2;
2275 int dim = code->tempArrays[i].u32 & 3;
2276 lData[i].setParent(this);
2277 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2278 volume += (len * dim * 4 + 0xf) & ~0xf;
2279 }
2280 }
2281 if (code->immdArrayCount && !iData) {
2282 uint32_t volume = 0;
2283 iData = new DataArray[code->immdArrayCount];
2284 if (!iData)
2285 return false;
2286 for (int i = 0; i < code->immdArrayCount; ++i) {
2287 int len = code->immdArrays[i].u32 >> 2;
2288 int dim = code->immdArrays[i].u32 & 3;
2289 iData[i].setParent(this);
2290 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2291 volume += (len * dim * 4 + 0xf) & ~0xf;
2292 }
2293 }
2294
2295 prog->main->setEntry(entry);
2296 prog->main->setExit(leave);
2297
2298 setPosition(entry, true);
2299 entryBBs.push(entry);
2300 leaveBBs.push(leave);
2301
2302 if (info->io.genUserClip > 0) {
2303 for (int c = 0; c < 4; ++c)
2304 clipVtx[c] = getScratch();
2305 }
2306
2307 if (prog->getType() == Program::TYPE_FRAGMENT) {
2308 Symbol *sv = mkSysVal(SV_POSITION, 3);
2309 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2310 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2311 }
2312
2313 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2314 if (!handleInstruction(&code->insns[ip]))
2315 return false;
2316 }
2317 return true;
2318 }
2319
2320 } // unnamed namespace
2321
2322 namespace nv50_ir {
2323
2324 bool
2325 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2326 {
2327 tgsi::Source src(info);
2328 if (!src.scanSource())
2329 return false;
2330
2331 Converter builder(this, &src);
2332 return builder.run();
2333 }
2334
2335 } // namespace nv50_ir