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[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_util.h"
27 }
28
29 #include <set>
30
31 #include "nv50_ir.h"
32 #include "nv50_ir_util.h"
33 #include "nv50_ir_build_util.h"
34
35 namespace tgsi {
36
37 class Source;
38
39 static nv50_ir::operation translateOpcode(uint opcode);
40 static nv50_ir::DataFile translateFile(uint file);
41 static nv50_ir::TexTarget translateTexture(uint texTarg);
42 static nv50_ir::SVSemantic translateSysVal(uint sysval);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 nv50_ir::Modifier getMod(int chan) const;
101
102 SrcRegister getIndirect(int dim) const
103 {
104 assert(fsr && isIndirect(dim));
105 if (dim)
106 return SrcRegister(fsr->DimIndirect);
107 return SrcRegister(fsr->Indirect);
108 }
109
110 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
111 {
112 assert(reg.File == TGSI_FILE_IMMEDIATE);
113 assert(!reg.Absolute);
114 assert(!reg.Negate);
115 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
116 }
117
118 private:
119 const struct tgsi_src_register reg;
120 const struct tgsi_full_src_register *fsr;
121 };
122
123 class DstRegister
124 {
125 public:
126 DstRegister(const struct tgsi_full_dst_register *dst)
127 : reg(dst->Register),
128 fdr(dst)
129 { }
130
131 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
132
133 uint getFile() const { return reg.File; }
134
135 bool is2D() const { return reg.Dimension; }
136
137 bool isIndirect(int dim) const
138 {
139 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
140 }
141
142 int getIndex(int dim) const
143 {
144 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
145 }
146
147 unsigned int getMask() const { return reg.WriteMask; }
148
149 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
150
151 SrcRegister getIndirect(int dim) const
152 {
153 assert(fdr && isIndirect(dim));
154 if (dim)
155 return SrcRegister(fdr->DimIndirect);
156 return SrcRegister(fdr->Indirect);
157 }
158
159 private:
160 const struct tgsi_dst_register reg;
161 const struct tgsi_full_dst_register *fdr;
162 };
163
164 inline uint getOpcode() const { return insn->Instruction.Opcode; }
165
166 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
167 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
168
169 // mask of used components of source s
170 unsigned int srcMask(unsigned int s) const;
171
172 SrcRegister getSrc(unsigned int s) const
173 {
174 assert(s < srcCount());
175 return SrcRegister(&insn->Src[s]);
176 }
177
178 DstRegister getDst(unsigned int d) const
179 {
180 assert(d < dstCount());
181 return DstRegister(&insn->Dst[d]);
182 }
183
184 SrcRegister getTexOffset(unsigned int i) const
185 {
186 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
187 return SrcRegister(insn->TexOffsets[i]);
188 }
189
190 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
191
192 bool checkDstSrcAliasing() const;
193
194 inline nv50_ir::operation getOP() const {
195 return translateOpcode(getOpcode()); }
196
197 nv50_ir::DataType inferSrcType() const;
198 nv50_ir::DataType inferDstType() const;
199
200 nv50_ir::CondCode getSetCond() const;
201
202 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
203
204 inline uint getLabel() { return insn->Label.Label; }
205
206 unsigned getSaturate() const { return insn->Instruction.Saturate; }
207
208 void print() const
209 {
210 tgsi_dump_instruction(insn, 1);
211 }
212
213 private:
214 const struct tgsi_full_instruction *insn;
215 };
216
217 unsigned int Instruction::srcMask(unsigned int s) const
218 {
219 unsigned int mask = insn->Dst[0].Register.WriteMask;
220
221 switch (insn->Instruction.Opcode) {
222 case TGSI_OPCODE_COS:
223 case TGSI_OPCODE_SIN:
224 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
225 case TGSI_OPCODE_DP2:
226 return 0x3;
227 case TGSI_OPCODE_DP3:
228 return 0x7;
229 case TGSI_OPCODE_DP4:
230 case TGSI_OPCODE_DPH:
231 case TGSI_OPCODE_KIL: /* WriteMask ignored */
232 return 0xf;
233 case TGSI_OPCODE_DST:
234 return mask & (s ? 0xa : 0x6);
235 case TGSI_OPCODE_EX2:
236 case TGSI_OPCODE_EXP:
237 case TGSI_OPCODE_LG2:
238 case TGSI_OPCODE_LOG:
239 case TGSI_OPCODE_POW:
240 case TGSI_OPCODE_RCP:
241 case TGSI_OPCODE_RSQ:
242 case TGSI_OPCODE_SCS:
243 return 0x1;
244 case TGSI_OPCODE_IF:
245 return 0x1;
246 case TGSI_OPCODE_LIT:
247 return 0xb;
248 case TGSI_OPCODE_TEX2:
249 case TGSI_OPCODE_TXB2:
250 case TGSI_OPCODE_TXL2:
251 return (s == 0) ? 0xf : 0x3;
252 case TGSI_OPCODE_TEX:
253 case TGSI_OPCODE_TXB:
254 case TGSI_OPCODE_TXD:
255 case TGSI_OPCODE_TXL:
256 case TGSI_OPCODE_TXP:
257 {
258 const struct tgsi_instruction_texture *tex = &insn->Texture;
259
260 assert(insn->Instruction.Texture);
261
262 mask = 0x7;
263 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
264 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
265 mask |= 0x8; /* bias, lod or proj */
266
267 switch (tex->Texture) {
268 case TGSI_TEXTURE_1D:
269 mask &= 0x9;
270 break;
271 case TGSI_TEXTURE_SHADOW1D:
272 mask &= 0xd;
273 break;
274 case TGSI_TEXTURE_1D_ARRAY:
275 case TGSI_TEXTURE_2D:
276 case TGSI_TEXTURE_RECT:
277 mask &= 0xb;
278 break;
279 case TGSI_TEXTURE_CUBE_ARRAY:
280 case TGSI_TEXTURE_SHADOW2D_ARRAY:
281 case TGSI_TEXTURE_SHADOWCUBE:
282 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
283 mask |= 0x8;
284 break;
285 default:
286 break;
287 }
288 }
289 return mask;
290 case TGSI_OPCODE_XPD:
291 {
292 unsigned int x = 0;
293 if (mask & 1) x |= 0x6;
294 if (mask & 2) x |= 0x5;
295 if (mask & 4) x |= 0x3;
296 return x;
297 }
298 default:
299 break;
300 }
301
302 return mask;
303 }
304
305 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
306 {
307 nv50_ir::Modifier m(0);
308
309 if (reg.Absolute)
310 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
311 if (reg.Negate)
312 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
313 return m;
314 }
315
316 static nv50_ir::DataFile translateFile(uint file)
317 {
318 switch (file) {
319 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
320 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
321 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
322 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
323 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
324 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
325 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
326 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
327 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
328 case TGSI_FILE_SAMPLER:
329 case TGSI_FILE_NULL:
330 default:
331 return nv50_ir::FILE_NULL;
332 }
333 }
334
335 static nv50_ir::SVSemantic translateSysVal(uint sysval)
336 {
337 switch (sysval) {
338 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
339 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
340 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
341 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
342 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
343 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
344 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
345 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
346 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
347 default:
348 assert(0);
349 return nv50_ir::SV_CLOCK;
350 }
351 }
352
353 #define NV50_IR_TEX_TARG_CASE(a, b) \
354 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
355
356 static nv50_ir::TexTarget translateTexture(uint tex)
357 {
358 switch (tex) {
359 NV50_IR_TEX_TARG_CASE(1D, 1D);
360 NV50_IR_TEX_TARG_CASE(2D, 2D);
361 NV50_IR_TEX_TARG_CASE(3D, 3D);
362 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
363 NV50_IR_TEX_TARG_CASE(RECT, RECT);
364 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
365 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
366 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
367 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
368 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
369 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
370 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
371 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
372 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
373 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
374 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
375
376 case TGSI_TEXTURE_UNKNOWN:
377 default:
378 assert(!"invalid texture target");
379 return nv50_ir::TEX_TARGET_2D;
380 }
381 }
382
383 nv50_ir::DataType Instruction::inferSrcType() const
384 {
385 switch (getOpcode()) {
386 case TGSI_OPCODE_AND:
387 case TGSI_OPCODE_OR:
388 case TGSI_OPCODE_XOR:
389 case TGSI_OPCODE_NOT:
390 case TGSI_OPCODE_U2F:
391 case TGSI_OPCODE_UADD:
392 case TGSI_OPCODE_UDIV:
393 case TGSI_OPCODE_UMOD:
394 case TGSI_OPCODE_UMAD:
395 case TGSI_OPCODE_UMUL:
396 case TGSI_OPCODE_UMAX:
397 case TGSI_OPCODE_UMIN:
398 case TGSI_OPCODE_USEQ:
399 case TGSI_OPCODE_USGE:
400 case TGSI_OPCODE_USLT:
401 case TGSI_OPCODE_USNE:
402 case TGSI_OPCODE_USHR:
403 case TGSI_OPCODE_UCMP:
404 case TGSI_OPCODE_ATOMUADD:
405 case TGSI_OPCODE_ATOMXCHG:
406 case TGSI_OPCODE_ATOMCAS:
407 case TGSI_OPCODE_ATOMAND:
408 case TGSI_OPCODE_ATOMOR:
409 case TGSI_OPCODE_ATOMXOR:
410 case TGSI_OPCODE_ATOMUMIN:
411 case TGSI_OPCODE_ATOMUMAX:
412 return nv50_ir::TYPE_U32;
413 case TGSI_OPCODE_I2F:
414 case TGSI_OPCODE_IDIV:
415 case TGSI_OPCODE_IMAX:
416 case TGSI_OPCODE_IMIN:
417 case TGSI_OPCODE_IABS:
418 case TGSI_OPCODE_INEG:
419 case TGSI_OPCODE_ISGE:
420 case TGSI_OPCODE_ISHR:
421 case TGSI_OPCODE_ISLT:
422 case TGSI_OPCODE_ISSG:
423 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
424 case TGSI_OPCODE_MOD:
425 case TGSI_OPCODE_UARL:
426 case TGSI_OPCODE_ATOMIMIN:
427 case TGSI_OPCODE_ATOMIMAX:
428 return nv50_ir::TYPE_S32;
429 default:
430 return nv50_ir::TYPE_F32;
431 }
432 }
433
434 nv50_ir::DataType Instruction::inferDstType() const
435 {
436 switch (getOpcode()) {
437 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
438 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
439 case TGSI_OPCODE_I2F:
440 case TGSI_OPCODE_U2F:
441 return nv50_ir::TYPE_F32;
442 default:
443 return inferSrcType();
444 }
445 }
446
447 nv50_ir::CondCode Instruction::getSetCond() const
448 {
449 using namespace nv50_ir;
450
451 switch (getOpcode()) {
452 case TGSI_OPCODE_SLT:
453 case TGSI_OPCODE_ISLT:
454 case TGSI_OPCODE_USLT:
455 return CC_LT;
456 case TGSI_OPCODE_SLE:
457 return CC_LE;
458 case TGSI_OPCODE_SGE:
459 case TGSI_OPCODE_ISGE:
460 case TGSI_OPCODE_USGE:
461 return CC_GE;
462 case TGSI_OPCODE_SGT:
463 return CC_GT;
464 case TGSI_OPCODE_SEQ:
465 case TGSI_OPCODE_USEQ:
466 return CC_EQ;
467 case TGSI_OPCODE_SNE:
468 return CC_NEU;
469 case TGSI_OPCODE_USNE:
470 return CC_NE;
471 case TGSI_OPCODE_SFL:
472 return CC_NEVER;
473 case TGSI_OPCODE_STR:
474 default:
475 return CC_ALWAYS;
476 }
477 }
478
479 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
480
481 static nv50_ir::operation translateOpcode(uint opcode)
482 {
483 switch (opcode) {
484 NV50_IR_OPCODE_CASE(ARL, SHL);
485 NV50_IR_OPCODE_CASE(MOV, MOV);
486
487 NV50_IR_OPCODE_CASE(RCP, RCP);
488 NV50_IR_OPCODE_CASE(RSQ, RSQ);
489
490 NV50_IR_OPCODE_CASE(MUL, MUL);
491 NV50_IR_OPCODE_CASE(ADD, ADD);
492
493 NV50_IR_OPCODE_CASE(MIN, MIN);
494 NV50_IR_OPCODE_CASE(MAX, MAX);
495 NV50_IR_OPCODE_CASE(SLT, SET);
496 NV50_IR_OPCODE_CASE(SGE, SET);
497 NV50_IR_OPCODE_CASE(MAD, MAD);
498 NV50_IR_OPCODE_CASE(SUB, SUB);
499
500 NV50_IR_OPCODE_CASE(FLR, FLOOR);
501 NV50_IR_OPCODE_CASE(ROUND, CVT);
502 NV50_IR_OPCODE_CASE(EX2, EX2);
503 NV50_IR_OPCODE_CASE(LG2, LG2);
504 NV50_IR_OPCODE_CASE(POW, POW);
505
506 NV50_IR_OPCODE_CASE(ABS, ABS);
507
508 NV50_IR_OPCODE_CASE(COS, COS);
509 NV50_IR_OPCODE_CASE(DDX, DFDX);
510 NV50_IR_OPCODE_CASE(DDY, DFDY);
511 NV50_IR_OPCODE_CASE(KILP, DISCARD);
512
513 NV50_IR_OPCODE_CASE(SEQ, SET);
514 NV50_IR_OPCODE_CASE(SFL, SET);
515 NV50_IR_OPCODE_CASE(SGT, SET);
516 NV50_IR_OPCODE_CASE(SIN, SIN);
517 NV50_IR_OPCODE_CASE(SLE, SET);
518 NV50_IR_OPCODE_CASE(SNE, SET);
519 NV50_IR_OPCODE_CASE(STR, SET);
520 NV50_IR_OPCODE_CASE(TEX, TEX);
521 NV50_IR_OPCODE_CASE(TXD, TXD);
522 NV50_IR_OPCODE_CASE(TXP, TEX);
523
524 NV50_IR_OPCODE_CASE(BRA, BRA);
525 NV50_IR_OPCODE_CASE(CAL, CALL);
526 NV50_IR_OPCODE_CASE(RET, RET);
527 NV50_IR_OPCODE_CASE(CMP, SLCT);
528
529 NV50_IR_OPCODE_CASE(TXB, TXB);
530
531 NV50_IR_OPCODE_CASE(DIV, DIV);
532
533 NV50_IR_OPCODE_CASE(TXL, TXL);
534
535 NV50_IR_OPCODE_CASE(CEIL, CEIL);
536 NV50_IR_OPCODE_CASE(I2F, CVT);
537 NV50_IR_OPCODE_CASE(NOT, NOT);
538 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
539 NV50_IR_OPCODE_CASE(SHL, SHL);
540
541 NV50_IR_OPCODE_CASE(AND, AND);
542 NV50_IR_OPCODE_CASE(OR, OR);
543 NV50_IR_OPCODE_CASE(MOD, MOD);
544 NV50_IR_OPCODE_CASE(XOR, XOR);
545 NV50_IR_OPCODE_CASE(SAD, SAD);
546 NV50_IR_OPCODE_CASE(TXF, TXF);
547 NV50_IR_OPCODE_CASE(TXQ, TXQ);
548
549 NV50_IR_OPCODE_CASE(EMIT, EMIT);
550 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
551
552 NV50_IR_OPCODE_CASE(KIL, DISCARD);
553
554 NV50_IR_OPCODE_CASE(F2I, CVT);
555 NV50_IR_OPCODE_CASE(IDIV, DIV);
556 NV50_IR_OPCODE_CASE(IMAX, MAX);
557 NV50_IR_OPCODE_CASE(IMIN, MIN);
558 NV50_IR_OPCODE_CASE(IABS, ABS);
559 NV50_IR_OPCODE_CASE(INEG, NEG);
560 NV50_IR_OPCODE_CASE(ISGE, SET);
561 NV50_IR_OPCODE_CASE(ISHR, SHR);
562 NV50_IR_OPCODE_CASE(ISLT, SET);
563 NV50_IR_OPCODE_CASE(F2U, CVT);
564 NV50_IR_OPCODE_CASE(U2F, CVT);
565 NV50_IR_OPCODE_CASE(UADD, ADD);
566 NV50_IR_OPCODE_CASE(UDIV, DIV);
567 NV50_IR_OPCODE_CASE(UMAD, MAD);
568 NV50_IR_OPCODE_CASE(UMAX, MAX);
569 NV50_IR_OPCODE_CASE(UMIN, MIN);
570 NV50_IR_OPCODE_CASE(UMOD, MOD);
571 NV50_IR_OPCODE_CASE(UMUL, MUL);
572 NV50_IR_OPCODE_CASE(USEQ, SET);
573 NV50_IR_OPCODE_CASE(USGE, SET);
574 NV50_IR_OPCODE_CASE(USHR, SHR);
575 NV50_IR_OPCODE_CASE(USLT, SET);
576 NV50_IR_OPCODE_CASE(USNE, SET);
577
578 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
579 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
580 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
581 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
582 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
583 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
584 NV50_IR_OPCODE_CASE(GATHER4, TXG);
585 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
586
587 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
588 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
589 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
590 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
591 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
592 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
593 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
594 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
595 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
596 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
597
598 NV50_IR_OPCODE_CASE(TEX2, TEX);
599 NV50_IR_OPCODE_CASE(TXB2, TXB);
600 NV50_IR_OPCODE_CASE(TXL2, TXL);
601
602 NV50_IR_OPCODE_CASE(END, EXIT);
603
604 default:
605 return nv50_ir::OP_NOP;
606 }
607 }
608
609 static uint16_t opcodeToSubOp(uint opcode)
610 {
611 switch (opcode) {
612 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
613 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
614 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
615 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
616 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
617 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
618 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
619 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
620 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
621 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
622 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
623 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
624 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
625 default:
626 return 0;
627 }
628 }
629
630 bool Instruction::checkDstSrcAliasing() const
631 {
632 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
633 return false;
634
635 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
636 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
637 break;
638 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
639 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
640 return true;
641 }
642 return false;
643 }
644
645 class Source
646 {
647 public:
648 Source(struct nv50_ir_prog_info *);
649 ~Source();
650
651 public:
652 bool scanSource();
653 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
654
655 public:
656 struct tgsi_shader_info scan;
657 struct tgsi_full_instruction *insns;
658 const struct tgsi_token *tokens;
659 struct nv50_ir_prog_info *info;
660
661 nv50_ir::DynArray tempArrays;
662 nv50_ir::DynArray immdArrays;
663
664 typedef nv50_ir::BuildUtil::Location Location;
665 // these registers are per-subroutine, cannot be used for parameter passing
666 std::set<Location> locals;
667
668 bool mainTempsInLMem;
669
670 int clipVertexOutput;
671
672 struct TextureView {
673 uint8_t target; // TGSI_TEXTURE_*
674 };
675 std::vector<TextureView> textureViews;
676
677 struct Resource {
678 uint8_t target; // TGSI_TEXTURE_*
679 bool raw;
680 uint8_t slot; // $surface index
681 };
682 std::vector<Resource> resources;
683
684 private:
685 int inferSysValDirection(unsigned sn) const;
686 bool scanDeclaration(const struct tgsi_full_declaration *);
687 bool scanInstruction(const struct tgsi_full_instruction *);
688 void scanProperty(const struct tgsi_full_property *);
689 void scanImmediate(const struct tgsi_full_immediate *);
690
691 inline bool isEdgeFlagPassthrough(const Instruction&) const;
692 };
693
694 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
695 {
696 tokens = (const struct tgsi_token *)info->bin.source;
697
698 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
699 tgsi_dump(tokens, 0);
700
701 mainTempsInLMem = FALSE;
702 }
703
704 Source::~Source()
705 {
706 if (insns)
707 FREE(insns);
708
709 if (info->immd.data)
710 FREE(info->immd.data);
711 if (info->immd.type)
712 FREE(info->immd.type);
713 }
714
715 bool Source::scanSource()
716 {
717 unsigned insnCount = 0;
718 struct tgsi_parse_context parse;
719
720 tgsi_scan_shader(tokens, &scan);
721
722 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
723 sizeof(insns[0]));
724 if (!insns)
725 return false;
726
727 clipVertexOutput = -1;
728
729 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
730 resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
731
732 info->immd.bufSize = 0;
733
734 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
735 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
736 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
737
738 if (info->type == PIPE_SHADER_FRAGMENT) {
739 info->prop.fp.writesDepth = scan.writes_z;
740 info->prop.fp.usesDiscard = scan.uses_kill;
741 } else
742 if (info->type == PIPE_SHADER_GEOMETRY) {
743 info->prop.gp.instanceCount = 1; // default value
744 }
745
746 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
747 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
748
749 tgsi_parse_init(&parse, tokens);
750 while (!tgsi_parse_end_of_tokens(&parse)) {
751 tgsi_parse_token(&parse);
752
753 switch (parse.FullToken.Token.Type) {
754 case TGSI_TOKEN_TYPE_IMMEDIATE:
755 scanImmediate(&parse.FullToken.FullImmediate);
756 break;
757 case TGSI_TOKEN_TYPE_DECLARATION:
758 scanDeclaration(&parse.FullToken.FullDeclaration);
759 break;
760 case TGSI_TOKEN_TYPE_INSTRUCTION:
761 insns[insnCount++] = parse.FullToken.FullInstruction;
762 scanInstruction(&parse.FullToken.FullInstruction);
763 break;
764 case TGSI_TOKEN_TYPE_PROPERTY:
765 scanProperty(&parse.FullToken.FullProperty);
766 break;
767 default:
768 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
769 break;
770 }
771 }
772 tgsi_parse_free(&parse);
773
774 if (mainTempsInLMem)
775 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
776
777 if (info->io.genUserClip > 0) {
778 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
779
780 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
781
782 for (unsigned int n = 0; n < nOut; ++n) {
783 unsigned int i = info->numOutputs++;
784 info->out[i].id = i;
785 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
786 info->out[i].si = n;
787 info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
788 }
789 }
790
791 return info->assignSlots(info) == 0;
792 }
793
794 void Source::scanProperty(const struct tgsi_full_property *prop)
795 {
796 switch (prop->Property.PropertyName) {
797 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
798 info->prop.gp.outputPrim = prop->u[0].Data;
799 break;
800 case TGSI_PROPERTY_GS_INPUT_PRIM:
801 info->prop.gp.inputPrim = prop->u[0].Data;
802 break;
803 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
804 info->prop.gp.maxVertices = prop->u[0].Data;
805 break;
806 #if 0
807 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
808 info->prop.gp.instanceCount = prop->u[0].Data;
809 break;
810 #endif
811 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
812 info->prop.fp.separateFragData = TRUE;
813 break;
814 case TGSI_PROPERTY_FS_COORD_ORIGIN:
815 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
816 // we don't care
817 break;
818 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
819 info->io.genUserClip = -1;
820 break;
821 default:
822 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
823 break;
824 }
825 }
826
827 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
828 {
829 const unsigned n = info->immd.count++;
830
831 assert(n < scan.immediate_count);
832
833 for (int c = 0; c < 4; ++c)
834 info->immd.data[n * 4 + c] = imm->u[c].Uint;
835
836 info->immd.type[n] = imm->Immediate.DataType;
837 }
838
839 int Source::inferSysValDirection(unsigned sn) const
840 {
841 switch (sn) {
842 case TGSI_SEMANTIC_INSTANCEID:
843 case TGSI_SEMANTIC_VERTEXID:
844 return 1;
845 #if 0
846 case TGSI_SEMANTIC_LAYER:
847 case TGSI_SEMANTIC_VIEWPORTINDEX:
848 return 0;
849 #endif
850 case TGSI_SEMANTIC_PRIMID:
851 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
852 default:
853 return 0;
854 }
855 }
856
857 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
858 {
859 unsigned i, c;
860 unsigned sn = TGSI_SEMANTIC_GENERIC;
861 unsigned si = 0;
862 const unsigned first = decl->Range.First, last = decl->Range.Last;
863
864 if (decl->Declaration.Semantic) {
865 sn = decl->Semantic.Name;
866 si = decl->Semantic.Index;
867 }
868
869 if (decl->Declaration.Local) {
870 for (i = first; i <= last; ++i) {
871 for (c = 0; c < 4; ++c) {
872 locals.insert(
873 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
874 }
875 }
876 }
877
878 switch (decl->Declaration.File) {
879 case TGSI_FILE_INPUT:
880 if (info->type == PIPE_SHADER_VERTEX) {
881 // all vertex attributes are equal
882 for (i = first; i <= last; ++i) {
883 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
884 info->in[i].si = i;
885 }
886 } else {
887 for (i = first; i <= last; ++i, ++si) {
888 info->in[i].id = i;
889 info->in[i].sn = sn;
890 info->in[i].si = si;
891 if (info->type == PIPE_SHADER_FRAGMENT) {
892 // translate interpolation mode
893 switch (decl->Interp.Interpolate) {
894 case TGSI_INTERPOLATE_CONSTANT:
895 info->in[i].flat = 1;
896 break;
897 case TGSI_INTERPOLATE_COLOR:
898 info->in[i].sc = 1;
899 break;
900 case TGSI_INTERPOLATE_LINEAR:
901 info->in[i].linear = 1;
902 break;
903 default:
904 break;
905 }
906 if (decl->Interp.Centroid)
907 info->in[i].centroid = 1;
908 }
909 }
910 }
911 break;
912 case TGSI_FILE_OUTPUT:
913 for (i = first; i <= last; ++i, ++si) {
914 switch (sn) {
915 case TGSI_SEMANTIC_POSITION:
916 if (info->type == PIPE_SHADER_FRAGMENT)
917 info->io.fragDepth = i;
918 else
919 if (clipVertexOutput < 0)
920 clipVertexOutput = i;
921 break;
922 case TGSI_SEMANTIC_COLOR:
923 if (info->type == PIPE_SHADER_FRAGMENT)
924 info->prop.fp.numColourResults++;
925 break;
926 case TGSI_SEMANTIC_EDGEFLAG:
927 info->io.edgeFlagOut = i;
928 break;
929 case TGSI_SEMANTIC_CLIPVERTEX:
930 clipVertexOutput = i;
931 break;
932 case TGSI_SEMANTIC_CLIPDIST:
933 info->io.clipDistanceMask |=
934 decl->Declaration.UsageMask << (si * 4);
935 info->io.genUserClip = -1;
936 break;
937 default:
938 break;
939 }
940 info->out[i].id = i;
941 info->out[i].sn = sn;
942 info->out[i].si = si;
943 }
944 break;
945 case TGSI_FILE_SYSTEM_VALUE:
946 switch (sn) {
947 case TGSI_SEMANTIC_INSTANCEID:
948 info->io.instanceId = first;
949 break;
950 case TGSI_SEMANTIC_VERTEXID:
951 info->io.vertexId = first;
952 break;
953 default:
954 break;
955 }
956 for (i = first; i <= last; ++i, ++si) {
957 info->sv[i].sn = sn;
958 info->sv[i].si = si;
959 info->sv[i].input = inferSysValDirection(sn);
960 }
961 break;
962 case TGSI_FILE_RESOURCE:
963 for (i = first; i <= last; ++i) {
964 resources[i].target = decl->Resource.Resource;
965 resources[i].raw = decl->Resource.Raw;
966 resources[i].slot = i;
967 }
968 break;
969 case TGSI_FILE_SAMPLER_VIEW:
970 for (i = first; i <= last; ++i)
971 textureViews[i].target = decl->SamplerView.Resource;
972 break;
973 case TGSI_FILE_NULL:
974 case TGSI_FILE_TEMPORARY:
975 case TGSI_FILE_ADDRESS:
976 case TGSI_FILE_CONSTANT:
977 case TGSI_FILE_IMMEDIATE:
978 case TGSI_FILE_PREDICATE:
979 case TGSI_FILE_SAMPLER:
980 break;
981 default:
982 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
983 return false;
984 }
985 return true;
986 }
987
988 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
989 {
990 return insn.getOpcode() == TGSI_OPCODE_MOV &&
991 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
992 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
993 }
994
995 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
996 {
997 Instruction insn(inst);
998
999 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1000 info->numBarriers = 1;
1001
1002 if (insn.dstCount()) {
1003 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1004 Instruction::DstRegister dst = insn.getDst(0);
1005
1006 if (dst.isIndirect(0))
1007 for (unsigned i = 0; i < info->numOutputs; ++i)
1008 info->out[i].mask = 0xf;
1009 else
1010 info->out[dst.getIndex(0)].mask |= dst.getMask();
1011
1012 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE)
1013 info->out[dst.getIndex(0)].mask &= 1;
1014
1015 if (isEdgeFlagPassthrough(insn))
1016 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1017 } else
1018 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1019 if (insn.getDst(0).isIndirect(0))
1020 mainTempsInLMem = TRUE;
1021 }
1022 }
1023
1024 for (unsigned s = 0; s < insn.srcCount(); ++s) {
1025 Instruction::SrcRegister src = insn.getSrc(s);
1026 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1027 if (src.isIndirect(0))
1028 mainTempsInLMem = TRUE;
1029 } else
1030 if (src.getFile() == TGSI_FILE_RESOURCE) {
1031 if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1032 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1033 0x1 : 0x2;
1034 }
1035 if (src.getFile() != TGSI_FILE_INPUT)
1036 continue;
1037 unsigned mask = insn.srcMask(s);
1038
1039 if (src.isIndirect(0)) {
1040 for (unsigned i = 0; i < info->numInputs; ++i)
1041 info->in[i].mask = 0xf;
1042 } else {
1043 for (unsigned c = 0; c < 4; ++c) {
1044 if (!(mask & (1 << c)))
1045 continue;
1046 int k = src.getSwizzle(c);
1047 int i = src.getIndex(0);
1048 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
1049 if (k <= TGSI_SWIZZLE_W)
1050 info->in[i].mask |= 1 << k;
1051 }
1052 }
1053 }
1054 return true;
1055 }
1056
1057 nv50_ir::TexInstruction::Target
1058 Instruction::getTexture(const tgsi::Source *code, int s) const
1059 {
1060 // XXX: indirect access
1061 unsigned int r;
1062
1063 switch (getSrc(s).getFile()) {
1064 case TGSI_FILE_RESOURCE:
1065 r = getSrc(s).getIndex(0);
1066 return translateTexture(code->resources.at(r).target);
1067 case TGSI_FILE_SAMPLER_VIEW:
1068 r = getSrc(s).getIndex(0);
1069 return translateTexture(code->textureViews.at(r).target);
1070 default:
1071 return translateTexture(insn->Texture.Texture);
1072 }
1073 }
1074
1075 } // namespace tgsi
1076
1077 namespace {
1078
1079 using namespace nv50_ir;
1080
1081 class Converter : public BuildUtil
1082 {
1083 public:
1084 Converter(Program *, const tgsi::Source *);
1085 ~Converter();
1086
1087 bool run();
1088
1089 private:
1090 struct Subroutine
1091 {
1092 Subroutine(Function *f) : f(f) { }
1093 Function *f;
1094 ValueMap values;
1095 };
1096
1097 Value *getVertexBase(int s);
1098 DataArray *getArrayForFile(unsigned file, int idx);
1099 Value *fetchSrc(int s, int c);
1100 Value *acquireDst(int d, int c);
1101 void storeDst(int d, int c, Value *);
1102
1103 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1104 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1105 Value *val, Value *ptr);
1106
1107 Value *applySrcMod(Value *, int s, int c);
1108
1109 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1110 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1111 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1112
1113 bool handleInstruction(const struct tgsi_full_instruction *);
1114 void exportOutputs();
1115 inline Subroutine *getSubroutine(unsigned ip);
1116 inline Subroutine *getSubroutine(Function *);
1117 inline bool isEndOfSubroutine(uint ip);
1118
1119 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1120
1121 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1122 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1123 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1124 void handleTXF(Value *dst0[4], int R);
1125 void handleTXQ(Value *dst0[4], enum TexQuery);
1126 void handleLIT(Value *dst0[4]);
1127 void handleUserClipPlanes();
1128
1129 Symbol *getResourceBase(int r);
1130 void getResourceCoords(std::vector<Value *>&, int r, int s);
1131
1132 void handleLOAD(Value *dst0[4]);
1133 void handleSTORE();
1134 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1135
1136 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1137
1138 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1139
1140 Value *buildDot(int dim);
1141
1142 class BindArgumentsPass : public Pass {
1143 public:
1144 BindArgumentsPass(Converter &conv) : conv(conv) { }
1145
1146 private:
1147 Converter &conv;
1148 Subroutine *sub;
1149
1150 inline const Location *getValueLocation(Subroutine *, Value *);
1151
1152 template<typename T> inline void
1153 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1154 T (Function::*proto));
1155
1156 template<typename T> inline void
1157 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1158 T (Function::*proto));
1159
1160 protected:
1161 bool visit(Function *);
1162 bool visit(BasicBlock *bb) { return false; }
1163 };
1164
1165 private:
1166 const struct tgsi::Source *code;
1167 const struct nv50_ir_prog_info *info;
1168
1169 struct {
1170 std::map<unsigned, Subroutine> map;
1171 Subroutine *cur;
1172 } sub;
1173
1174 uint ip; // instruction pointer
1175
1176 tgsi::Instruction tgsi;
1177
1178 DataType dstTy;
1179 DataType srcTy;
1180
1181 DataArray tData; // TGSI_FILE_TEMPORARY
1182 DataArray aData; // TGSI_FILE_ADDRESS
1183 DataArray pData; // TGSI_FILE_PREDICATE
1184 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1185
1186 Value *zero;
1187 Value *fragCoord[4];
1188 Value *clipVtx[4];
1189
1190 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1191 uint8_t vtxBaseValid;
1192
1193 Stack condBBs; // fork BB, then else clause BB
1194 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1195 Stack loopBBs; // loop headers
1196 Stack breakBBs; // end of / after loop
1197 };
1198
1199 Symbol *
1200 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1201 {
1202 const int swz = src.getSwizzle(c);
1203
1204 return makeSym(src.getFile(),
1205 src.is2D() ? src.getIndex(1) : 0,
1206 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1207 src.getIndex(0) * 16 + swz * 4);
1208 }
1209
1210 Symbol *
1211 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1212 {
1213 return makeSym(dst.getFile(),
1214 dst.is2D() ? dst.getIndex(1) : 0,
1215 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1216 dst.getIndex(0) * 16 + c * 4);
1217 }
1218
1219 Symbol *
1220 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1221 {
1222 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1223
1224 sym->reg.fileIndex = fileIdx;
1225
1226 if (idx >= 0) {
1227 if (sym->reg.file == FILE_SHADER_INPUT)
1228 sym->setOffset(info->in[idx].slot[c] * 4);
1229 else
1230 if (sym->reg.file == FILE_SHADER_OUTPUT)
1231 sym->setOffset(info->out[idx].slot[c] * 4);
1232 else
1233 if (sym->reg.file == FILE_SYSTEM_VALUE)
1234 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1235 else
1236 sym->setOffset(address);
1237 } else {
1238 sym->setOffset(address);
1239 }
1240 return sym;
1241 }
1242
1243 static inline uint8_t
1244 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1245 {
1246 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1247
1248 if (var->flat)
1249 mode = NV50_IR_INTERP_FLAT;
1250 else
1251 if (var->linear)
1252 mode = NV50_IR_INTERP_LINEAR;
1253 else
1254 if (var->sc)
1255 mode = NV50_IR_INTERP_SC;
1256
1257 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1258 ? OP_PINTERP : OP_LINTERP;
1259
1260 if (var->centroid)
1261 mode |= NV50_IR_INTERP_CENTROID;
1262
1263 return mode;
1264 }
1265
1266 Value *
1267 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1268 {
1269 operation op;
1270
1271 // XXX: no way to know interpolation mode if we don't know what's accessed
1272 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1273 src.getIndex(0)], op);
1274
1275 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1276
1277 insn->setDef(0, getScratch());
1278 insn->setSrc(0, srcToSym(src, c));
1279 if (op == OP_PINTERP)
1280 insn->setSrc(1, fragCoord[3]);
1281 if (ptr)
1282 insn->setIndirect(0, 0, ptr);
1283
1284 insn->setInterpolate(mode);
1285
1286 bb->insertTail(insn);
1287 return insn->getDef(0);
1288 }
1289
1290 Value *
1291 Converter::applySrcMod(Value *val, int s, int c)
1292 {
1293 Modifier m = tgsi.getSrc(s).getMod(c);
1294 DataType ty = tgsi.inferSrcType();
1295
1296 if (m & Modifier(NV50_IR_MOD_ABS))
1297 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1298
1299 if (m & Modifier(NV50_IR_MOD_NEG))
1300 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1301
1302 return val;
1303 }
1304
1305 Value *
1306 Converter::getVertexBase(int s)
1307 {
1308 assert(s < 5);
1309 if (!(vtxBaseValid & (1 << s))) {
1310 const int index = tgsi.getSrc(s).getIndex(1);
1311 Value *rel = NULL;
1312 if (tgsi.getSrc(s).isIndirect(1))
1313 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1314 vtxBaseValid |= 1 << s;
1315 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1316 }
1317 return vtxBase[s];
1318 }
1319
1320 Value *
1321 Converter::fetchSrc(int s, int c)
1322 {
1323 Value *res;
1324 Value *ptr = NULL, *dimRel = NULL;
1325
1326 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1327
1328 if (src.isIndirect(0))
1329 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1330
1331 if (src.is2D()) {
1332 switch (src.getFile()) {
1333 case TGSI_FILE_INPUT:
1334 dimRel = getVertexBase(s);
1335 break;
1336 case TGSI_FILE_CONSTANT:
1337 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1338 if (src.isIndirect(1))
1339 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1340 break;
1341 default:
1342 break;
1343 }
1344 }
1345
1346 res = fetchSrc(src, c, ptr);
1347
1348 if (dimRel)
1349 res->getInsn()->setIndirect(0, 1, dimRel);
1350
1351 return applySrcMod(res, s, c);
1352 }
1353
1354 Converter::DataArray *
1355 Converter::getArrayForFile(unsigned file, int idx)
1356 {
1357 switch (file) {
1358 case TGSI_FILE_TEMPORARY:
1359 return &tData;
1360 case TGSI_FILE_PREDICATE:
1361 return &pData;
1362 case TGSI_FILE_ADDRESS:
1363 return &aData;
1364 case TGSI_FILE_OUTPUT:
1365 assert(prog->getType() == Program::TYPE_FRAGMENT);
1366 return &oData;
1367 default:
1368 assert(!"invalid/unhandled TGSI source file");
1369 return NULL;
1370 }
1371 }
1372
1373 Value *
1374 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1375 {
1376 const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1377 const int idx = src.getIndex(0);
1378 const int swz = src.getSwizzle(c);
1379
1380 switch (src.getFile()) {
1381 case TGSI_FILE_IMMEDIATE:
1382 assert(!ptr);
1383 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1384 case TGSI_FILE_CONSTANT:
1385 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1386 case TGSI_FILE_INPUT:
1387 if (prog->getType() == Program::TYPE_FRAGMENT) {
1388 // don't load masked inputs, won't be assigned a slot
1389 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1390 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1391 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1392 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1393 return interpolate(src, c, ptr);
1394 }
1395 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1396 case TGSI_FILE_OUTPUT:
1397 assert(!"load from output file");
1398 return NULL;
1399 case TGSI_FILE_SYSTEM_VALUE:
1400 assert(!ptr);
1401 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1402 default:
1403 return getArrayForFile(src.getFile(), idx2d)->load(
1404 sub.cur->values, idx, swz, ptr);
1405 }
1406 }
1407
1408 Value *
1409 Converter::acquireDst(int d, int c)
1410 {
1411 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1412 const unsigned f = dst.getFile();
1413 const int idx = dst.getIndex(0);
1414 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1415
1416 if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1417 return NULL;
1418
1419 if (dst.isIndirect(0) ||
1420 f == TGSI_FILE_SYSTEM_VALUE ||
1421 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1422 return getScratch();
1423
1424 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1425 }
1426
1427 void
1428 Converter::storeDst(int d, int c, Value *val)
1429 {
1430 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1431
1432 switch (tgsi.getSaturate()) {
1433 case TGSI_SAT_NONE:
1434 break;
1435 case TGSI_SAT_ZERO_ONE:
1436 mkOp1(OP_SAT, dstTy, val, val);
1437 break;
1438 case TGSI_SAT_MINUS_PLUS_ONE:
1439 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1440 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1441 break;
1442 default:
1443 assert(!"invalid saturation mode");
1444 break;
1445 }
1446
1447 Value *ptr = dst.isIndirect(0) ?
1448 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1449
1450 if (info->io.genUserClip > 0 &&
1451 dst.getFile() == TGSI_FILE_OUTPUT &&
1452 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1453 mkMov(clipVtx[c], val);
1454 val = clipVtx[c];
1455 }
1456
1457 storeDst(dst, c, val, ptr);
1458 }
1459
1460 void
1461 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1462 Value *val, Value *ptr)
1463 {
1464 const unsigned f = dst.getFile();
1465 const int idx = dst.getIndex(0);
1466 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1467
1468 if (f == TGSI_FILE_SYSTEM_VALUE) {
1469 assert(!ptr);
1470 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1471 } else
1472 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1473 if (ptr || (info->out[idx].mask & (1 << c)))
1474 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1475 } else
1476 if (f == TGSI_FILE_TEMPORARY ||
1477 f == TGSI_FILE_PREDICATE ||
1478 f == TGSI_FILE_ADDRESS ||
1479 f == TGSI_FILE_OUTPUT) {
1480 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1481 } else {
1482 assert(!"invalid dst file");
1483 }
1484 }
1485
1486 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1487 for (chan = 0; chan < 4; ++chan) \
1488 if (!inst.getDst(d).isMasked(chan))
1489
1490 Value *
1491 Converter::buildDot(int dim)
1492 {
1493 assert(dim > 0);
1494
1495 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1496 Value *dotp = getScratch();
1497
1498 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1499
1500 for (int c = 1; c < dim; ++c) {
1501 src0 = fetchSrc(0, c);
1502 src1 = fetchSrc(1, c);
1503 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1504 }
1505 return dotp;
1506 }
1507
1508 void
1509 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1510 {
1511 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1512 join->fixed = 1;
1513 conv->insertHead(join);
1514
1515 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1516 fork->insertBefore(fork->getExit(), fork->joinAt);
1517 }
1518
1519 void
1520 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1521 {
1522 unsigned rIdx = 0, sIdx = 0;
1523
1524 if (R >= 0)
1525 rIdx = tgsi.getSrc(R).getIndex(0);
1526 if (S >= 0)
1527 sIdx = tgsi.getSrc(S).getIndex(0);
1528
1529 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1530
1531 if (tgsi.getSrc(R).isIndirect(0)) {
1532 tex->tex.rIndirectSrc = s;
1533 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1534 }
1535 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1536 tex->tex.sIndirectSrc = s;
1537 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1538 }
1539 }
1540
1541 void
1542 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1543 {
1544 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1545 tex->tex.query = query;
1546 unsigned int c, d;
1547
1548 for (d = 0, c = 0; c < 4; ++c) {
1549 if (!dst0[c])
1550 continue;
1551 tex->tex.mask |= 1 << c;
1552 tex->setDef(d++, dst0[c]);
1553 }
1554 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1555
1556 setTexRS(tex, c, 1, -1);
1557
1558 bb->insertTail(tex);
1559 }
1560
1561 void
1562 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1563 {
1564 Value *proj = fetchSrc(0, 3);
1565 Instruction *insn = proj->getUniqueInsn();
1566 int c;
1567
1568 if (insn->op == OP_PINTERP) {
1569 bb->insertTail(insn = cloneForward(func, insn));
1570 insn->op = OP_LINTERP;
1571 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1572 insn->setSrc(1, NULL);
1573 proj = insn->getDef(0);
1574 }
1575 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1576
1577 for (c = 0; c < 4; ++c) {
1578 if (!(mask & (1 << c)))
1579 continue;
1580 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1581 continue;
1582 mask &= ~(1 << c);
1583
1584 bb->insertTail(insn = cloneForward(func, insn));
1585 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1586 insn->setSrc(1, proj);
1587 dst[c] = insn->getDef(0);
1588 }
1589 if (!mask)
1590 return;
1591
1592 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1593
1594 for (c = 0; c < 4; ++c)
1595 if (mask & (1 << c))
1596 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1597 }
1598
1599 // order of nv50 ir sources: x y z layer lod/bias shadow
1600 // order of TGSI TEX sources: x y z layer shadow lod/bias
1601 // lowering will finally set the hw specific order (like array first on nvc0)
1602 void
1603 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1604 {
1605 Value *val;
1606 Value *arg[4], *src[8];
1607 Value *lod = NULL, *shd = NULL;
1608 unsigned int s, c, d;
1609 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1610
1611 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1612
1613 for (s = 0; s < tgt.getArgCount(); ++s)
1614 arg[s] = src[s] = fetchSrc(0, s);
1615
1616 if (texi->op == OP_TXL || texi->op == OP_TXB)
1617 lod = fetchSrc(L >> 4, L & 3);
1618
1619 if (C == 0x0f)
1620 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1621
1622 if (tgt.isShadow())
1623 shd = fetchSrc(C >> 4, C & 3);
1624
1625 if (texi->op == OP_TXD) {
1626 for (c = 0; c < tgt.getDim(); ++c) {
1627 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1628 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1629 }
1630 }
1631
1632 // cube textures don't care about projection value, it's divided out
1633 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1634 unsigned int n = tgt.getDim();
1635 if (shd) {
1636 arg[n] = shd;
1637 ++n;
1638 assert(tgt.getDim() == tgt.getArgCount());
1639 }
1640 loadProjTexCoords(src, arg, (1 << n) - 1);
1641 if (shd)
1642 shd = src[n - 1];
1643 }
1644
1645 if (tgt.isCube()) {
1646 for (c = 0; c < 3; ++c)
1647 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1648 val = getScratch();
1649 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1650 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1651 mkOp1(OP_RCP, TYPE_F32, val, val);
1652 for (c = 0; c < 3; ++c)
1653 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1654 }
1655
1656 for (c = 0, d = 0; c < 4; ++c) {
1657 if (dst[c]) {
1658 texi->setDef(d++, dst[c]);
1659 texi->tex.mask |= 1 << c;
1660 } else {
1661 // NOTE: maybe hook up def too, for CSE
1662 }
1663 }
1664 for (s = 0; s < tgt.getArgCount(); ++s)
1665 texi->setSrc(s, src[s]);
1666 if (lod)
1667 texi->setSrc(s++, lod);
1668 if (shd)
1669 texi->setSrc(s++, shd);
1670
1671 setTexRS(texi, s, R, S);
1672
1673 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1674 texi->tex.levelZero = true;
1675
1676 bb->insertTail(texi);
1677 }
1678
1679 // 1st source: xyz = coordinates, w = lod
1680 // 2nd source: offset
1681 void
1682 Converter::handleTXF(Value *dst[4], int R)
1683 {
1684 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1685 unsigned int c, d, s;
1686
1687 texi->tex.target = tgsi.getTexture(code, R);
1688
1689 for (c = 0, d = 0; c < 4; ++c) {
1690 if (dst[c]) {
1691 texi->setDef(d++, dst[c]);
1692 texi->tex.mask |= 1 << c;
1693 }
1694 }
1695 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1696 texi->setSrc(c, fetchSrc(0, c));
1697 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1698
1699 setTexRS(texi, c, R, -1);
1700
1701 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1702 for (c = 0; c < 3; ++c) {
1703 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1704 if (texi->tex.offset[s][c])
1705 texi->tex.useOffsets = s + 1;
1706 }
1707 }
1708
1709 bb->insertTail(texi);
1710 }
1711
1712 void
1713 Converter::handleLIT(Value *dst0[4])
1714 {
1715 Value *val0 = NULL;
1716 unsigned int mask = tgsi.getDst(0).getMask();
1717
1718 if (mask & (1 << 0))
1719 loadImm(dst0[0], 1.0f);
1720
1721 if (mask & (1 << 3))
1722 loadImm(dst0[3], 1.0f);
1723
1724 if (mask & (3 << 1)) {
1725 val0 = getScratch();
1726 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1727 if (mask & (1 << 1))
1728 mkMov(dst0[1], val0);
1729 }
1730
1731 if (mask & (1 << 2)) {
1732 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1733 Value *val1 = getScratch(), *val3 = getScratch();
1734
1735 Value *pos128 = loadImm(NULL, +127.999999f);
1736 Value *neg128 = loadImm(NULL, -127.999999f);
1737
1738 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1739 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1740 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1741 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1742
1743 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1744 }
1745 }
1746
1747 static inline bool
1748 isResourceSpecial(const int r)
1749 {
1750 return (r == TGSI_RESOURCE_GLOBAL ||
1751 r == TGSI_RESOURCE_LOCAL ||
1752 r == TGSI_RESOURCE_PRIVATE ||
1753 r == TGSI_RESOURCE_INPUT);
1754 }
1755
1756 static inline bool
1757 isResourceRaw(const struct tgsi::Source *code, const int r)
1758 {
1759 return isResourceSpecial(r) || code->resources[r].raw;
1760 }
1761
1762 static inline nv50_ir::TexTarget
1763 getResourceTarget(const struct tgsi::Source *code, int r)
1764 {
1765 if (isResourceSpecial(r))
1766 return nv50_ir::TEX_TARGET_BUFFER;
1767 return tgsi::translateTexture(code->resources.at(r).target);
1768 }
1769
1770 Symbol *
1771 Converter::getResourceBase(const int r)
1772 {
1773 Symbol *sym = NULL;
1774
1775 switch (r) {
1776 case TGSI_RESOURCE_GLOBAL:
1777 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1778 break;
1779 case TGSI_RESOURCE_LOCAL:
1780 assert(prog->getType() == Program::TYPE_COMPUTE);
1781 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1782 info->prop.cp.sharedOffset);
1783 break;
1784 case TGSI_RESOURCE_PRIVATE:
1785 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1786 info->bin.tlsSpace);
1787 break;
1788 case TGSI_RESOURCE_INPUT:
1789 assert(prog->getType() == Program::TYPE_COMPUTE);
1790 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1791 info->prop.cp.inputOffset);
1792 break;
1793 default:
1794 sym = new_Symbol(prog,
1795 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1796 break;
1797 }
1798 return sym;
1799 }
1800
1801 void
1802 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
1803 {
1804 const int arg =
1805 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
1806
1807 for (int c = 0; c < arg; ++c)
1808 coords.push_back(fetchSrc(s, c));
1809
1810 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
1811 if (r == TGSI_RESOURCE_LOCAL ||
1812 r == TGSI_RESOURCE_PRIVATE ||
1813 r == TGSI_RESOURCE_INPUT)
1814 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
1815 coords[0]);
1816 }
1817
1818 static inline int
1819 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
1820 {
1821 int n = 0;
1822
1823 while (mask) {
1824 if (mask & 1) {
1825 size[n]++;
1826 } else {
1827 if (size[n])
1828 comp[n = 1] = size[0] + 1;
1829 else
1830 comp[n]++;
1831 }
1832 mask >>= 1;
1833 }
1834 if (size[0] == 3) {
1835 n = 1;
1836 size[0] = (comp[0] == 1) ? 1 : 2;
1837 size[1] = 3 - size[0];
1838 comp[1] = comp[0] + size[0];
1839 }
1840 return n + 1;
1841 }
1842
1843 // For raw loads, granularity is 4 byte.
1844 // Usage of the texture read mask on OP_SULDP is not allowed.
1845 void
1846 Converter::handleLOAD(Value *dst0[4])
1847 {
1848 const int r = tgsi.getSrc(0).getIndex(0);
1849 int c;
1850 std::vector<Value *> off, src, ldv, def;
1851
1852 getResourceCoords(off, r, 1);
1853
1854 if (isResourceRaw(code, r)) {
1855 uint8_t mask = 0;
1856 uint8_t comp[2] = { 0, 0 };
1857 uint8_t size[2] = { 0, 0 };
1858
1859 Symbol *base = getResourceBase(r);
1860
1861 // determine the base and size of the at most 2 load ops
1862 for (c = 0; c < 4; ++c)
1863 if (!tgsi.getDst(0).isMasked(c))
1864 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
1865
1866 int n = partitionLoadStore(comp, size, mask);
1867
1868 src = off;
1869
1870 def.resize(4); // index by component, the ones we need will be non-NULL
1871 for (c = 0; c < 4; ++c) {
1872 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
1873 def[c] = dst0[c];
1874 else
1875 if (mask & (1 << c))
1876 def[c] = getScratch();
1877 }
1878
1879 const bool useLd = isResourceSpecial(r) ||
1880 (info->io.nv50styleSurfaces &&
1881 code->resources[r].target == TGSI_TEXTURE_BUFFER);
1882
1883 for (int i = 0; i < n; ++i) {
1884 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
1885
1886 if (comp[i]) // adjust x component of source address if necessary
1887 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
1888 off[0], mkImm(comp[i] * 4));
1889 else
1890 src[0] = off[0];
1891
1892 if (useLd) {
1893 Instruction *ld =
1894 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
1895 for (size_t c = 1; c < ldv.size(); ++c)
1896 ld->setDef(c, ldv[c]);
1897 } else {
1898 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
1899 0, ldv, src)->dType = typeOfSize(size[i] * 4);
1900 }
1901 }
1902 } else {
1903 def.resize(4);
1904 for (c = 0; c < 4; ++c) {
1905 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
1906 def[c] = getScratch();
1907 else
1908 def[c] = dst0[c];
1909 }
1910
1911 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
1912 def, off);
1913 }
1914 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1915 if (dst0[c] != def[c])
1916 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
1917 }
1918
1919 // For formatted stores, the write mask on OP_SUSTP can be used.
1920 // Raw stores have to be split.
1921 void
1922 Converter::handleSTORE()
1923 {
1924 const int r = tgsi.getDst(0).getIndex(0);
1925 int c;
1926 std::vector<Value *> off, src, dummy;
1927
1928 getResourceCoords(off, r, 0);
1929 src = off;
1930 const int s = src.size();
1931
1932 if (isResourceRaw(code, r)) {
1933 uint8_t comp[2] = { 0, 0 };
1934 uint8_t size[2] = { 0, 0 };
1935
1936 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
1937
1938 Symbol *base = getResourceBase(r);
1939
1940 const bool useSt = isResourceSpecial(r) ||
1941 (info->io.nv50styleSurfaces &&
1942 code->resources[r].target == TGSI_TEXTURE_BUFFER);
1943
1944 for (int i = 0; i < n; ++i) {
1945 if (comp[i]) // adjust x component of source address if necessary
1946 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
1947 off[0], mkImm(comp[i] * 4));
1948 else
1949 src[0] = off[0];
1950
1951 const DataType stTy = typeOfSize(size[i] * 4);
1952
1953 if (useSt) {
1954 Instruction *st =
1955 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
1956 for (c = 1; c < size[i]; ++c)
1957 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
1958 st->setIndirect(0, 0, src[0]);
1959 } else {
1960 // attach values to be stored
1961 src.resize(s + size[i]);
1962 for (c = 0; c < size[i]; ++c)
1963 src[s + c] = fetchSrc(1, comp[i] + c);
1964 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
1965 0, dummy, src)->setType(stTy);
1966 }
1967 }
1968 } else {
1969 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1970 src.push_back(fetchSrc(1, c));
1971
1972 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
1973 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
1974 }
1975 }
1976
1977 // XXX: These only work on resources with the single-component u32/s32 formats.
1978 // Therefore the result is replicated. This might not be intended by TGSI, but
1979 // operating on more than 1 component would produce undefined results because
1980 // they do not exist.
1981 void
1982 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
1983 {
1984 const int r = tgsi.getSrc(0).getIndex(0);
1985 std::vector<Value *> srcv;
1986 std::vector<Value *> defv;
1987 LValue *dst = getScratch();
1988
1989 getResourceCoords(srcv, r, 1);
1990
1991 if (isResourceSpecial(r)) {
1992 assert(r != TGSI_RESOURCE_INPUT);
1993 Instruction *insn;
1994 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
1995 insn->subOp = subOp;
1996 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
1997 insn->setSrc(2, fetchSrc(3, 0));
1998 insn->setIndirect(0, 0, srcv.at(0));
1999 } else {
2000 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2001 TexTarget targ = getResourceTarget(code, r);
2002 int idx = code->resources[r].slot;
2003 defv.push_back(dst);
2004 srcv.push_back(fetchSrc(2, 0));
2005 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2006 srcv.push_back(fetchSrc(3, 0));
2007 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2008 tex->subOp = subOp;
2009 tex->tex.mask = 1;
2010 tex->setType(ty);
2011 }
2012
2013 for (int c = 0; c < 4; ++c)
2014 if (dst0[c])
2015 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2016 }
2017
2018 Converter::Subroutine *
2019 Converter::getSubroutine(unsigned ip)
2020 {
2021 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2022
2023 if (it == sub.map.end())
2024 it = sub.map.insert(std::make_pair(
2025 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2026
2027 return &it->second;
2028 }
2029
2030 Converter::Subroutine *
2031 Converter::getSubroutine(Function *f)
2032 {
2033 unsigned ip = f->getLabel();
2034 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2035
2036 if (it == sub.map.end())
2037 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2038
2039 return &it->second;
2040 }
2041
2042 bool
2043 Converter::isEndOfSubroutine(uint ip)
2044 {
2045 assert(ip < code->scan.num_instructions);
2046 tgsi::Instruction insn(&code->insns[ip]);
2047 return (insn.getOpcode() == TGSI_OPCODE_END ||
2048 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2049 // does END occur at end of main or the very end ?
2050 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2051 }
2052
2053 bool
2054 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2055 {
2056 Instruction *geni;
2057
2058 Value *dst0[4], *rDst0[4];
2059 Value *src0, *src1, *src2;
2060 Value *val0, *val1;
2061 int c;
2062
2063 tgsi = tgsi::Instruction(insn);
2064
2065 bool useScratchDst = tgsi.checkDstSrcAliasing();
2066
2067 operation op = tgsi.getOP();
2068 dstTy = tgsi.inferDstType();
2069 srcTy = tgsi.inferSrcType();
2070
2071 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2072
2073 if (tgsi.dstCount()) {
2074 for (c = 0; c < 4; ++c) {
2075 rDst0[c] = acquireDst(0, c);
2076 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2077 }
2078 }
2079
2080 switch (tgsi.getOpcode()) {
2081 case TGSI_OPCODE_ADD:
2082 case TGSI_OPCODE_UADD:
2083 case TGSI_OPCODE_AND:
2084 case TGSI_OPCODE_DIV:
2085 case TGSI_OPCODE_IDIV:
2086 case TGSI_OPCODE_UDIV:
2087 case TGSI_OPCODE_MAX:
2088 case TGSI_OPCODE_MIN:
2089 case TGSI_OPCODE_IMAX:
2090 case TGSI_OPCODE_IMIN:
2091 case TGSI_OPCODE_UMAX:
2092 case TGSI_OPCODE_UMIN:
2093 case TGSI_OPCODE_MOD:
2094 case TGSI_OPCODE_UMOD:
2095 case TGSI_OPCODE_MUL:
2096 case TGSI_OPCODE_UMUL:
2097 case TGSI_OPCODE_OR:
2098 case TGSI_OPCODE_POW:
2099 case TGSI_OPCODE_SHL:
2100 case TGSI_OPCODE_ISHR:
2101 case TGSI_OPCODE_USHR:
2102 case TGSI_OPCODE_SUB:
2103 case TGSI_OPCODE_XOR:
2104 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2105 src0 = fetchSrc(0, c);
2106 src1 = fetchSrc(1, c);
2107 mkOp2(op, dstTy, dst0[c], src0, src1);
2108 }
2109 break;
2110 case TGSI_OPCODE_MAD:
2111 case TGSI_OPCODE_UMAD:
2112 case TGSI_OPCODE_SAD:
2113 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2114 src0 = fetchSrc(0, c);
2115 src1 = fetchSrc(1, c);
2116 src2 = fetchSrc(2, c);
2117 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2118 }
2119 break;
2120 case TGSI_OPCODE_MOV:
2121 case TGSI_OPCODE_ABS:
2122 case TGSI_OPCODE_CEIL:
2123 case TGSI_OPCODE_FLR:
2124 case TGSI_OPCODE_TRUNC:
2125 case TGSI_OPCODE_RCP:
2126 case TGSI_OPCODE_IABS:
2127 case TGSI_OPCODE_INEG:
2128 case TGSI_OPCODE_NOT:
2129 case TGSI_OPCODE_DDX:
2130 case TGSI_OPCODE_DDY:
2131 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2132 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2133 break;
2134 case TGSI_OPCODE_RSQ:
2135 src0 = fetchSrc(0, 0);
2136 val0 = getScratch();
2137 mkOp1(OP_ABS, TYPE_F32, val0, src0);
2138 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2139 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2140 mkMov(dst0[c], val0);
2141 break;
2142 case TGSI_OPCODE_ARL:
2143 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2144 src0 = fetchSrc(0, c);
2145 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
2146 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
2147 }
2148 break;
2149 case TGSI_OPCODE_UARL:
2150 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2151 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
2152 break;
2153 case TGSI_OPCODE_EX2:
2154 case TGSI_OPCODE_LG2:
2155 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2156 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2157 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2158 break;
2159 case TGSI_OPCODE_COS:
2160 case TGSI_OPCODE_SIN:
2161 val0 = getScratch();
2162 if (mask & 7) {
2163 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2164 mkOp1(op, TYPE_F32, val0, val0);
2165 for (c = 0; c < 3; ++c)
2166 if (dst0[c])
2167 mkMov(dst0[c], val0);
2168 }
2169 if (dst0[3]) {
2170 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2171 mkOp1(op, TYPE_F32, dst0[3], val0);
2172 }
2173 break;
2174 case TGSI_OPCODE_SCS:
2175 if (mask & 3) {
2176 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2177 if (dst0[0])
2178 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2179 if (dst0[1])
2180 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2181 }
2182 if (dst0[2])
2183 loadImm(dst0[2], 0.0f);
2184 if (dst0[3])
2185 loadImm(dst0[3], 1.0f);
2186 break;
2187 case TGSI_OPCODE_EXP:
2188 src0 = fetchSrc(0, 0);
2189 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2190 if (dst0[1])
2191 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2192 if (dst0[0])
2193 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2194 if (dst0[2])
2195 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2196 if (dst0[3])
2197 loadImm(dst0[3], 1.0f);
2198 break;
2199 case TGSI_OPCODE_LOG:
2200 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2201 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2202 if (dst0[0] || dst0[1])
2203 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2204 if (dst0[1]) {
2205 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2206 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2207 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2208 }
2209 if (dst0[3])
2210 loadImm(dst0[3], 1.0f);
2211 break;
2212 case TGSI_OPCODE_DP2:
2213 val0 = buildDot(2);
2214 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2215 mkMov(dst0[c], val0);
2216 break;
2217 case TGSI_OPCODE_DP3:
2218 val0 = buildDot(3);
2219 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2220 mkMov(dst0[c], val0);
2221 break;
2222 case TGSI_OPCODE_DP4:
2223 val0 = buildDot(4);
2224 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2225 mkMov(dst0[c], val0);
2226 break;
2227 case TGSI_OPCODE_DPH:
2228 val0 = buildDot(3);
2229 src1 = fetchSrc(1, 3);
2230 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2231 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2232 mkMov(dst0[c], val0);
2233 break;
2234 case TGSI_OPCODE_DST:
2235 if (dst0[0])
2236 loadImm(dst0[0], 1.0f);
2237 if (dst0[1]) {
2238 src0 = fetchSrc(0, 1);
2239 src1 = fetchSrc(1, 1);
2240 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2241 }
2242 if (dst0[2])
2243 mkMov(dst0[2], fetchSrc(0, 2));
2244 if (dst0[3])
2245 mkMov(dst0[3], fetchSrc(1, 3));
2246 break;
2247 case TGSI_OPCODE_LRP:
2248 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2249 src0 = fetchSrc(0, c);
2250 src1 = fetchSrc(1, c);
2251 src2 = fetchSrc(2, c);
2252 mkOp3(OP_MAD, TYPE_F32, dst0[c],
2253 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2254 }
2255 break;
2256 case TGSI_OPCODE_LIT:
2257 handleLIT(dst0);
2258 break;
2259 case TGSI_OPCODE_XPD:
2260 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2261 if (c < 3) {
2262 val0 = getSSA();
2263 src0 = fetchSrc(1, (c + 1) % 3);
2264 src1 = fetchSrc(0, (c + 2) % 3);
2265 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2266 mkOp1(OP_NEG, TYPE_F32, val0, val0);
2267
2268 src0 = fetchSrc(0, (c + 1) % 3);
2269 src1 = fetchSrc(1, (c + 2) % 3);
2270 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2271 } else {
2272 loadImm(dst0[c], 1.0f);
2273 }
2274 }
2275 break;
2276 case TGSI_OPCODE_ISSG:
2277 case TGSI_OPCODE_SSG:
2278 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2279 src0 = fetchSrc(0, c);
2280 val0 = getScratch();
2281 val1 = getScratch();
2282 mkCmp(OP_SET, CC_GT, srcTy, val0, src0, zero);
2283 mkCmp(OP_SET, CC_LT, srcTy, val1, src0, zero);
2284 if (srcTy == TYPE_F32)
2285 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2286 else
2287 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2288 }
2289 break;
2290 case TGSI_OPCODE_UCMP:
2291 case TGSI_OPCODE_CMP:
2292 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2293 src0 = fetchSrc(0, c);
2294 src1 = fetchSrc(1, c);
2295 src2 = fetchSrc(2, c);
2296 if (src1 == src2)
2297 mkMov(dst0[c], src1);
2298 else
2299 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2300 srcTy, dst0[c], src1, src2, src0);
2301 }
2302 break;
2303 case TGSI_OPCODE_FRC:
2304 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2305 src0 = fetchSrc(0, c);
2306 val0 = getScratch();
2307 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2308 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2309 }
2310 break;
2311 case TGSI_OPCODE_ROUND:
2312 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2313 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2314 ->rnd = ROUND_NI;
2315 break;
2316 case TGSI_OPCODE_CLAMP:
2317 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2318 src0 = fetchSrc(0, c);
2319 src1 = fetchSrc(1, c);
2320 src2 = fetchSrc(2, c);
2321 val0 = getScratch();
2322 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2323 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2324 }
2325 break;
2326 case TGSI_OPCODE_SLT:
2327 case TGSI_OPCODE_SGE:
2328 case TGSI_OPCODE_SEQ:
2329 case TGSI_OPCODE_SFL:
2330 case TGSI_OPCODE_SGT:
2331 case TGSI_OPCODE_SLE:
2332 case TGSI_OPCODE_SNE:
2333 case TGSI_OPCODE_STR:
2334 case TGSI_OPCODE_ISGE:
2335 case TGSI_OPCODE_ISLT:
2336 case TGSI_OPCODE_USEQ:
2337 case TGSI_OPCODE_USGE:
2338 case TGSI_OPCODE_USLT:
2339 case TGSI_OPCODE_USNE:
2340 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2341 src0 = fetchSrc(0, c);
2342 src1 = fetchSrc(1, c);
2343 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
2344 }
2345 break;
2346 case TGSI_OPCODE_KIL:
2347 val0 = new_LValue(func, FILE_PREDICATE);
2348 for (c = 0; c < 4; ++c) {
2349 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
2350 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2351 }
2352 break;
2353 case TGSI_OPCODE_KILP:
2354 mkOp(OP_DISCARD, TYPE_NONE, NULL);
2355 break;
2356 case TGSI_OPCODE_TEX:
2357 case TGSI_OPCODE_TXB:
2358 case TGSI_OPCODE_TXL:
2359 case TGSI_OPCODE_TXP:
2360 // R S L C Dx Dy
2361 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2362 break;
2363 case TGSI_OPCODE_TXD:
2364 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2365 break;
2366 case TGSI_OPCODE_TEX2:
2367 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2368 break;
2369 case TGSI_OPCODE_TXB2:
2370 case TGSI_OPCODE_TXL2:
2371 handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
2372 break;
2373 case TGSI_OPCODE_SAMPLE:
2374 case TGSI_OPCODE_SAMPLE_B:
2375 case TGSI_OPCODE_SAMPLE_D:
2376 case TGSI_OPCODE_SAMPLE_L:
2377 case TGSI_OPCODE_SAMPLE_C:
2378 case TGSI_OPCODE_SAMPLE_C_LZ:
2379 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2380 break;
2381 case TGSI_OPCODE_TXF:
2382 handleTXF(dst0, 1);
2383 break;
2384 case TGSI_OPCODE_TXQ:
2385 case TGSI_OPCODE_SVIEWINFO:
2386 handleTXQ(dst0, TXQ_DIMS);
2387 break;
2388 case TGSI_OPCODE_F2I:
2389 case TGSI_OPCODE_F2U:
2390 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2391 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2392 break;
2393 case TGSI_OPCODE_I2F:
2394 case TGSI_OPCODE_U2F:
2395 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2396 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2397 break;
2398 case TGSI_OPCODE_EMIT:
2399 case TGSI_OPCODE_ENDPRIM:
2400 // get vertex stream if specified (must be immediate)
2401 src0 = tgsi.srcCount() ?
2402 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2403 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2404 break;
2405 case TGSI_OPCODE_IF:
2406 {
2407 BasicBlock *ifBB = new BasicBlock(func);
2408
2409 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2410 condBBs.push(bb);
2411 joinBBs.push(bb);
2412
2413 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2414
2415 setPosition(ifBB, true);
2416 }
2417 break;
2418 case TGSI_OPCODE_ELSE:
2419 {
2420 BasicBlock *elseBB = new BasicBlock(func);
2421 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2422
2423 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2424 condBBs.push(bb);
2425
2426 forkBB->getExit()->asFlow()->target.bb = elseBB;
2427 if (!bb->isTerminated())
2428 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2429
2430 setPosition(elseBB, true);
2431 }
2432 break;
2433 case TGSI_OPCODE_ENDIF:
2434 {
2435 BasicBlock *convBB = new BasicBlock(func);
2436 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2437 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2438
2439 if (!bb->isTerminated()) {
2440 // we only want join if none of the clauses ended with CONT/BREAK/RET
2441 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2442 insertConvergenceOps(convBB, forkBB);
2443 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2444 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2445 }
2446
2447 if (prevBB->getExit()->op == OP_BRA) {
2448 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2449 prevBB->getExit()->asFlow()->target.bb = convBB;
2450 }
2451 setPosition(convBB, true);
2452 }
2453 break;
2454 case TGSI_OPCODE_BGNLOOP:
2455 {
2456 BasicBlock *lbgnBB = new BasicBlock(func);
2457 BasicBlock *lbrkBB = new BasicBlock(func);
2458
2459 loopBBs.push(lbgnBB);
2460 breakBBs.push(lbrkBB);
2461 if (loopBBs.getSize() > func->loopNestingBound)
2462 func->loopNestingBound++;
2463
2464 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2465
2466 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2467 setPosition(lbgnBB, true);
2468 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2469 }
2470 break;
2471 case TGSI_OPCODE_ENDLOOP:
2472 {
2473 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2474
2475 if (!bb->isTerminated()) {
2476 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2477 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2478 }
2479 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2480 }
2481 break;
2482 case TGSI_OPCODE_BRK:
2483 {
2484 if (bb->isTerminated())
2485 break;
2486 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2487 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2488 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2489 }
2490 break;
2491 case TGSI_OPCODE_CONT:
2492 {
2493 if (bb->isTerminated())
2494 break;
2495 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2496 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2497 contBB->explicitCont = true;
2498 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2499 }
2500 break;
2501 case TGSI_OPCODE_BGNSUB:
2502 {
2503 Subroutine *s = getSubroutine(ip);
2504 BasicBlock *entry = new BasicBlock(s->f);
2505 BasicBlock *leave = new BasicBlock(s->f);
2506
2507 // multiple entrypoints possible, keep the graph connected
2508 if (prog->getType() == Program::TYPE_COMPUTE)
2509 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2510
2511 sub.cur = s;
2512 s->f->setEntry(entry);
2513 s->f->setExit(leave);
2514 setPosition(entry, true);
2515 return true;
2516 }
2517 case TGSI_OPCODE_ENDSUB:
2518 {
2519 sub.cur = getSubroutine(prog->main);
2520 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2521 return true;
2522 }
2523 case TGSI_OPCODE_CAL:
2524 {
2525 Subroutine *s = getSubroutine(tgsi.getLabel());
2526 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2527 func->call.attach(&s->f->call, Graph::Edge::TREE);
2528 return true;
2529 }
2530 case TGSI_OPCODE_RET:
2531 {
2532 if (bb->isTerminated())
2533 return true;
2534 BasicBlock *leave = BasicBlock::get(func->cfgExit);
2535
2536 if (!isEndOfSubroutine(ip + 1)) {
2537 // insert a PRERET at the entry if this is an early return
2538 // (only needed for sharing code in the epilogue)
2539 BasicBlock *pos = getBB();
2540 setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2541 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2542 setPosition(pos, true);
2543 }
2544 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2545 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2546 }
2547 break;
2548 case TGSI_OPCODE_END:
2549 {
2550 // attach and generate epilogue code
2551 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2552 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2553 setPosition(epilogue, true);
2554 if (prog->getType() == Program::TYPE_FRAGMENT)
2555 exportOutputs();
2556 if (info->io.genUserClip > 0)
2557 handleUserClipPlanes();
2558 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2559 }
2560 break;
2561 case TGSI_OPCODE_SWITCH:
2562 case TGSI_OPCODE_CASE:
2563 ERROR("switch/case opcode encountered, should have been lowered\n");
2564 abort();
2565 break;
2566 case TGSI_OPCODE_LOAD:
2567 handleLOAD(dst0);
2568 break;
2569 case TGSI_OPCODE_STORE:
2570 handleSTORE();
2571 break;
2572 case TGSI_OPCODE_BARRIER:
2573 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2574 geni->fixed = 1;
2575 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2576 break;
2577 case TGSI_OPCODE_MFENCE:
2578 case TGSI_OPCODE_LFENCE:
2579 case TGSI_OPCODE_SFENCE:
2580 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2581 geni->fixed = 1;
2582 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2583 break;
2584 case TGSI_OPCODE_ATOMUADD:
2585 case TGSI_OPCODE_ATOMXCHG:
2586 case TGSI_OPCODE_ATOMCAS:
2587 case TGSI_OPCODE_ATOMAND:
2588 case TGSI_OPCODE_ATOMOR:
2589 case TGSI_OPCODE_ATOMXOR:
2590 case TGSI_OPCODE_ATOMUMIN:
2591 case TGSI_OPCODE_ATOMIMIN:
2592 case TGSI_OPCODE_ATOMUMAX:
2593 case TGSI_OPCODE_ATOMIMAX:
2594 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2595 break;
2596 default:
2597 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2598 assert(0);
2599 break;
2600 }
2601
2602 if (tgsi.dstCount()) {
2603 for (c = 0; c < 4; ++c) {
2604 if (!dst0[c])
2605 continue;
2606 if (dst0[c] != rDst0[c])
2607 mkMov(rDst0[c], dst0[c]);
2608 storeDst(0, c, rDst0[c]);
2609 }
2610 }
2611 vtxBaseValid = 0;
2612
2613 return true;
2614 }
2615
2616 void
2617 Converter::handleUserClipPlanes()
2618 {
2619 Value *res[8];
2620 int n, i, c;
2621
2622 for (c = 0; c < 4; ++c) {
2623 for (i = 0; i < info->io.genUserClip; ++i) {
2624 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
2625 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
2626 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
2627 if (c == 0)
2628 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2629 else
2630 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2631 }
2632 }
2633
2634 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2635
2636 for (i = 0; i < info->io.genUserClip; ++i) {
2637 n = i / 4 + first;
2638 c = i % 4;
2639 Symbol *sym =
2640 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2641 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2642 }
2643 }
2644
2645 void
2646 Converter::exportOutputs()
2647 {
2648 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2649 for (unsigned int c = 0; c < 4; ++c) {
2650 if (!oData.exists(sub.cur->values, i, c))
2651 continue;
2652 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2653 info->out[i].slot[c] * 4);
2654 Value *val = oData.load(sub.cur->values, i, c, NULL);
2655 if (val)
2656 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2657 }
2658 }
2659 }
2660
2661 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2662 code(code),
2663 tgsi(NULL),
2664 tData(this), aData(this), pData(this), oData(this)
2665 {
2666 info = code->info;
2667
2668 const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2669
2670 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2671 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2672 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2673 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2674
2675 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2676 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2677 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_ADDRESS, 0);
2678 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2679
2680 zero = mkImm((uint32_t)0);
2681
2682 vtxBaseValid = 0;
2683 }
2684
2685 Converter::~Converter()
2686 {
2687 }
2688
2689 inline const Converter::Location *
2690 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
2691 {
2692 ValueMap::l_iterator it = s->values.l.find(v);
2693 return it == s->values.l.end() ? NULL : &it->second;
2694 }
2695
2696 template<typename T> inline void
2697 Converter::BindArgumentsPass::updateCallArgs(
2698 Instruction *i, void (Instruction::*setArg)(int, Value *),
2699 T (Function::*proto))
2700 {
2701 Function *g = i->asFlow()->target.fn;
2702 Subroutine *subg = conv.getSubroutine(g);
2703
2704 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2705 Value *v = (g->*proto)[a].get();
2706 const Converter::Location &l = *getValueLocation(subg, v);
2707 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2708
2709 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2710 }
2711 }
2712
2713 template<typename T> inline void
2714 Converter::BindArgumentsPass::updatePrototype(
2715 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2716 {
2717 (func->*updateSet)();
2718
2719 for (unsigned i = 0; i < set->getSize(); ++i) {
2720 Value *v = func->getLValue(i);
2721 const Converter::Location *l = getValueLocation(sub, v);
2722
2723 // only include values with a matching TGSI register
2724 if (set->test(i) && l && !conv.code->locals.count(*l))
2725 (func->*proto).push_back(v);
2726 }
2727 }
2728
2729 bool
2730 Converter::BindArgumentsPass::visit(Function *f)
2731 {
2732 sub = conv.getSubroutine(f);
2733
2734 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2735 !bi.end(); bi.next()) {
2736 for (Instruction *i = BasicBlock::get(bi)->getFirst();
2737 i; i = i->next) {
2738 if (i->op == OP_CALL && !i->asFlow()->builtin) {
2739 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2740 updateCallArgs(i, &Instruction::setDef, &Function::outs);
2741 }
2742 }
2743 }
2744
2745 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2746 return true;
2747 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2748 &Function::buildLiveSets, &Function::ins);
2749 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2750 &Function::buildDefSets, &Function::outs);
2751
2752 return true;
2753 }
2754
2755 bool
2756 Converter::run()
2757 {
2758 BasicBlock *entry = new BasicBlock(prog->main);
2759 BasicBlock *leave = new BasicBlock(prog->main);
2760
2761 prog->main->setEntry(entry);
2762 prog->main->setExit(leave);
2763
2764 setPosition(entry, true);
2765 sub.cur = getSubroutine(prog->main);
2766
2767 if (info->io.genUserClip > 0) {
2768 for (int c = 0; c < 4; ++c)
2769 clipVtx[c] = getScratch();
2770 }
2771
2772 if (prog->getType() == Program::TYPE_FRAGMENT) {
2773 Symbol *sv = mkSysVal(SV_POSITION, 3);
2774 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2775 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2776 }
2777
2778 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2779 if (!handleInstruction(&code->insns[ip]))
2780 return false;
2781 }
2782
2783 if (!BindArgumentsPass(*this).run(prog))
2784 return false;
2785
2786 return true;
2787 }
2788
2789 } // unnamed namespace
2790
2791 namespace nv50_ir {
2792
2793 bool
2794 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2795 {
2796 tgsi::Source src(info);
2797 if (!src.scanSource())
2798 return false;
2799 tlsSize = info->bin.tlsSpace;
2800
2801 Converter builder(this, &src);
2802 return builder.run();
2803 }
2804
2805 } // namespace nv50_ir