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nv50/ir/tgsi: translate SNE as unordered comparison
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 default:
325 assert(0);
326 return nv50_ir::SV_CLOCK;
327 }
328 }
329
330 #define NV50_IR_TEX_TARG_CASE(a, b) \
331 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
332
333 static nv50_ir::TexTarget translateTexture(uint tex)
334 {
335 switch (tex) {
336 NV50_IR_TEX_TARG_CASE(1D, 1D);
337 NV50_IR_TEX_TARG_CASE(2D, 2D);
338 NV50_IR_TEX_TARG_CASE(3D, 3D);
339 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
340 NV50_IR_TEX_TARG_CASE(RECT, RECT);
341 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
342 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
344 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
348
349 case TGSI_TEXTURE_UNKNOWN:
350 default:
351 assert(!"invalid texture target");
352 return nv50_ir::TEX_TARGET_2D;
353 }
354 }
355
356 nv50_ir::DataType Instruction::inferSrcType() const
357 {
358 switch (getOpcode()) {
359 case TGSI_OPCODE_AND:
360 case TGSI_OPCODE_OR:
361 case TGSI_OPCODE_XOR:
362 case TGSI_OPCODE_U2F:
363 case TGSI_OPCODE_UADD:
364 case TGSI_OPCODE_UDIV:
365 case TGSI_OPCODE_UMOD:
366 case TGSI_OPCODE_UMAD:
367 case TGSI_OPCODE_UMUL:
368 case TGSI_OPCODE_UMAX:
369 case TGSI_OPCODE_UMIN:
370 case TGSI_OPCODE_USEQ:
371 case TGSI_OPCODE_USGE:
372 case TGSI_OPCODE_USLT:
373 case TGSI_OPCODE_USNE:
374 case TGSI_OPCODE_USHR:
375 case TGSI_OPCODE_UCMP:
376 return nv50_ir::TYPE_U32;
377 case TGSI_OPCODE_I2F:
378 case TGSI_OPCODE_IDIV:
379 case TGSI_OPCODE_IMAX:
380 case TGSI_OPCODE_IMIN:
381 case TGSI_OPCODE_IABS:
382 case TGSI_OPCODE_INEG:
383 case TGSI_OPCODE_ISGE:
384 case TGSI_OPCODE_ISHR:
385 case TGSI_OPCODE_ISLT:
386 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
387 case TGSI_OPCODE_MOD:
388 case TGSI_OPCODE_UARL:
389 return nv50_ir::TYPE_S32;
390 default:
391 return nv50_ir::TYPE_F32;
392 }
393 }
394
395 nv50_ir::DataType Instruction::inferDstType() const
396 {
397 switch (getOpcode()) {
398 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
399 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
400 case TGSI_OPCODE_I2F:
401 case TGSI_OPCODE_U2F:
402 return nv50_ir::TYPE_F32;
403 default:
404 return inferSrcType();
405 }
406 }
407
408 nv50_ir::CondCode Instruction::getSetCond() const
409 {
410 using namespace nv50_ir;
411
412 switch (getOpcode()) {
413 case TGSI_OPCODE_SLT:
414 case TGSI_OPCODE_ISLT:
415 case TGSI_OPCODE_USLT:
416 return CC_LT;
417 case TGSI_OPCODE_SLE:
418 return CC_LE;
419 case TGSI_OPCODE_SGE:
420 case TGSI_OPCODE_ISGE:
421 case TGSI_OPCODE_USGE:
422 return CC_GE;
423 case TGSI_OPCODE_SGT:
424 return CC_GT;
425 case TGSI_OPCODE_SEQ:
426 case TGSI_OPCODE_USEQ:
427 return CC_EQ;
428 case TGSI_OPCODE_SNE:
429 return CC_NEU;
430 case TGSI_OPCODE_USNE:
431 return CC_NE;
432 case TGSI_OPCODE_SFL:
433 return CC_NEVER;
434 case TGSI_OPCODE_STR:
435 default:
436 return CC_ALWAYS;
437 }
438 }
439
440 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
441
442 static nv50_ir::operation translateOpcode(uint opcode)
443 {
444 switch (opcode) {
445 NV50_IR_OPCODE_CASE(ARL, SHL);
446 NV50_IR_OPCODE_CASE(MOV, MOV);
447
448 NV50_IR_OPCODE_CASE(RCP, RCP);
449 NV50_IR_OPCODE_CASE(RSQ, RSQ);
450
451 NV50_IR_OPCODE_CASE(MUL, MUL);
452 NV50_IR_OPCODE_CASE(ADD, ADD);
453
454 NV50_IR_OPCODE_CASE(MIN, MIN);
455 NV50_IR_OPCODE_CASE(MAX, MAX);
456 NV50_IR_OPCODE_CASE(SLT, SET);
457 NV50_IR_OPCODE_CASE(SGE, SET);
458 NV50_IR_OPCODE_CASE(MAD, MAD);
459 NV50_IR_OPCODE_CASE(SUB, SUB);
460
461 NV50_IR_OPCODE_CASE(FLR, FLOOR);
462 NV50_IR_OPCODE_CASE(ROUND, CVT);
463 NV50_IR_OPCODE_CASE(EX2, EX2);
464 NV50_IR_OPCODE_CASE(LG2, LG2);
465 NV50_IR_OPCODE_CASE(POW, POW);
466
467 NV50_IR_OPCODE_CASE(ABS, ABS);
468
469 NV50_IR_OPCODE_CASE(COS, COS);
470 NV50_IR_OPCODE_CASE(DDX, DFDX);
471 NV50_IR_OPCODE_CASE(DDY, DFDY);
472 NV50_IR_OPCODE_CASE(KILP, DISCARD);
473
474 NV50_IR_OPCODE_CASE(SEQ, SET);
475 NV50_IR_OPCODE_CASE(SFL, SET);
476 NV50_IR_OPCODE_CASE(SGT, SET);
477 NV50_IR_OPCODE_CASE(SIN, SIN);
478 NV50_IR_OPCODE_CASE(SLE, SET);
479 NV50_IR_OPCODE_CASE(SNE, SET);
480 NV50_IR_OPCODE_CASE(STR, SET);
481 NV50_IR_OPCODE_CASE(TEX, TEX);
482 NV50_IR_OPCODE_CASE(TXD, TXD);
483 NV50_IR_OPCODE_CASE(TXP, TEX);
484
485 NV50_IR_OPCODE_CASE(BRA, BRA);
486 NV50_IR_OPCODE_CASE(CAL, CALL);
487 NV50_IR_OPCODE_CASE(RET, RET);
488 NV50_IR_OPCODE_CASE(CMP, SLCT);
489
490 NV50_IR_OPCODE_CASE(TXB, TXB);
491
492 NV50_IR_OPCODE_CASE(DIV, DIV);
493
494 NV50_IR_OPCODE_CASE(TXL, TXL);
495
496 NV50_IR_OPCODE_CASE(CEIL, CEIL);
497 NV50_IR_OPCODE_CASE(I2F, CVT);
498 NV50_IR_OPCODE_CASE(NOT, NOT);
499 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
500 NV50_IR_OPCODE_CASE(SHL, SHL);
501
502 NV50_IR_OPCODE_CASE(AND, AND);
503 NV50_IR_OPCODE_CASE(OR, OR);
504 NV50_IR_OPCODE_CASE(MOD, MOD);
505 NV50_IR_OPCODE_CASE(XOR, XOR);
506 NV50_IR_OPCODE_CASE(SAD, SAD);
507 NV50_IR_OPCODE_CASE(TXF, TXF);
508 NV50_IR_OPCODE_CASE(TXQ, TXQ);
509
510 NV50_IR_OPCODE_CASE(EMIT, EMIT);
511 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
512
513 NV50_IR_OPCODE_CASE(KIL, DISCARD);
514
515 NV50_IR_OPCODE_CASE(F2I, CVT);
516 NV50_IR_OPCODE_CASE(IDIV, DIV);
517 NV50_IR_OPCODE_CASE(IMAX, MAX);
518 NV50_IR_OPCODE_CASE(IMIN, MIN);
519 NV50_IR_OPCODE_CASE(IABS, ABS);
520 NV50_IR_OPCODE_CASE(INEG, NEG);
521 NV50_IR_OPCODE_CASE(ISGE, SET);
522 NV50_IR_OPCODE_CASE(ISHR, SHR);
523 NV50_IR_OPCODE_CASE(ISLT, SET);
524 NV50_IR_OPCODE_CASE(F2U, CVT);
525 NV50_IR_OPCODE_CASE(U2F, CVT);
526 NV50_IR_OPCODE_CASE(UADD, ADD);
527 NV50_IR_OPCODE_CASE(UDIV, DIV);
528 NV50_IR_OPCODE_CASE(UMAD, MAD);
529 NV50_IR_OPCODE_CASE(UMAX, MAX);
530 NV50_IR_OPCODE_CASE(UMIN, MIN);
531 NV50_IR_OPCODE_CASE(UMOD, MOD);
532 NV50_IR_OPCODE_CASE(UMUL, MUL);
533 NV50_IR_OPCODE_CASE(USEQ, SET);
534 NV50_IR_OPCODE_CASE(USGE, SET);
535 NV50_IR_OPCODE_CASE(USHR, SHR);
536 NV50_IR_OPCODE_CASE(USLT, SET);
537 NV50_IR_OPCODE_CASE(USNE, SET);
538
539 NV50_IR_OPCODE_CASE(LOAD, TXF);
540 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
541 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
542 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
543 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
544 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
545 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
546 NV50_IR_OPCODE_CASE(GATHER4, TXG);
547 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
548
549 NV50_IR_OPCODE_CASE(END, EXIT);
550
551 default:
552 return nv50_ir::OP_NOP;
553 }
554 }
555
556 bool Instruction::checkDstSrcAliasing() const
557 {
558 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
559 return false;
560
561 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
562 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
563 break;
564 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
565 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
566 return true;
567 }
568 return false;
569 }
570
571 class Source
572 {
573 public:
574 Source(struct nv50_ir_prog_info *);
575 ~Source();
576
577 struct Subroutine
578 {
579 unsigned pc;
580 };
581
582 public:
583 bool scanSource();
584 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
585
586 public:
587 struct tgsi_shader_info scan;
588 struct tgsi_full_instruction *insns;
589 const struct tgsi_token *tokens;
590 struct nv50_ir_prog_info *info;
591
592 nv50_ir::DynArray tempArrays;
593 nv50_ir::DynArray immdArrays;
594 int tempArrayCount;
595 int immdArrayCount;
596
597 bool mainTempsInLMem;
598
599 int clipVertexOutput;
600
601 uint8_t *resourceTargets; // TGSI_TEXTURE_*
602 unsigned resourceCount;
603
604 Subroutine *subroutines;
605 unsigned subroutineCount;
606
607 private:
608 int inferSysValDirection(unsigned sn) const;
609 bool scanDeclaration(const struct tgsi_full_declaration *);
610 bool scanInstruction(const struct tgsi_full_instruction *);
611 void scanProperty(const struct tgsi_full_property *);
612 void scanImmediate(const struct tgsi_full_immediate *);
613
614 inline bool isEdgeFlagPassthrough(const Instruction&) const;
615 };
616
617 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
618 {
619 tokens = (const struct tgsi_token *)info->bin.source;
620
621 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
622 tgsi_dump(tokens, 0);
623
624 resourceTargets = NULL;
625 subroutines = NULL;
626
627 mainTempsInLMem = FALSE;
628 }
629
630 Source::~Source()
631 {
632 if (insns)
633 FREE(insns);
634
635 if (info->immd.data)
636 FREE(info->immd.data);
637 if (info->immd.type)
638 FREE(info->immd.type);
639
640 if (resourceTargets)
641 delete[] resourceTargets;
642 if (subroutines)
643 delete[] subroutines;
644 }
645
646 bool Source::scanSource()
647 {
648 unsigned insnCount = 0;
649 unsigned subrCount = 0;
650 struct tgsi_parse_context parse;
651
652 tgsi_scan_shader(tokens, &scan);
653
654 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
655 sizeof(insns[0]));
656 if (!insns)
657 return false;
658
659 clipVertexOutput = -1;
660
661 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
662 resourceTargets = new uint8_t[resourceCount];
663
664 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
665 subroutines = new Subroutine[subroutineCount];
666
667 info->immd.bufSize = 0;
668 tempArrayCount = 0;
669 immdArrayCount = 0;
670
671 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
672 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
673 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
674
675 if (info->type == PIPE_SHADER_FRAGMENT) {
676 info->prop.fp.writesDepth = scan.writes_z;
677 info->prop.fp.usesDiscard = scan.uses_kill;
678 } else
679 if (info->type == PIPE_SHADER_GEOMETRY) {
680 info->prop.gp.instanceCount = 1; // default value
681 }
682
683 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
684 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
685
686 tgsi_parse_init(&parse, tokens);
687 while (!tgsi_parse_end_of_tokens(&parse)) {
688 tgsi_parse_token(&parse);
689
690 switch (parse.FullToken.Token.Type) {
691 case TGSI_TOKEN_TYPE_IMMEDIATE:
692 scanImmediate(&parse.FullToken.FullImmediate);
693 break;
694 case TGSI_TOKEN_TYPE_DECLARATION:
695 scanDeclaration(&parse.FullToken.FullDeclaration);
696 break;
697 case TGSI_TOKEN_TYPE_INSTRUCTION:
698 insns[insnCount++] = parse.FullToken.FullInstruction;
699 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
700 subroutines[++subrCount].pc = insnCount - 1;
701 else
702 scanInstruction(&parse.FullToken.FullInstruction);
703 break;
704 case TGSI_TOKEN_TYPE_PROPERTY:
705 scanProperty(&parse.FullToken.FullProperty);
706 break;
707 default:
708 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
709 break;
710 }
711 }
712 tgsi_parse_free(&parse);
713
714 if (mainTempsInLMem)
715 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
716
717 if (info->io.genUserClip > 0)
718 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
719
720 return info->assignSlots(info) == 0;
721 }
722
723 void Source::scanProperty(const struct tgsi_full_property *prop)
724 {
725 switch (prop->Property.PropertyName) {
726 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
727 info->prop.gp.outputPrim = prop->u[0].Data;
728 break;
729 case TGSI_PROPERTY_GS_INPUT_PRIM:
730 info->prop.gp.inputPrim = prop->u[0].Data;
731 break;
732 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
733 info->prop.gp.maxVertices = prop->u[0].Data;
734 break;
735 #if 0
736 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
737 info->prop.gp.instanceCount = prop->u[0].Data;
738 break;
739 #endif
740 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
741 info->prop.fp.separateFragData = TRUE;
742 break;
743 case TGSI_PROPERTY_FS_COORD_ORIGIN:
744 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
745 // we don't care
746 break;
747 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
748 info->io.genUserClip = -1;
749 break;
750 default:
751 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
752 break;
753 }
754 }
755
756 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
757 {
758 const unsigned n = info->immd.count++;
759
760 assert(n < scan.immediate_count);
761
762 for (int c = 0; c < 4; ++c)
763 info->immd.data[n * 4 + c] = imm->u[c].Uint;
764
765 info->immd.type[n] = imm->Immediate.DataType;
766 }
767
768 int Source::inferSysValDirection(unsigned sn) const
769 {
770 switch (sn) {
771 case TGSI_SEMANTIC_INSTANCEID:
772 // case TGSI_SEMANTIC_VERTEXID:
773 return 1;
774 #if 0
775 case TGSI_SEMANTIC_LAYER:
776 case TGSI_SEMANTIC_VIEWPORTINDEX:
777 return 0;
778 #endif
779 case TGSI_SEMANTIC_PRIMID:
780 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
781 default:
782 return 0;
783 }
784 }
785
786 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
787 {
788 unsigned i;
789 unsigned sn = TGSI_SEMANTIC_GENERIC;
790 unsigned si = 0;
791 const unsigned first = decl->Range.First, last = decl->Range.Last;
792
793 if (decl->Declaration.Semantic) {
794 sn = decl->Semantic.Name;
795 si = decl->Semantic.Index;
796 }
797
798 switch (decl->Declaration.File) {
799 case TGSI_FILE_INPUT:
800 if (info->type == PIPE_SHADER_VERTEX) {
801 // all vertex attributes are equal
802 for (i = first; i <= last; ++i) {
803 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
804 info->in[i].si = i;
805 }
806 } else {
807 for (i = first; i <= last; ++i, ++si) {
808 info->in[i].id = i;
809 info->in[i].sn = sn;
810 info->in[i].si = si;
811 if (info->type == PIPE_SHADER_FRAGMENT) {
812 // translate interpolation mode
813 switch (decl->Declaration.Interpolate) {
814 case TGSI_INTERPOLATE_CONSTANT:
815 info->in[i].flat = 1;
816 break;
817 case TGSI_INTERPOLATE_LINEAR:
818 if (sn != TGSI_SEMANTIC_COLOR) // GL_NICEST
819 info->in[i].linear = 1;
820 break;
821 default:
822 break;
823 }
824 if (decl->Declaration.Centroid)
825 info->in[i].centroid = 1;
826 }
827 }
828 }
829 break;
830 case TGSI_FILE_OUTPUT:
831 for (i = first; i <= last; ++i, ++si) {
832 switch (sn) {
833 case TGSI_SEMANTIC_POSITION:
834 if (info->type == PIPE_SHADER_FRAGMENT)
835 info->io.fragDepth = i;
836 else
837 if (clipVertexOutput < 0)
838 clipVertexOutput = i;
839 break;
840 case TGSI_SEMANTIC_COLOR:
841 if (info->type == PIPE_SHADER_FRAGMENT)
842 info->prop.fp.numColourResults++;
843 break;
844 case TGSI_SEMANTIC_EDGEFLAG:
845 info->io.edgeFlagOut = i;
846 break;
847 case TGSI_SEMANTIC_CLIPVERTEX:
848 clipVertexOutput = i;
849 break;
850 case TGSI_SEMANTIC_CLIPDIST:
851 info->io.clipDistanceMask |=
852 decl->Declaration.UsageMask << (si * 4);
853 info->io.genUserClip = -1;
854 break;
855 default:
856 break;
857 }
858 info->out[i].id = i;
859 info->out[i].sn = sn;
860 info->out[i].si = si;
861 }
862 break;
863 case TGSI_FILE_SYSTEM_VALUE:
864 for (i = first; i <= last; ++i, ++si) {
865 info->sv[i].sn = sn;
866 info->sv[i].si = si;
867 info->sv[i].input = inferSysValDirection(sn);
868 }
869 break;
870 case TGSI_FILE_RESOURCE:
871 for (i = first; i <= last; ++i)
872 resourceTargets[i] = decl->Resource.Resource;
873 break;
874 case TGSI_FILE_IMMEDIATE_ARRAY:
875 {
876 if (decl->Dim.Index2D >= immdArrayCount)
877 immdArrayCount = decl->Dim.Index2D + 1;
878 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
879 int c;
880 uint32_t base, count;
881 switch (decl->Declaration.UsageMask) {
882 case 0x1: c = 1; break;
883 case 0x3: c = 2; break;
884 default:
885 c = 4;
886 break;
887 }
888 immdArrays[decl->Dim.Index2D].u32 |= c;
889 count = (last + 1) * c;
890 base = info->immd.bufSize / 4;
891 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
892 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
893 info->immd.bufSize);
894 // NOTE: this assumes array declarations are ordered by Dim.Index2D
895 for (i = 0; i < count; ++i)
896 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
897 }
898 break;
899 case TGSI_FILE_TEMPORARY_ARRAY:
900 {
901 if (decl->Dim.Index2D >= tempArrayCount)
902 tempArrayCount = decl->Dim.Index2D + 1;
903 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
904 int c;
905 uint32_t count;
906 switch (decl->Declaration.UsageMask) {
907 case 0x1: c = 1; break;
908 case 0x3: c = 2; break;
909 default:
910 c = 4;
911 break;
912 }
913 tempArrays[decl->Dim.Index2D].u32 |= c;
914 count = (last + 1) * c;
915 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
916 }
917 break;
918 case TGSI_FILE_NULL:
919 case TGSI_FILE_TEMPORARY:
920 case TGSI_FILE_ADDRESS:
921 case TGSI_FILE_CONSTANT:
922 case TGSI_FILE_IMMEDIATE:
923 case TGSI_FILE_PREDICATE:
924 case TGSI_FILE_SAMPLER:
925 break;
926 default:
927 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
928 return false;
929 }
930 return true;
931 }
932
933 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
934 {
935 return insn.getOpcode() == TGSI_OPCODE_MOV &&
936 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
937 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
938 }
939
940 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
941 {
942 Instruction insn(inst);
943
944 if (insn.dstCount()) {
945 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
946 Instruction::DstRegister dst = insn.getDst(0);
947
948 if (dst.isIndirect(0))
949 for (unsigned i = 0; i < info->numOutputs; ++i)
950 info->out[i].mask = 0xf;
951 else
952 info->out[dst.getIndex(0)].mask |= dst.getMask();
953
954 if (isEdgeFlagPassthrough(insn))
955 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
956 } else
957 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
958 if (insn.getDst(0).isIndirect(0))
959 mainTempsInLMem = TRUE;
960 }
961 }
962
963 for (unsigned s = 0; s < insn.srcCount(); ++s) {
964 Instruction::SrcRegister src = insn.getSrc(s);
965 if (src.getFile() == TGSI_FILE_TEMPORARY)
966 if (src.isIndirect(0))
967 mainTempsInLMem = TRUE;
968 if (src.getFile() != TGSI_FILE_INPUT)
969 continue;
970 unsigned mask = insn.srcMask(s);
971
972 if (src.isIndirect(0)) {
973 for (unsigned i = 0; i < info->numInputs; ++i)
974 info->in[i].mask = 0xf;
975 } else {
976 for (unsigned c = 0; c < 4; ++c) {
977 if (!(mask & (1 << c)))
978 continue;
979 int k = src.getSwizzle(c);
980 int i = src.getIndex(0);
981 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
982 if (k <= TGSI_SWIZZLE_W)
983 info->in[i].mask |= 1 << k;
984 }
985 }
986 }
987 return true;
988 }
989
990 nv50_ir::TexInstruction::Target
991 Instruction::getTexture(const tgsi::Source *code, int s) const
992 {
993 if (insn->Instruction.Texture) {
994 return translateTexture(insn->Texture.Texture);
995 } else {
996 // XXX: indirect access
997 unsigned int r = getSrc(s).getIndex(0);
998 assert(r < code->resourceCount);
999 return translateTexture(code->resourceTargets[r]);
1000 }
1001 }
1002
1003 } // namespace tgsi
1004
1005 namespace {
1006
1007 using namespace nv50_ir;
1008
1009 class Converter : public BuildUtil
1010 {
1011 public:
1012 Converter(Program *, const tgsi::Source *);
1013 ~Converter();
1014
1015 bool run();
1016
1017 private:
1018 Value *getVertexBase(int s);
1019 Value *fetchSrc(int s, int c);
1020 Value *acquireDst(int d, int c);
1021 void storeDst(int d, int c, Value *);
1022
1023 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1024 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1025 Value *val, Value *ptr);
1026
1027 Value *applySrcMod(Value *, int s, int c);
1028
1029 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1030 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1031 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1032
1033 bool handleInstruction(const struct tgsi_full_instruction *);
1034 void exportOutputs();
1035 inline bool isEndOfSubroutine(uint ip);
1036
1037 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1038
1039 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1040 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1041 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1042 void handleTXF(Value *dst0[4], int R);
1043 void handleTXQ(Value *dst0[4], enum TexQuery);
1044 void handleLIT(Value *dst0[4]);
1045 void handleUserClipPlanes();
1046
1047 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1048
1049 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1050
1051 Value *buildDot(int dim);
1052
1053 private:
1054 const struct tgsi::Source *code;
1055 const struct nv50_ir_prog_info *info;
1056
1057 uint ip; // instruction pointer
1058
1059 tgsi::Instruction tgsi;
1060
1061 DataType dstTy;
1062 DataType srcTy;
1063
1064 DataArray tData; // TGSI_FILE_TEMPORARY
1065 DataArray aData; // TGSI_FILE_ADDRESS
1066 DataArray pData; // TGSI_FILE_PREDICATE
1067 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1068 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1069 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1070
1071 Value *zero;
1072 Value *fragCoord[4];
1073 Value *clipVtx[4];
1074
1075 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1076 uint8_t vtxBaseValid;
1077
1078 Stack condBBs; // fork BB, then else clause BB
1079 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1080 Stack loopBBs; // loop headers
1081 Stack breakBBs; // end of / after loop
1082 Stack entryBBs; // start of current (inlined) subroutine
1083 Stack leaveBBs; // end of current (inlined) subroutine
1084 Stack retIPs; // return instruction pointer
1085 };
1086
1087 Symbol *
1088 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1089 {
1090 const int swz = src.getSwizzle(c);
1091
1092 return makeSym(src.getFile(),
1093 src.is2D() ? src.getIndex(1) : 0,
1094 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1095 src.getIndex(0) * 16 + swz * 4);
1096 }
1097
1098 Symbol *
1099 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1100 {
1101 return makeSym(dst.getFile(),
1102 dst.is2D() ? dst.getIndex(1) : 0,
1103 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1104 dst.getIndex(0) * 16 + c * 4);
1105 }
1106
1107 Symbol *
1108 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1109 {
1110 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1111
1112 sym->reg.fileIndex = fileIdx;
1113
1114 if (idx >= 0) {
1115 if (sym->reg.file == FILE_SHADER_INPUT)
1116 sym->setOffset(info->in[idx].slot[c] * 4);
1117 else
1118 if (sym->reg.file == FILE_SHADER_OUTPUT)
1119 sym->setOffset(info->out[idx].slot[c] * 4);
1120 else
1121 if (sym->reg.file == FILE_SYSTEM_VALUE)
1122 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1123 else
1124 sym->setOffset(address);
1125 } else {
1126 sym->setOffset(address);
1127 }
1128 return sym;
1129 }
1130
1131 static inline uint8_t
1132 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1133 {
1134 uint8_t mode;
1135
1136 if (var->flat)
1137 mode = NV50_IR_INTERP_FLAT;
1138 else
1139 if (var->linear)
1140 mode = NV50_IR_INTERP_LINEAR;
1141 else
1142 mode = NV50_IR_INTERP_PERSPECTIVE;
1143
1144 op = (mode == NV50_IR_INTERP_PERSPECTIVE) ? OP_PINTERP : OP_LINTERP;
1145
1146 if (var->centroid)
1147 mode |= NV50_IR_INTERP_CENTROID;
1148
1149 return mode;
1150 }
1151
1152 Value *
1153 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1154 {
1155 operation op;
1156
1157 // XXX: no way to know interpolation mode if we don't know what's accessed
1158 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1159 src.getIndex(0)], op);
1160
1161 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1162
1163 insn->setDef(0, getScratch());
1164 insn->setSrc(0, srcToSym(src, c));
1165 if (op == OP_PINTERP)
1166 insn->setSrc(1, fragCoord[3]);
1167 if (ptr)
1168 insn->setIndirect(0, 0, ptr);
1169
1170 insn->setInterpolate(mode);
1171
1172 bb->insertTail(insn);
1173 return insn->getDef(0);
1174 }
1175
1176 Value *
1177 Converter::applySrcMod(Value *val, int s, int c)
1178 {
1179 Modifier m = tgsi.getSrc(s).getMod(c);
1180 DataType ty = tgsi.inferSrcType();
1181
1182 if (m & Modifier(NV50_IR_MOD_ABS))
1183 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1184
1185 if (m & Modifier(NV50_IR_MOD_NEG))
1186 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1187
1188 return val;
1189 }
1190
1191 Value *
1192 Converter::getVertexBase(int s)
1193 {
1194 assert(s < 5);
1195 if (!(vtxBaseValid & (1 << s))) {
1196 const int index = tgsi.getSrc(s).getIndex(1);
1197 Value *rel = NULL;
1198 if (tgsi.getSrc(s).isIndirect(1))
1199 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1200 vtxBaseValid |= 1 << s;
1201 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1202 }
1203 return vtxBase[s];
1204 }
1205
1206 Value *
1207 Converter::fetchSrc(int s, int c)
1208 {
1209 Value *res;
1210 Value *ptr = NULL, *dimRel = NULL;
1211
1212 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1213
1214 if (src.isIndirect(0))
1215 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1216
1217 if (src.is2D()) {
1218 switch (src.getFile()) {
1219 case TGSI_FILE_INPUT:
1220 dimRel = getVertexBase(s);
1221 break;
1222 case TGSI_FILE_CONSTANT:
1223 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1224 if (src.isIndirect(1))
1225 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1226 break;
1227 default:
1228 break;
1229 }
1230 }
1231
1232 res = fetchSrc(src, c, ptr);
1233
1234 if (dimRel)
1235 res->getInsn()->setIndirect(0, 1, dimRel);
1236
1237 return applySrcMod(res, s, c);
1238 }
1239
1240 Value *
1241 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1242 {
1243 const int idx = src.getIndex(0);
1244 const int swz = src.getSwizzle(c);
1245
1246 switch (src.getFile()) {
1247 case TGSI_FILE_TEMPORARY:
1248 return tData.load(idx, swz, ptr);
1249 case TGSI_FILE_PREDICATE:
1250 return pData.load(idx, swz, ptr);
1251 case TGSI_FILE_ADDRESS:
1252 return aData.load(idx, swz, ptr);
1253
1254 case TGSI_FILE_TEMPORARY_ARRAY:
1255 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1256 return lData[src.getIndex(1)].load(idx, swz, ptr);
1257 case TGSI_FILE_IMMEDIATE_ARRAY:
1258 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1259 return iData[src.getIndex(1)].load(idx, swz, ptr);
1260
1261 case TGSI_FILE_IMMEDIATE:
1262 assert(!ptr);
1263 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1264
1265 case TGSI_FILE_CONSTANT:
1266 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1267
1268 case TGSI_FILE_INPUT:
1269 if (prog->getType() == Program::TYPE_FRAGMENT) {
1270 // don't load masked inputs, won't be assigned a slot
1271 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1272 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1273 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1274 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1275 return interpolate(src, c, ptr);
1276 }
1277 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1278
1279 case TGSI_FILE_SYSTEM_VALUE:
1280 assert(!ptr);
1281 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1282
1283 case TGSI_FILE_OUTPUT:
1284 case TGSI_FILE_RESOURCE:
1285 case TGSI_FILE_SAMPLER:
1286 case TGSI_FILE_NULL:
1287 default:
1288 assert(!"invalid/unhandled TGSI source file");
1289 return NULL;
1290 }
1291 }
1292
1293 Value *
1294 Converter::acquireDst(int d, int c)
1295 {
1296 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1297
1298 if (dst.isMasked(c))
1299 return NULL;
1300 if (dst.isIndirect(0))
1301 return getScratch();
1302
1303 const int idx = dst.getIndex(0);
1304
1305 switch (dst.getFile()) {
1306 case TGSI_FILE_TEMPORARY:
1307 return tData.acquire(idx, c);
1308 case TGSI_FILE_TEMPORARY_ARRAY:
1309 return getScratch();
1310 case TGSI_FILE_PREDICATE:
1311 return pData.acquire(idx, c);
1312 case TGSI_FILE_ADDRESS:
1313 return aData.acquire(idx, c);
1314
1315 case TGSI_FILE_OUTPUT:
1316 if (prog->getType() == Program::TYPE_FRAGMENT)
1317 return oData.acquire(idx, c);
1318 // fall through
1319 case TGSI_FILE_SYSTEM_VALUE:
1320 return getScratch();
1321
1322 default:
1323 assert(!"invalid dst file");
1324 return NULL;
1325 }
1326 }
1327
1328 void
1329 Converter::storeDst(int d, int c, Value *val)
1330 {
1331 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1332
1333 switch (tgsi.getSaturate()) {
1334 case TGSI_SAT_NONE:
1335 break;
1336 case TGSI_SAT_ZERO_ONE:
1337 mkOp1(OP_SAT, dstTy, val, val);
1338 break;
1339 case TGSI_SAT_MINUS_PLUS_ONE:
1340 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1341 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1342 break;
1343 default:
1344 assert(!"invalid saturation mode");
1345 break;
1346 }
1347
1348 Value *ptr = dst.isIndirect(0) ?
1349 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1350
1351 if (info->io.genUserClip > 0 &&
1352 dst.getFile() == TGSI_FILE_OUTPUT &&
1353 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1354 mkMov(clipVtx[c], val);
1355 val = clipVtx[c];
1356 }
1357
1358 storeDst(dst, c, val, ptr);
1359 }
1360
1361 void
1362 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1363 Value *val, Value *ptr)
1364 {
1365 const int idx = dst.getIndex(0);
1366
1367 switch (dst.getFile()) {
1368 case TGSI_FILE_TEMPORARY:
1369 tData.store(idx, c, ptr, val);
1370 break;
1371 case TGSI_FILE_TEMPORARY_ARRAY:
1372 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1373 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1374 break;
1375 case TGSI_FILE_PREDICATE:
1376 pData.store(idx, c, ptr, val);
1377 break;
1378 case TGSI_FILE_ADDRESS:
1379 aData.store(idx, c, ptr, val);
1380 break;
1381
1382 case TGSI_FILE_OUTPUT:
1383 if (prog->getType() == Program::TYPE_FRAGMENT)
1384 oData.store(idx, c, ptr, val);
1385 else
1386 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1387 break;
1388
1389 case TGSI_FILE_SYSTEM_VALUE:
1390 assert(!ptr);
1391 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1392 break;
1393
1394 default:
1395 assert(!"invalid dst file");
1396 break;
1397 }
1398 }
1399
1400 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1401 for (chan = 0; chan < 4; ++chan) \
1402 if (!inst.getDst(d).isMasked(chan))
1403
1404 Value *
1405 Converter::buildDot(int dim)
1406 {
1407 assert(dim > 0);
1408
1409 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1410 Value *dotp = getScratch();
1411
1412 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1413
1414 for (int c = 1; c < dim; ++c) {
1415 src0 = fetchSrc(0, c);
1416 src1 = fetchSrc(1, c);
1417 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1418 }
1419 return dotp;
1420 }
1421
1422 void
1423 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1424 {
1425 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1426 join->fixed = 1;
1427 conv->insertHead(join);
1428
1429 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1430 fork->insertBefore(fork->getExit(), fork->joinAt);
1431 }
1432
1433 void
1434 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1435 {
1436 unsigned rIdx = 0, sIdx = 0;
1437
1438 if (R >= 0)
1439 rIdx = tgsi.getSrc(R).getIndex(0);
1440 if (S >= 0)
1441 sIdx = tgsi.getSrc(S).getIndex(0);
1442
1443 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1444
1445 if (tgsi.getSrc(R).isIndirect(0)) {
1446 tex->tex.rIndirectSrc = s;
1447 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1448 }
1449 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1450 tex->tex.sIndirectSrc = s;
1451 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1452 }
1453 }
1454
1455 void
1456 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1457 {
1458 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1459 tex->tex.query = query;
1460 unsigned int c, d;
1461
1462 for (d = 0, c = 0; c < 4; ++c) {
1463 if (!dst0[c])
1464 continue;
1465 tex->tex.mask |= 1 << c;
1466 tex->setDef(d++, dst0[c]);
1467 }
1468 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1469
1470 setTexRS(tex, c, 1, -1);
1471
1472 bb->insertTail(tex);
1473 }
1474
1475 void
1476 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1477 {
1478 Value *proj = fetchSrc(0, 3);
1479 Instruction *insn = proj->getUniqueInsn();
1480 int c;
1481
1482 if (insn->op == OP_PINTERP) {
1483 bb->insertTail(insn = insn->clone(true));
1484 insn->op = OP_LINTERP;
1485 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1486 insn->setSrc(1, NULL);
1487 proj = insn->getDef(0);
1488 }
1489 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1490
1491 for (c = 0; c < 4; ++c) {
1492 if (!(mask & (1 << c)))
1493 continue;
1494 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1495 continue;
1496 mask &= ~(1 << c);
1497
1498 bb->insertTail(insn = insn->clone(true));
1499 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1500 insn->setSrc(1, proj);
1501 dst[c] = insn->getDef(0);
1502 }
1503 if (!mask)
1504 return;
1505
1506 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1507
1508 for (c = 0; c < 4; ++c)
1509 if (mask & (1 << c))
1510 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1511 }
1512
1513 // order of nv50 ir sources: x y z layer lod/bias shadow
1514 // order of TGSI TEX sources: x y z layer shadow lod/bias
1515 // lowering will finally set the hw specific order (like array first on nvc0)
1516 void
1517 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1518 {
1519 Value *val;
1520 Value *arg[4], *src[8];
1521 Value *lod = NULL, *shd = NULL;
1522 unsigned int s, c, d;
1523 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1524
1525 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1526
1527 for (s = 0; s < tgt.getArgCount(); ++s)
1528 arg[s] = src[s] = fetchSrc(0, s);
1529
1530 if (texi->op == OP_TXL || texi->op == OP_TXB)
1531 lod = fetchSrc(L >> 4, L & 3);
1532
1533 if (C == 0x0f)
1534 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1535
1536 if (tgt.isShadow())
1537 shd = fetchSrc(C >> 4, C & 3);
1538
1539 if (texi->op == OP_TXD) {
1540 for (c = 0; c < tgt.getDim(); ++c) {
1541 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1542 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1543 }
1544 }
1545
1546 // cube textures don't care about projection value, it's divided out
1547 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1548 unsigned int n = tgt.getDim();
1549 if (shd) {
1550 arg[n] = shd;
1551 ++n;
1552 assert(tgt.getDim() == tgt.getArgCount());
1553 }
1554 loadProjTexCoords(src, arg, (1 << n) - 1);
1555 if (shd)
1556 shd = src[n - 1];
1557 }
1558
1559 if (tgt.isCube()) {
1560 for (c = 0; c < 3; ++c)
1561 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1562 val = getScratch();
1563 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1564 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1565 mkOp1(OP_RCP, TYPE_F32, val, val);
1566 for (c = 0; c < 3; ++c)
1567 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1568 }
1569
1570 for (c = 0, d = 0; c < 4; ++c) {
1571 if (dst[c]) {
1572 texi->setDef(d++, dst[c]);
1573 texi->tex.mask |= 1 << c;
1574 } else {
1575 // NOTE: maybe hook up def too, for CSE
1576 }
1577 }
1578 for (s = 0; s < tgt.getArgCount(); ++s)
1579 texi->setSrc(s, src[s]);
1580 if (lod)
1581 texi->setSrc(s++, lod);
1582 if (shd)
1583 texi->setSrc(s++, shd);
1584
1585 setTexRS(texi, s, R, S);
1586
1587 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1588 texi->tex.levelZero = true;
1589
1590 bb->insertTail(texi);
1591 }
1592
1593 // 1st source: xyz = coordinates, w = lod
1594 // 2nd source: offset
1595 void
1596 Converter::handleTXF(Value *dst[4], int R)
1597 {
1598 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1599 unsigned int c, d, s;
1600
1601 texi->tex.target = tgsi.getTexture(code, R);
1602
1603 for (c = 0, d = 0; c < 4; ++c) {
1604 if (dst[c]) {
1605 texi->setDef(d++, dst[c]);
1606 texi->tex.mask |= 1 << c;
1607 }
1608 }
1609 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1610 texi->setSrc(c, fetchSrc(0, c));
1611 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1612
1613 setTexRS(texi, c, R, -1);
1614
1615 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1616 for (c = 0; c < 3; ++c) {
1617 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1618 if (texi->tex.offset[s][c])
1619 texi->tex.useOffsets = s + 1;
1620 }
1621 }
1622
1623 bb->insertTail(texi);
1624 }
1625
1626 void
1627 Converter::handleLIT(Value *dst0[4])
1628 {
1629 Value *val0 = NULL;
1630 unsigned int mask = tgsi.getDst(0).getMask();
1631
1632 if (mask & (1 << 0))
1633 loadImm(dst0[0], 1.0f);
1634
1635 if (mask & (1 << 3))
1636 loadImm(dst0[3], 1.0f);
1637
1638 if (mask & (3 << 1)) {
1639 val0 = getScratch();
1640 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1641 if (mask & (1 << 1))
1642 mkMov(dst0[1], val0);
1643 }
1644
1645 if (mask & (1 << 2)) {
1646 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1647 Value *val1 = getScratch(), *val3 = getScratch();
1648
1649 Value *pos128 = loadImm(NULL, +127.999999f);
1650 Value *neg128 = loadImm(NULL, -127.999999f);
1651
1652 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1653 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1654 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1655 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1656
1657 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1658 }
1659 }
1660
1661 bool
1662 Converter::isEndOfSubroutine(uint ip)
1663 {
1664 assert(ip < code->scan.num_instructions);
1665 tgsi::Instruction insn(&code->insns[ip]);
1666 return (insn.getOpcode() == TGSI_OPCODE_END ||
1667 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1668 // does END occur at end of main or the very end ?
1669 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1670 }
1671
1672 bool
1673 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1674 {
1675 Value *dst0[4], *rDst0[4];
1676 Value *src0, *src1, *src2;
1677 Value *val0, *val1;
1678 int c;
1679
1680 tgsi = tgsi::Instruction(insn);
1681
1682 bool useScratchDst = tgsi.checkDstSrcAliasing();
1683
1684 operation op = tgsi.getOP();
1685 dstTy = tgsi.inferDstType();
1686 srcTy = tgsi.inferSrcType();
1687
1688 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1689
1690 if (tgsi.dstCount()) {
1691 for (c = 0; c < 4; ++c) {
1692 rDst0[c] = acquireDst(0, c);
1693 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1694 }
1695 }
1696
1697 switch (tgsi.getOpcode()) {
1698 case TGSI_OPCODE_ADD:
1699 case TGSI_OPCODE_UADD:
1700 case TGSI_OPCODE_AND:
1701 case TGSI_OPCODE_DIV:
1702 case TGSI_OPCODE_IDIV:
1703 case TGSI_OPCODE_UDIV:
1704 case TGSI_OPCODE_MAX:
1705 case TGSI_OPCODE_MIN:
1706 case TGSI_OPCODE_IMAX:
1707 case TGSI_OPCODE_IMIN:
1708 case TGSI_OPCODE_UMAX:
1709 case TGSI_OPCODE_UMIN:
1710 case TGSI_OPCODE_MOD:
1711 case TGSI_OPCODE_UMOD:
1712 case TGSI_OPCODE_MUL:
1713 case TGSI_OPCODE_UMUL:
1714 case TGSI_OPCODE_OR:
1715 case TGSI_OPCODE_POW:
1716 case TGSI_OPCODE_SHL:
1717 case TGSI_OPCODE_ISHR:
1718 case TGSI_OPCODE_USHR:
1719 case TGSI_OPCODE_SUB:
1720 case TGSI_OPCODE_XOR:
1721 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1722 src0 = fetchSrc(0, c);
1723 src1 = fetchSrc(1, c);
1724 mkOp2(op, dstTy, dst0[c], src0, src1);
1725 }
1726 break;
1727 case TGSI_OPCODE_MAD:
1728 case TGSI_OPCODE_UMAD:
1729 case TGSI_OPCODE_SAD:
1730 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1731 src0 = fetchSrc(0, c);
1732 src1 = fetchSrc(1, c);
1733 src2 = fetchSrc(2, c);
1734 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1735 }
1736 break;
1737 case TGSI_OPCODE_MOV:
1738 case TGSI_OPCODE_ABS:
1739 case TGSI_OPCODE_CEIL:
1740 case TGSI_OPCODE_FLR:
1741 case TGSI_OPCODE_TRUNC:
1742 case TGSI_OPCODE_RCP:
1743 case TGSI_OPCODE_IABS:
1744 case TGSI_OPCODE_INEG:
1745 case TGSI_OPCODE_NOT:
1746 case TGSI_OPCODE_DDX:
1747 case TGSI_OPCODE_DDY:
1748 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1749 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1750 break;
1751 case TGSI_OPCODE_RSQ:
1752 src0 = fetchSrc(0, 0);
1753 val0 = getScratch();
1754 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1755 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1756 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1757 mkMov(dst0[c], val0);
1758 break;
1759 case TGSI_OPCODE_ARL:
1760 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1761 src0 = fetchSrc(0, c);
1762 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1763 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1764 }
1765 break;
1766 case TGSI_OPCODE_UARL:
1767 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1768 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1769 break;
1770 case TGSI_OPCODE_EX2:
1771 case TGSI_OPCODE_LG2:
1772 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1773 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1774 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1775 break;
1776 case TGSI_OPCODE_COS:
1777 case TGSI_OPCODE_SIN:
1778 val0 = getScratch();
1779 if (mask & 7) {
1780 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1781 mkOp1(op, TYPE_F32, val0, val0);
1782 for (c = 0; c < 3; ++c)
1783 if (dst0[c])
1784 mkMov(dst0[c], val0);
1785 }
1786 if (dst0[3]) {
1787 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1788 mkOp1(op, TYPE_F32, dst0[3], val0);
1789 }
1790 break;
1791 case TGSI_OPCODE_SCS:
1792 if (mask & 3) {
1793 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1794 if (dst0[0])
1795 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1796 if (dst0[1])
1797 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1798 }
1799 if (dst0[2])
1800 loadImm(dst0[2], 0.0f);
1801 if (dst0[3])
1802 loadImm(dst0[3], 1.0f);
1803 break;
1804 case TGSI_OPCODE_EXP:
1805 src0 = fetchSrc(0, 0);
1806 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1807 if (dst0[1])
1808 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1809 if (dst0[0])
1810 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1811 if (dst0[2])
1812 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1813 if (dst0[3])
1814 loadImm(dst0[3], 1.0f);
1815 break;
1816 case TGSI_OPCODE_LOG:
1817 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1818 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1819 if (dst0[0] || dst0[1])
1820 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1821 if (dst0[1]) {
1822 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1823 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1824 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1825 }
1826 if (dst0[3])
1827 loadImm(dst0[3], 1.0f);
1828 break;
1829 case TGSI_OPCODE_DP2:
1830 val0 = buildDot(2);
1831 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1832 mkMov(dst0[c], val0);
1833 break;
1834 case TGSI_OPCODE_DP3:
1835 val0 = buildDot(3);
1836 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1837 mkMov(dst0[c], val0);
1838 break;
1839 case TGSI_OPCODE_DP4:
1840 val0 = buildDot(4);
1841 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1842 mkMov(dst0[c], val0);
1843 break;
1844 case TGSI_OPCODE_DPH:
1845 val0 = buildDot(3);
1846 src1 = fetchSrc(1, 3);
1847 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1848 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1849 mkMov(dst0[c], val0);
1850 break;
1851 case TGSI_OPCODE_DST:
1852 if (dst0[0])
1853 loadImm(dst0[0], 1.0f);
1854 if (dst0[1]) {
1855 src0 = fetchSrc(0, 1);
1856 src1 = fetchSrc(1, 1);
1857 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1858 }
1859 if (dst0[2])
1860 mkMov(dst0[2], fetchSrc(0, 2));
1861 if (dst0[3])
1862 mkMov(dst0[3], fetchSrc(1, 3));
1863 break;
1864 case TGSI_OPCODE_LRP:
1865 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1866 src0 = fetchSrc(0, c);
1867 src1 = fetchSrc(1, c);
1868 src2 = fetchSrc(2, c);
1869 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1870 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1871 }
1872 break;
1873 case TGSI_OPCODE_LIT:
1874 handleLIT(dst0);
1875 break;
1876 case TGSI_OPCODE_XPD:
1877 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1878 if (c < 3) {
1879 val0 = getSSA();
1880 src0 = fetchSrc(1, (c + 1) % 3);
1881 src1 = fetchSrc(0, (c + 2) % 3);
1882 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1883 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1884
1885 src0 = fetchSrc(0, (c + 1) % 3);
1886 src1 = fetchSrc(1, (c + 2) % 3);
1887 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1888 } else {
1889 loadImm(dst0[c], 1.0f);
1890 }
1891 }
1892 break;
1893 case TGSI_OPCODE_SSG:
1894 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1895 src0 = fetchSrc(0, c);
1896 val0 = getScratch();
1897 val1 = getScratch();
1898 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, src0, zero);
1899 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, src0, zero);
1900 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1901 }
1902 break;
1903 case TGSI_OPCODE_UCMP:
1904 case TGSI_OPCODE_CMP:
1905 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1906 src0 = fetchSrc(0, c);
1907 src1 = fetchSrc(1, c);
1908 src2 = fetchSrc(2, c);
1909 if (src1 == src2)
1910 mkMov(dst0[c], src1);
1911 else
1912 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1913 srcTy, dst0[c], src1, src2, src0);
1914 }
1915 break;
1916 case TGSI_OPCODE_FRC:
1917 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1918 src0 = fetchSrc(0, c);
1919 val0 = getScratch();
1920 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1921 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1922 }
1923 break;
1924 case TGSI_OPCODE_ROUND:
1925 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1926 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1927 ->rnd = ROUND_NI;
1928 break;
1929 case TGSI_OPCODE_CLAMP:
1930 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1931 src0 = fetchSrc(0, c);
1932 src1 = fetchSrc(1, c);
1933 src2 = fetchSrc(2, c);
1934 val0 = getScratch();
1935 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1936 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1937 }
1938 break;
1939 case TGSI_OPCODE_SLT:
1940 case TGSI_OPCODE_SGE:
1941 case TGSI_OPCODE_SEQ:
1942 case TGSI_OPCODE_SFL:
1943 case TGSI_OPCODE_SGT:
1944 case TGSI_OPCODE_SLE:
1945 case TGSI_OPCODE_SNE:
1946 case TGSI_OPCODE_STR:
1947 case TGSI_OPCODE_ISGE:
1948 case TGSI_OPCODE_ISLT:
1949 case TGSI_OPCODE_USEQ:
1950 case TGSI_OPCODE_USGE:
1951 case TGSI_OPCODE_USLT:
1952 case TGSI_OPCODE_USNE:
1953 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1954 src0 = fetchSrc(0, c);
1955 src1 = fetchSrc(1, c);
1956 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1957 }
1958 break;
1959 case TGSI_OPCODE_KIL:
1960 val0 = new_LValue(func, FILE_PREDICATE);
1961 for (c = 0; c < 4; ++c) {
1962 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1963 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1964 }
1965 break;
1966 case TGSI_OPCODE_KILP:
1967 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1968 break;
1969 case TGSI_OPCODE_TEX:
1970 case TGSI_OPCODE_TXB:
1971 case TGSI_OPCODE_TXL:
1972 case TGSI_OPCODE_TXP:
1973 // R S L C Dx Dy
1974 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1975 break;
1976 case TGSI_OPCODE_TXD:
1977 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1978 break;
1979 case TGSI_OPCODE_SAMPLE:
1980 case TGSI_OPCODE_SAMPLE_B:
1981 case TGSI_OPCODE_SAMPLE_D:
1982 case TGSI_OPCODE_SAMPLE_L:
1983 case TGSI_OPCODE_SAMPLE_C:
1984 case TGSI_OPCODE_SAMPLE_C_LZ:
1985 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
1986 break;
1987 case TGSI_OPCODE_TXF:
1988 case TGSI_OPCODE_LOAD:
1989 handleTXF(dst0, 1);
1990 break;
1991 case TGSI_OPCODE_TXQ:
1992 case TGSI_OPCODE_RESINFO:
1993 handleTXQ(dst0, TXQ_DIMS);
1994 break;
1995 case TGSI_OPCODE_F2I:
1996 case TGSI_OPCODE_F2U:
1997 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1998 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
1999 break;
2000 case TGSI_OPCODE_I2F:
2001 case TGSI_OPCODE_U2F:
2002 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2003 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2004 break;
2005 case TGSI_OPCODE_EMIT:
2006 case TGSI_OPCODE_ENDPRIM:
2007 // get vertex stream if specified (must be immediate)
2008 src0 = tgsi.srcCount() ?
2009 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2010 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2011 break;
2012 case TGSI_OPCODE_IF:
2013 {
2014 BasicBlock *ifBB = new BasicBlock(func);
2015
2016 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2017 condBBs.push(bb);
2018 joinBBs.push(bb);
2019
2020 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2021
2022 setPosition(ifBB, true);
2023 }
2024 break;
2025 case TGSI_OPCODE_ELSE:
2026 {
2027 BasicBlock *elseBB = new BasicBlock(func);
2028 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2029
2030 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2031 condBBs.push(bb);
2032
2033 forkBB->getExit()->asFlow()->target.bb = elseBB;
2034 if (!bb->isTerminated())
2035 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2036
2037 setPosition(elseBB, true);
2038 }
2039 break;
2040 case TGSI_OPCODE_ENDIF:
2041 {
2042 BasicBlock *convBB = new BasicBlock(func);
2043 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2044 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2045
2046 if (!bb->isTerminated()) {
2047 // we only want join if none of the clauses ended with CONT/BREAK/RET
2048 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2049 insertConvergenceOps(convBB, forkBB);
2050 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2051 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2052 }
2053
2054 if (prevBB->getExit()->op == OP_BRA) {
2055 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2056 prevBB->getExit()->asFlow()->target.bb = convBB;
2057 }
2058 setPosition(convBB, true);
2059 }
2060 break;
2061 case TGSI_OPCODE_BGNLOOP:
2062 {
2063 BasicBlock *lbgnBB = new BasicBlock(func);
2064 BasicBlock *lbrkBB = new BasicBlock(func);
2065
2066 loopBBs.push(lbgnBB);
2067 breakBBs.push(lbrkBB);
2068 if (loopBBs.getSize() > func->loopNestingBound)
2069 func->loopNestingBound++;
2070
2071 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2072
2073 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2074 setPosition(lbgnBB, true);
2075 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2076 }
2077 break;
2078 case TGSI_OPCODE_ENDLOOP:
2079 {
2080 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2081
2082 if (!bb->isTerminated()) {
2083 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2084 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2085 }
2086 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2087 }
2088 break;
2089 case TGSI_OPCODE_BRK:
2090 {
2091 if (bb->isTerminated())
2092 break;
2093 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2094 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2095 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2096 }
2097 break;
2098 case TGSI_OPCODE_CONT:
2099 {
2100 if (bb->isTerminated())
2101 break;
2102 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2103 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2104 contBB->explicitCont = true;
2105 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2106 }
2107 break;
2108 case TGSI_OPCODE_BGNSUB:
2109 {
2110 if (!retIPs.getSize()) {
2111 // end of main function
2112 ip = code->scan.num_instructions - 2; // goto END
2113 return true;
2114 }
2115 BasicBlock *entry = new BasicBlock(func);
2116 BasicBlock *leave = new BasicBlock(func);
2117 entryBBs.push(entry);
2118 leaveBBs.push(leave);
2119 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2120 setPosition(entry, true);
2121 }
2122 return true;
2123 case TGSI_OPCODE_ENDSUB:
2124 {
2125 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2126 entryBBs.pop();
2127 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2128 setPosition(leave, true);
2129 ip = retIPs.pop().u.u;
2130 }
2131 return true;
2132 case TGSI_OPCODE_CAL:
2133 // we don't have function declarations, so inline everything
2134 retIPs.push(ip);
2135 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2136 return true;
2137 case TGSI_OPCODE_RET:
2138 {
2139 if (bb->isTerminated())
2140 return true;
2141 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2142 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2143 if (!isEndOfSubroutine(ip + 1)) {
2144 // insert a PRERET at the entry if this is an early return
2145 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2146 preRet->fixed = 1;
2147 entry->insertHead(preRet);
2148 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2149 }
2150 // everything inlined so RET serves only to wrap up the stack
2151 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2152 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2153 }
2154 break;
2155 case TGSI_OPCODE_END:
2156 {
2157 // attach and generate epilogue code
2158 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2159 entryBBs.pop();
2160 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2161 setPosition(epilogue, true);
2162 if (prog->getType() == Program::TYPE_FRAGMENT)
2163 exportOutputs();
2164 if (info->io.genUserClip > 0)
2165 handleUserClipPlanes();
2166 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2167 }
2168 break;
2169 case TGSI_OPCODE_SWITCH:
2170 case TGSI_OPCODE_CASE:
2171 ERROR("switch/case opcode encountered, should have been lowered\n");
2172 abort();
2173 break;
2174 default:
2175 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2176 assert(0);
2177 break;
2178 }
2179
2180 if (tgsi.dstCount()) {
2181 for (c = 0; c < 4; ++c) {
2182 if (!dst0[c])
2183 continue;
2184 if (dst0[c] != rDst0[c])
2185 mkMov(rDst0[c], dst0[c]);
2186 storeDst(0, c, rDst0[c]);
2187 }
2188 }
2189 vtxBaseValid = 0;
2190
2191 return true;
2192 }
2193
2194 void
2195 Converter::handleUserClipPlanes()
2196 {
2197 Value *res[8];
2198 int i, c;
2199
2200 for (c = 0; c < 4; ++c) {
2201 for (i = 0; i < info->io.genUserClip; ++i) {
2202 Value *ucp;
2203 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2204 i * 16 + c * 4), NULL);
2205 if (c == 0)
2206 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2207 else
2208 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2209 }
2210 }
2211
2212 for (i = 0; i < info->io.genUserClip; ++i)
2213 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2214 }
2215
2216 void
2217 Converter::exportOutputs()
2218 {
2219 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2220 for (unsigned int c = 0; c < 4; ++c) {
2221 if (!oData.exists(i, c))
2222 continue;
2223 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2224 info->out[i].slot[c] * 4);
2225 Value *val = oData.load(i, c, NULL);
2226 if (val)
2227 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2228 }
2229 }
2230 }
2231
2232 Converter::Converter(Program *ir, const tgsi::Source *src)
2233 : code(src),
2234 tgsi(NULL),
2235 tData(this), aData(this), pData(this), oData(this)
2236 {
2237 prog = ir;
2238 info = code->info;
2239
2240 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2241
2242 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2243 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2244 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2245 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2246
2247 lData = NULL;
2248 iData = NULL;
2249
2250 zero = mkImm((uint32_t)0);
2251
2252 vtxBaseValid = 0;
2253 }
2254
2255 Converter::~Converter()
2256 {
2257 if (lData)
2258 delete[] lData;
2259 if (iData)
2260 delete[] iData;
2261 }
2262
2263 bool
2264 Converter::run()
2265 {
2266 BasicBlock *entry = new BasicBlock(prog->main);
2267 BasicBlock *leave = new BasicBlock(prog->main);
2268
2269 if (code->tempArrayCount && !lData) {
2270 uint32_t volume = 0;
2271 lData = new DataArray[code->tempArrayCount];
2272 if (!lData)
2273 return false;
2274 for (int i = 0; i < code->tempArrayCount; ++i) {
2275 int len = code->tempArrays[i].u32 >> 2;
2276 int dim = code->tempArrays[i].u32 & 3;
2277 lData[i].setParent(this);
2278 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2279 volume += (len * dim * 4 + 0xf) & ~0xf;
2280 }
2281 }
2282 if (code->immdArrayCount && !iData) {
2283 uint32_t volume = 0;
2284 iData = new DataArray[code->immdArrayCount];
2285 if (!iData)
2286 return false;
2287 for (int i = 0; i < code->immdArrayCount; ++i) {
2288 int len = code->immdArrays[i].u32 >> 2;
2289 int dim = code->immdArrays[i].u32 & 3;
2290 iData[i].setParent(this);
2291 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2292 volume += (len * dim * 4 + 0xf) & ~0xf;
2293 }
2294 }
2295
2296 prog->main->setEntry(entry);
2297 prog->main->setExit(leave);
2298
2299 setPosition(entry, true);
2300 entryBBs.push(entry);
2301 leaveBBs.push(leave);
2302
2303 if (info->io.genUserClip > 0) {
2304 for (int c = 0; c < 4; ++c)
2305 clipVtx[c] = getScratch();
2306 }
2307
2308 if (prog->getType() == Program::TYPE_FRAGMENT) {
2309 Symbol *sv = mkSysVal(SV_POSITION, 3);
2310 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2311 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2312 }
2313
2314 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2315 if (!handleInstruction(&code->insns[ip]))
2316 return false;
2317 }
2318 return true;
2319 }
2320
2321 } // unnamed namespace
2322
2323 namespace nv50_ir {
2324
2325 bool
2326 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2327 {
2328 tgsi::Source src(info);
2329 if (!src.scanSource())
2330 return false;
2331
2332 Converter builder(this, &src);
2333 return builder.run();
2334 }
2335
2336 } // namespace nv50_ir