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nvc0: add support for GF119 (NVD9)
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 default:
325 assert(0);
326 return nv50_ir::SV_CLOCK;
327 }
328 }
329
330 #define NV50_IR_TEX_TARG_CASE(a, b) \
331 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
332
333 static nv50_ir::TexTarget translateTexture(uint tex)
334 {
335 switch (tex) {
336 NV50_IR_TEX_TARG_CASE(1D, 1D);
337 NV50_IR_TEX_TARG_CASE(2D, 2D);
338 NV50_IR_TEX_TARG_CASE(3D, 3D);
339 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
340 NV50_IR_TEX_TARG_CASE(RECT, RECT);
341 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
342 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
344 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
348
349 case TGSI_TEXTURE_UNKNOWN:
350 default:
351 assert(!"invalid texture target");
352 return nv50_ir::TEX_TARGET_2D;
353 }
354 }
355
356 nv50_ir::DataType Instruction::inferSrcType() const
357 {
358 switch (getOpcode()) {
359 case TGSI_OPCODE_AND:
360 case TGSI_OPCODE_OR:
361 case TGSI_OPCODE_XOR:
362 case TGSI_OPCODE_U2F:
363 case TGSI_OPCODE_UADD:
364 case TGSI_OPCODE_UDIV:
365 case TGSI_OPCODE_UMOD:
366 case TGSI_OPCODE_UMAD:
367 case TGSI_OPCODE_UMUL:
368 case TGSI_OPCODE_UMAX:
369 case TGSI_OPCODE_UMIN:
370 case TGSI_OPCODE_USEQ:
371 case TGSI_OPCODE_USGE:
372 case TGSI_OPCODE_USLT:
373 case TGSI_OPCODE_USNE:
374 case TGSI_OPCODE_USHR:
375 case TGSI_OPCODE_UCMP:
376 return nv50_ir::TYPE_U32;
377 case TGSI_OPCODE_I2F:
378 case TGSI_OPCODE_IDIV:
379 case TGSI_OPCODE_IMAX:
380 case TGSI_OPCODE_IMIN:
381 case TGSI_OPCODE_INEG:
382 case TGSI_OPCODE_ISGE:
383 case TGSI_OPCODE_ISHR:
384 case TGSI_OPCODE_ISLT:
385 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
386 case TGSI_OPCODE_MOD:
387 case TGSI_OPCODE_UARL:
388 return nv50_ir::TYPE_S32;
389 default:
390 return nv50_ir::TYPE_F32;
391 }
392 }
393
394 nv50_ir::DataType Instruction::inferDstType() const
395 {
396 switch (getOpcode()) {
397 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
398 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
399 case TGSI_OPCODE_I2F:
400 case TGSI_OPCODE_U2F:
401 return nv50_ir::TYPE_F32;
402 default:
403 return inferSrcType();
404 }
405 }
406
407 nv50_ir::CondCode Instruction::getSetCond() const
408 {
409 using namespace nv50_ir;
410
411 switch (getOpcode()) {
412 case TGSI_OPCODE_SLT:
413 case TGSI_OPCODE_ISLT:
414 case TGSI_OPCODE_USLT:
415 return CC_LT;
416 case TGSI_OPCODE_SLE:
417 return CC_LE;
418 case TGSI_OPCODE_SGE:
419 case TGSI_OPCODE_ISGE:
420 case TGSI_OPCODE_USGE:
421 return CC_GE;
422 case TGSI_OPCODE_SGT:
423 return CC_GT;
424 case TGSI_OPCODE_SEQ:
425 case TGSI_OPCODE_USEQ:
426 return CC_EQ;
427 case TGSI_OPCODE_SNE:
428 case TGSI_OPCODE_USNE:
429 return CC_NE;
430 case TGSI_OPCODE_SFL:
431 return CC_NEVER;
432 case TGSI_OPCODE_STR:
433 default:
434 return CC_ALWAYS;
435 }
436 }
437
438 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
439
440 static nv50_ir::operation translateOpcode(uint opcode)
441 {
442 switch (opcode) {
443 NV50_IR_OPCODE_CASE(ARL, SHL);
444 NV50_IR_OPCODE_CASE(MOV, MOV);
445
446 NV50_IR_OPCODE_CASE(RCP, RCP);
447 NV50_IR_OPCODE_CASE(RSQ, RSQ);
448
449 NV50_IR_OPCODE_CASE(MUL, MUL);
450 NV50_IR_OPCODE_CASE(ADD, ADD);
451
452 NV50_IR_OPCODE_CASE(MIN, MIN);
453 NV50_IR_OPCODE_CASE(MAX, MAX);
454 NV50_IR_OPCODE_CASE(SLT, SET);
455 NV50_IR_OPCODE_CASE(SGE, SET);
456 NV50_IR_OPCODE_CASE(MAD, MAD);
457 NV50_IR_OPCODE_CASE(SUB, SUB);
458
459 NV50_IR_OPCODE_CASE(FLR, FLOOR);
460 NV50_IR_OPCODE_CASE(ROUND, CVT);
461 NV50_IR_OPCODE_CASE(EX2, EX2);
462 NV50_IR_OPCODE_CASE(LG2, LG2);
463 NV50_IR_OPCODE_CASE(POW, POW);
464
465 NV50_IR_OPCODE_CASE(ABS, ABS);
466
467 NV50_IR_OPCODE_CASE(COS, COS);
468 NV50_IR_OPCODE_CASE(DDX, DFDX);
469 NV50_IR_OPCODE_CASE(DDY, DFDY);
470 NV50_IR_OPCODE_CASE(KILP, DISCARD);
471
472 NV50_IR_OPCODE_CASE(SEQ, SET);
473 NV50_IR_OPCODE_CASE(SFL, SET);
474 NV50_IR_OPCODE_CASE(SGT, SET);
475 NV50_IR_OPCODE_CASE(SIN, SIN);
476 NV50_IR_OPCODE_CASE(SLE, SET);
477 NV50_IR_OPCODE_CASE(SNE, SET);
478 NV50_IR_OPCODE_CASE(STR, SET);
479 NV50_IR_OPCODE_CASE(TEX, TEX);
480 NV50_IR_OPCODE_CASE(TXD, TXD);
481 NV50_IR_OPCODE_CASE(TXP, TEX);
482
483 NV50_IR_OPCODE_CASE(BRA, BRA);
484 NV50_IR_OPCODE_CASE(CAL, CALL);
485 NV50_IR_OPCODE_CASE(RET, RET);
486 NV50_IR_OPCODE_CASE(CMP, SLCT);
487
488 NV50_IR_OPCODE_CASE(TXB, TXB);
489
490 NV50_IR_OPCODE_CASE(DIV, DIV);
491
492 NV50_IR_OPCODE_CASE(TXL, TXL);
493
494 NV50_IR_OPCODE_CASE(CEIL, CEIL);
495 NV50_IR_OPCODE_CASE(I2F, CVT);
496 NV50_IR_OPCODE_CASE(NOT, NOT);
497 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
498 NV50_IR_OPCODE_CASE(SHL, SHL);
499
500 NV50_IR_OPCODE_CASE(AND, AND);
501 NV50_IR_OPCODE_CASE(OR, OR);
502 NV50_IR_OPCODE_CASE(MOD, MOD);
503 NV50_IR_OPCODE_CASE(XOR, XOR);
504 NV50_IR_OPCODE_CASE(SAD, SAD);
505 NV50_IR_OPCODE_CASE(TXF, TXF);
506 NV50_IR_OPCODE_CASE(TXQ, TXQ);
507
508 NV50_IR_OPCODE_CASE(EMIT, EMIT);
509 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
510
511 NV50_IR_OPCODE_CASE(KIL, DISCARD);
512
513 NV50_IR_OPCODE_CASE(F2I, CVT);
514 NV50_IR_OPCODE_CASE(IDIV, DIV);
515 NV50_IR_OPCODE_CASE(IMAX, MAX);
516 NV50_IR_OPCODE_CASE(IMIN, MIN);
517 NV50_IR_OPCODE_CASE(INEG, NEG);
518 NV50_IR_OPCODE_CASE(ISGE, SET);
519 NV50_IR_OPCODE_CASE(ISHR, SHR);
520 NV50_IR_OPCODE_CASE(ISLT, SET);
521 NV50_IR_OPCODE_CASE(F2U, CVT);
522 NV50_IR_OPCODE_CASE(U2F, CVT);
523 NV50_IR_OPCODE_CASE(UADD, ADD);
524 NV50_IR_OPCODE_CASE(UDIV, DIV);
525 NV50_IR_OPCODE_CASE(UMAD, MAD);
526 NV50_IR_OPCODE_CASE(UMAX, MAX);
527 NV50_IR_OPCODE_CASE(UMIN, MIN);
528 NV50_IR_OPCODE_CASE(UMOD, MOD);
529 NV50_IR_OPCODE_CASE(UMUL, MUL);
530 NV50_IR_OPCODE_CASE(USEQ, SET);
531 NV50_IR_OPCODE_CASE(USGE, SET);
532 NV50_IR_OPCODE_CASE(USHR, SHR);
533 NV50_IR_OPCODE_CASE(USLT, SET);
534 NV50_IR_OPCODE_CASE(USNE, SET);
535
536 NV50_IR_OPCODE_CASE(LOAD, TXF);
537 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
538 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
539 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
540 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
541 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
542 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
543 NV50_IR_OPCODE_CASE(GATHER4, TXG);
544 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
545
546 NV50_IR_OPCODE_CASE(END, EXIT);
547
548 default:
549 return nv50_ir::OP_NOP;
550 }
551 }
552
553 bool Instruction::checkDstSrcAliasing() const
554 {
555 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
556 return false;
557
558 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
559 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
560 break;
561 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
562 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
563 return true;
564 }
565 return false;
566 }
567
568 class Source
569 {
570 public:
571 Source(struct nv50_ir_prog_info *);
572 ~Source();
573
574 struct Subroutine
575 {
576 unsigned pc;
577 };
578
579 public:
580 bool scanSource();
581 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
582
583 public:
584 struct tgsi_shader_info scan;
585 struct tgsi_full_instruction *insns;
586 const struct tgsi_token *tokens;
587 struct nv50_ir_prog_info *info;
588
589 nv50_ir::DynArray tempArrays;
590 nv50_ir::DynArray immdArrays;
591 int tempArrayCount;
592 int immdArrayCount;
593
594 bool mainTempsInLMem;
595
596 uint8_t *resourceTargets; // TGSI_TEXTURE_*
597 unsigned resourceCount;
598
599 Subroutine *subroutines;
600 unsigned subroutineCount;
601
602 private:
603 int inferSysValDirection(unsigned sn) const;
604 bool scanDeclaration(const struct tgsi_full_declaration *);
605 bool scanInstruction(const struct tgsi_full_instruction *);
606 void scanProperty(const struct tgsi_full_property *);
607 void scanImmediate(const struct tgsi_full_immediate *);
608
609 inline bool isEdgeFlagPassthrough(const Instruction&) const;
610 };
611
612 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
613 {
614 tokens = (const struct tgsi_token *)info->bin.source;
615
616 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
617 tgsi_dump(tokens, 0);
618
619 resourceTargets = NULL;
620 subroutines = NULL;
621
622 mainTempsInLMem = FALSE;
623 }
624
625 Source::~Source()
626 {
627 if (insns)
628 FREE(insns);
629
630 if (info->immd.data)
631 FREE(info->immd.data);
632 if (info->immd.type)
633 FREE(info->immd.type);
634
635 if (resourceTargets)
636 delete[] resourceTargets;
637 if (subroutines)
638 delete[] subroutines;
639 }
640
641 bool Source::scanSource()
642 {
643 unsigned insnCount = 0;
644 unsigned subrCount = 0;
645 struct tgsi_parse_context parse;
646
647 tgsi_scan_shader(tokens, &scan);
648
649 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
650 sizeof(insns[0]));
651 if (!insns)
652 return false;
653
654 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
655 resourceTargets = new uint8_t[resourceCount];
656
657 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
658 subroutines = new Subroutine[subroutineCount];
659
660 info->immd.bufSize = 0;
661 tempArrayCount = 0;
662 immdArrayCount = 0;
663
664 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
665 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
666 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
667
668 if (info->type == PIPE_SHADER_FRAGMENT) {
669 info->prop.fp.writesDepth = scan.writes_z;
670 info->prop.fp.usesDiscard = scan.uses_kill;
671 } else
672 if (info->type == PIPE_SHADER_GEOMETRY) {
673 info->prop.gp.instanceCount = 1; // default value
674 }
675
676 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
677 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
678
679 tgsi_parse_init(&parse, tokens);
680 while (!tgsi_parse_end_of_tokens(&parse)) {
681 tgsi_parse_token(&parse);
682
683 switch (parse.FullToken.Token.Type) {
684 case TGSI_TOKEN_TYPE_IMMEDIATE:
685 scanImmediate(&parse.FullToken.FullImmediate);
686 break;
687 case TGSI_TOKEN_TYPE_DECLARATION:
688 scanDeclaration(&parse.FullToken.FullDeclaration);
689 break;
690 case TGSI_TOKEN_TYPE_INSTRUCTION:
691 insns[insnCount++] = parse.FullToken.FullInstruction;
692 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
693 subroutines[++subrCount].pc = insnCount - 1;
694 else
695 scanInstruction(&parse.FullToken.FullInstruction);
696 break;
697 case TGSI_TOKEN_TYPE_PROPERTY:
698 scanProperty(&parse.FullToken.FullProperty);
699 break;
700 default:
701 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
702 break;
703 }
704 }
705 tgsi_parse_free(&parse);
706
707 if (mainTempsInLMem)
708 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
709
710 return info->assignSlots(info) == 0;
711 }
712
713 void Source::scanProperty(const struct tgsi_full_property *prop)
714 {
715 switch (prop->Property.PropertyName) {
716 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
717 info->prop.gp.outputPrim = prop->u[0].Data;
718 break;
719 case TGSI_PROPERTY_GS_INPUT_PRIM:
720 info->prop.gp.inputPrim = prop->u[0].Data;
721 break;
722 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
723 info->prop.gp.maxVertices = prop->u[0].Data;
724 break;
725 #if 0
726 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
727 info->prop.gp.instanceCount = prop->u[0].Data;
728 break;
729 #endif
730 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
731 info->prop.fp.separateFragData = TRUE;
732 break;
733 case TGSI_PROPERTY_FS_COORD_ORIGIN:
734 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
735 // we don't care
736 break;
737 default:
738 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
739 break;
740 }
741 }
742
743 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
744 {
745 const unsigned n = info->immd.count++;
746
747 assert(n < scan.immediate_count);
748
749 for (int c = 0; c < 4; ++c)
750 info->immd.data[n * 4 + c] = imm->u[c].Uint;
751
752 info->immd.type[n] = imm->Immediate.DataType;
753 }
754
755 int Source::inferSysValDirection(unsigned sn) const
756 {
757 switch (sn) {
758 case TGSI_SEMANTIC_INSTANCEID:
759 // case TGSI_SEMANTIC_VERTEXID:
760 return 1;
761 #if 0
762 case TGSI_SEMANTIC_LAYER:
763 case TGSI_SEMANTIC_VIEWPORTINDEX:
764 return 0;
765 #endif
766 case TGSI_SEMANTIC_PRIMID:
767 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
768 default:
769 return 0;
770 }
771 }
772
773 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
774 {
775 unsigned i;
776 unsigned sn = TGSI_SEMANTIC_GENERIC;
777 unsigned si = 0;
778 const unsigned first = decl->Range.First, last = decl->Range.Last;
779
780 if (decl->Declaration.Semantic) {
781 sn = decl->Semantic.Name;
782 si = decl->Semantic.Index;
783 }
784
785 switch (decl->Declaration.File) {
786 case TGSI_FILE_INPUT:
787 if (info->type == PIPE_SHADER_VERTEX) {
788 // all vertex attributes are equal
789 for (i = first; i <= last; ++i) {
790 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
791 info->in[i].si = i;
792 }
793 } else {
794 for (i = first; i <= last; ++i, ++si) {
795 info->in[i].id = i;
796 info->in[i].sn = sn;
797 info->in[i].si = si;
798 if (info->type == PIPE_SHADER_FRAGMENT) {
799 // translate interpolation mode
800 switch (decl->Declaration.Interpolate) {
801 case TGSI_INTERPOLATE_CONSTANT:
802 info->in[i].flat = 1;
803 break;
804 case TGSI_INTERPOLATE_LINEAR:
805 if (sn != TGSI_SEMANTIC_COLOR) // GL_NICEST
806 info->in[i].linear = 1;
807 break;
808 default:
809 break;
810 }
811 if (decl->Declaration.Centroid)
812 info->in[i].centroid = 1;
813 }
814 }
815 }
816 break;
817 case TGSI_FILE_OUTPUT:
818 for (i = first; i <= last; ++i, ++si) {
819 switch (sn) {
820 case TGSI_SEMANTIC_POSITION:
821 if (info->type == PIPE_SHADER_FRAGMENT)
822 info->io.fragDepth = i;
823 break;
824 case TGSI_SEMANTIC_COLOR:
825 if (info->type == PIPE_SHADER_FRAGMENT)
826 info->prop.fp.numColourResults++;
827 break;
828 case TGSI_SEMANTIC_EDGEFLAG:
829 info->io.edgeFlagOut = i;
830 break;
831 default:
832 break;
833 }
834 info->out[i].id = i;
835 info->out[i].sn = sn;
836 info->out[i].si = si;
837 }
838 break;
839 case TGSI_FILE_SYSTEM_VALUE:
840 for (i = first; i <= last; ++i, ++si) {
841 info->sv[i].sn = sn;
842 info->sv[i].si = si;
843 info->sv[i].input = inferSysValDirection(sn);
844 }
845 break;
846 case TGSI_FILE_RESOURCE:
847 for (i = first; i <= last; ++i)
848 resourceTargets[i] = decl->Resource.Resource;
849 break;
850 case TGSI_FILE_IMMEDIATE_ARRAY:
851 {
852 if (decl->Dim.Index2D >= immdArrayCount)
853 immdArrayCount = decl->Dim.Index2D + 1;
854 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
855 int c;
856 uint32_t base, count;
857 switch (decl->Declaration.UsageMask) {
858 case 0x1: c = 1; break;
859 case 0x3: c = 2; break;
860 default:
861 c = 4;
862 break;
863 }
864 immdArrays[decl->Dim.Index2D].u32 |= c;
865 count = (last + 1) * c;
866 base = info->immd.bufSize / 4;
867 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
868 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
869 info->immd.bufSize);
870 // NOTE: this assumes array declarations are ordered by Dim.Index2D
871 for (i = 0; i < count; ++i)
872 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
873 }
874 break;
875 case TGSI_FILE_TEMPORARY_ARRAY:
876 {
877 if (decl->Dim.Index2D >= tempArrayCount)
878 tempArrayCount = decl->Dim.Index2D + 1;
879 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
880 int c;
881 uint32_t count;
882 switch (decl->Declaration.UsageMask) {
883 case 0x1: c = 1; break;
884 case 0x3: c = 2; break;
885 default:
886 c = 4;
887 break;
888 }
889 tempArrays[decl->Dim.Index2D].u32 |= c;
890 count = (last + 1) * c;
891 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
892 }
893 break;
894 case TGSI_FILE_NULL:
895 case TGSI_FILE_TEMPORARY:
896 case TGSI_FILE_ADDRESS:
897 case TGSI_FILE_CONSTANT:
898 case TGSI_FILE_IMMEDIATE:
899 case TGSI_FILE_PREDICATE:
900 case TGSI_FILE_SAMPLER:
901 break;
902 default:
903 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
904 return false;
905 }
906 return true;
907 }
908
909 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
910 {
911 return insn.getOpcode() == TGSI_OPCODE_MOV &&
912 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
913 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
914 }
915
916 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
917 {
918 Instruction insn(inst);
919
920 if (insn.dstCount()) {
921 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
922 Instruction::DstRegister dst = insn.getDst(0);
923
924 if (dst.isIndirect(0))
925 for (unsigned i = 0; i < info->numOutputs; ++i)
926 info->out[i].mask = 0xf;
927 else
928 info->out[dst.getIndex(0)].mask |= dst.getMask();
929
930 if (isEdgeFlagPassthrough(insn))
931 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
932 } else
933 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
934 if (insn.getDst(0).isIndirect(0))
935 mainTempsInLMem = TRUE;
936 }
937 }
938
939 for (unsigned s = 0; s < insn.srcCount(); ++s) {
940 Instruction::SrcRegister src = insn.getSrc(s);
941 if (src.getFile() == TGSI_FILE_TEMPORARY)
942 if (src.isIndirect(0))
943 mainTempsInLMem = TRUE;
944 if (src.getFile() != TGSI_FILE_INPUT)
945 continue;
946 unsigned mask = insn.srcMask(s);
947
948 if (src.isIndirect(0)) {
949 for (unsigned i = 0; i < info->numInputs; ++i)
950 info->in[i].mask = 0xf;
951 } else {
952 for (unsigned c = 0; c < 4; ++c) {
953 if (!(mask & (1 << c)))
954 continue;
955 int k = src.getSwizzle(c);
956 int i = src.getIndex(0);
957 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
958 if (k <= TGSI_SWIZZLE_W)
959 info->in[i].mask |= 1 << k;
960 }
961 }
962 }
963 return true;
964 }
965
966 nv50_ir::TexInstruction::Target
967 Instruction::getTexture(const tgsi::Source *code, int s) const
968 {
969 if (insn->Instruction.Texture) {
970 return translateTexture(insn->Texture.Texture);
971 } else {
972 // XXX: indirect access
973 unsigned int r = getSrc(s).getIndex(0);
974 assert(r < code->resourceCount);
975 return translateTexture(code->resourceTargets[r]);
976 }
977 }
978
979 } // namespace tgsi
980
981 namespace {
982
983 using namespace nv50_ir;
984
985 class Converter : public BuildUtil
986 {
987 public:
988 Converter(Program *, const tgsi::Source *);
989 ~Converter();
990
991 bool run();
992
993 private:
994 Value *getVertexBase(int s);
995 Value *fetchSrc(int s, int c);
996 Value *acquireDst(int d, int c);
997 void storeDst(int d, int c, Value *);
998
999 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1000 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1001 Value *val, Value *ptr);
1002
1003 Value *applySrcMod(Value *, int s, int c);
1004
1005 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1006 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1007 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1008
1009 bool handleInstruction(const struct tgsi_full_instruction *);
1010 void exportOutputs();
1011 inline bool isEndOfSubroutine(uint ip);
1012
1013 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1014
1015 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1016 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1017 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1018 void handleTXF(Value *dst0[4], int R);
1019 void handleTXQ(Value *dst0[4], enum TexQuery);
1020 void handleLIT(Value *dst0[4]);
1021 void handleUserClipPlanes();
1022
1023 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1024
1025 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1026
1027 Value *buildDot(int dim);
1028
1029 private:
1030 const struct tgsi::Source *code;
1031 const struct nv50_ir_prog_info *info;
1032
1033 uint ip; // instruction pointer
1034
1035 tgsi::Instruction tgsi;
1036
1037 DataType dstTy;
1038 DataType srcTy;
1039
1040 DataArray tData; // TGSI_FILE_TEMPORARY
1041 DataArray aData; // TGSI_FILE_ADDRESS
1042 DataArray pData; // TGSI_FILE_PREDICATE
1043 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1044 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1045 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1046
1047 Value *zero;
1048 Value *fragCoord[4];
1049 Value *clipVtx[4];
1050
1051 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1052 uint8_t vtxBaseValid;
1053
1054 Stack condBBs; // fork BB, then else clause BB
1055 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1056 Stack loopBBs; // loop headers
1057 Stack breakBBs; // end of / after loop
1058 Stack entryBBs; // start of current (inlined) subroutine
1059 Stack leaveBBs; // end of current (inlined) subroutine
1060 Stack retIPs; // return instruction pointer
1061 };
1062
1063 Symbol *
1064 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1065 {
1066 const int swz = src.getSwizzle(c);
1067
1068 return makeSym(src.getFile(),
1069 src.is2D() ? src.getIndex(1) : 0,
1070 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1071 src.getIndex(0) * 16 + swz * 4);
1072 }
1073
1074 Symbol *
1075 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1076 {
1077 return makeSym(dst.getFile(),
1078 dst.is2D() ? dst.getIndex(1) : 0,
1079 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1080 dst.getIndex(0) * 16 + c * 4);
1081 }
1082
1083 Symbol *
1084 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1085 {
1086 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1087
1088 sym->reg.fileIndex = fileIdx;
1089
1090 if (idx >= 0) {
1091 if (sym->reg.file == FILE_SHADER_INPUT)
1092 sym->setOffset(info->in[idx].slot[c] * 4);
1093 else
1094 if (sym->reg.file == FILE_SHADER_OUTPUT)
1095 sym->setOffset(info->out[idx].slot[c] * 4);
1096 else
1097 if (sym->reg.file == FILE_SYSTEM_VALUE)
1098 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1099 else
1100 sym->setOffset(address);
1101 } else {
1102 sym->setOffset(address);
1103 }
1104 return sym;
1105 }
1106
1107 static inline uint8_t
1108 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1109 {
1110 uint8_t mode;
1111
1112 if (var->flat)
1113 mode = NV50_IR_INTERP_FLAT;
1114 else
1115 if (var->linear)
1116 mode = NV50_IR_INTERP_LINEAR;
1117 else
1118 mode = NV50_IR_INTERP_PERSPECTIVE;
1119
1120 op = (mode == NV50_IR_INTERP_PERSPECTIVE) ? OP_PINTERP : OP_LINTERP;
1121
1122 if (var->centroid)
1123 mode |= NV50_IR_INTERP_CENTROID;
1124
1125 return mode;
1126 }
1127
1128 Value *
1129 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1130 {
1131 operation op;
1132
1133 // XXX: no way to know interpolation mode if we don't know what's accessed
1134 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1135 src.getIndex(0)], op);
1136
1137 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1138
1139 insn->setDef(0, getScratch());
1140 insn->setSrc(0, srcToSym(src, c));
1141 if (op == OP_PINTERP)
1142 insn->setSrc(1, fragCoord[3]);
1143 if (ptr)
1144 insn->setIndirect(0, 0, ptr);
1145
1146 insn->setInterpolate(mode);
1147
1148 bb->insertTail(insn);
1149 return insn->getDef(0);
1150 }
1151
1152 Value *
1153 Converter::applySrcMod(Value *val, int s, int c)
1154 {
1155 Modifier m = tgsi.getSrc(s).getMod(c);
1156 DataType ty = tgsi.inferSrcType();
1157
1158 if (m & Modifier(NV50_IR_MOD_ABS))
1159 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1160
1161 if (m & Modifier(NV50_IR_MOD_NEG))
1162 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1163
1164 return val;
1165 }
1166
1167 Value *
1168 Converter::getVertexBase(int s)
1169 {
1170 assert(s < 5);
1171 if (!(vtxBaseValid & (1 << s))) {
1172 const int index = tgsi.getSrc(s).getIndex(1);
1173 Value *rel = NULL;
1174 if (tgsi.getSrc(s).isIndirect(1))
1175 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1176 vtxBaseValid |= 1 << s;
1177 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1178 }
1179 return vtxBase[s];
1180 }
1181
1182 Value *
1183 Converter::fetchSrc(int s, int c)
1184 {
1185 Value *res;
1186 Value *ptr = NULL, *dimRel = NULL;
1187
1188 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1189
1190 if (src.isIndirect(0))
1191 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1192
1193 if (src.is2D()) {
1194 switch (src.getFile()) {
1195 case TGSI_FILE_INPUT:
1196 dimRel = getVertexBase(s);
1197 break;
1198 case TGSI_FILE_CONSTANT:
1199 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1200 if (src.isIndirect(1))
1201 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1202 break;
1203 default:
1204 break;
1205 }
1206 }
1207
1208 res = fetchSrc(src, c, ptr);
1209
1210 if (dimRel)
1211 res->getInsn()->setIndirect(0, 1, dimRel);
1212
1213 return applySrcMod(res, s, c);
1214 }
1215
1216 Value *
1217 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1218 {
1219 const int idx = src.getIndex(0);
1220 const int swz = src.getSwizzle(c);
1221
1222 switch (src.getFile()) {
1223 case TGSI_FILE_TEMPORARY:
1224 return tData.load(idx, swz, ptr);
1225 case TGSI_FILE_PREDICATE:
1226 return pData.load(idx, swz, ptr);
1227 case TGSI_FILE_ADDRESS:
1228 return aData.load(idx, swz, ptr);
1229
1230 case TGSI_FILE_TEMPORARY_ARRAY:
1231 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1232 return lData[src.getIndex(1)].load(idx, swz, ptr);
1233 case TGSI_FILE_IMMEDIATE_ARRAY:
1234 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1235 return iData[src.getIndex(1)].load(idx, swz, ptr);
1236
1237 case TGSI_FILE_IMMEDIATE:
1238 assert(!ptr);
1239 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1240
1241 case TGSI_FILE_CONSTANT:
1242 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1243
1244 case TGSI_FILE_INPUT:
1245 if (prog->getType() == Program::TYPE_FRAGMENT) {
1246 // don't load masked inputs, won't be assigned a slot
1247 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1248 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1249 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1250 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1251 return interpolate(src, c, ptr);
1252 }
1253 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1254
1255 case TGSI_FILE_SYSTEM_VALUE:
1256 assert(!ptr);
1257 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1258
1259 case TGSI_FILE_OUTPUT:
1260 case TGSI_FILE_RESOURCE:
1261 case TGSI_FILE_SAMPLER:
1262 case TGSI_FILE_NULL:
1263 default:
1264 assert(!"invalid/unhandled TGSI source file");
1265 return NULL;
1266 }
1267 }
1268
1269 Value *
1270 Converter::acquireDst(int d, int c)
1271 {
1272 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1273
1274 if (dst.isMasked(c))
1275 return NULL;
1276 if (dst.isIndirect(0))
1277 return getScratch();
1278
1279 const int idx = dst.getIndex(0);
1280
1281 switch (dst.getFile()) {
1282 case TGSI_FILE_TEMPORARY:
1283 return tData.acquire(idx, c);
1284 case TGSI_FILE_TEMPORARY_ARRAY:
1285 return getScratch();
1286 case TGSI_FILE_PREDICATE:
1287 return pData.acquire(idx, c);
1288 case TGSI_FILE_ADDRESS:
1289 return aData.acquire(idx, c);
1290
1291 case TGSI_FILE_OUTPUT:
1292 if (prog->getType() == Program::TYPE_FRAGMENT)
1293 return oData.acquire(idx, c);
1294 // fall through
1295 case TGSI_FILE_SYSTEM_VALUE:
1296 return getScratch();
1297
1298 default:
1299 assert(!"invalid dst file");
1300 return NULL;
1301 }
1302 }
1303
1304 void
1305 Converter::storeDst(int d, int c, Value *val)
1306 {
1307 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1308
1309 switch (tgsi.getSaturate()) {
1310 case TGSI_SAT_NONE:
1311 break;
1312 case TGSI_SAT_ZERO_ONE:
1313 mkOp1(OP_SAT, dstTy, val, val);
1314 break;
1315 case TGSI_SAT_MINUS_PLUS_ONE:
1316 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1317 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1318 break;
1319 default:
1320 assert(!"invalid saturation mode");
1321 break;
1322 }
1323
1324 Value *ptr = dst.isIndirect(0) ?
1325 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1326
1327 if (info->io.clipDistanceCount &&
1328 dst.getFile() == TGSI_FILE_OUTPUT &&
1329 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_POSITION) {
1330 mkMov(clipVtx[c], val);
1331 val = clipVtx[c];
1332 }
1333
1334 storeDst(dst, c, val, ptr);
1335 }
1336
1337 void
1338 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1339 Value *val, Value *ptr)
1340 {
1341 const int idx = dst.getIndex(0);
1342
1343 switch (dst.getFile()) {
1344 case TGSI_FILE_TEMPORARY:
1345 tData.store(idx, c, ptr, val);
1346 break;
1347 case TGSI_FILE_TEMPORARY_ARRAY:
1348 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1349 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1350 break;
1351 case TGSI_FILE_PREDICATE:
1352 pData.store(idx, c, ptr, val);
1353 break;
1354 case TGSI_FILE_ADDRESS:
1355 aData.store(idx, c, ptr, val);
1356 break;
1357
1358 case TGSI_FILE_OUTPUT:
1359 if (prog->getType() == Program::TYPE_FRAGMENT)
1360 oData.store(idx, c, ptr, val);
1361 else
1362 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1363 break;
1364
1365 case TGSI_FILE_SYSTEM_VALUE:
1366 assert(!ptr);
1367 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1368 break;
1369
1370 default:
1371 assert(!"invalid dst file");
1372 break;
1373 }
1374 }
1375
1376 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1377 for (chan = 0; chan < 4; ++chan) \
1378 if (!inst.getDst(d).isMasked(chan))
1379
1380 Value *
1381 Converter::buildDot(int dim)
1382 {
1383 assert(dim > 0);
1384
1385 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1386 Value *dotp = getScratch();
1387
1388 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1389
1390 for (int c = 1; c < dim; ++c) {
1391 src0 = fetchSrc(0, c);
1392 src1 = fetchSrc(1, c);
1393 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1394 }
1395 return dotp;
1396 }
1397
1398 void
1399 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1400 {
1401 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1402 join->fixed = 1;
1403 conv->insertHead(join);
1404
1405 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1406 fork->insertBefore(fork->getExit(), fork->joinAt);
1407 }
1408
1409 void
1410 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1411 {
1412 unsigned rIdx = 0, sIdx = 0;
1413
1414 if (R >= 0)
1415 rIdx = tgsi.getSrc(R).getIndex(0);
1416 if (S >= 0)
1417 sIdx = tgsi.getSrc(S).getIndex(0);
1418
1419 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1420
1421 if (tgsi.getSrc(R).isIndirect(0)) {
1422 tex->tex.rIndirectSrc = s;
1423 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1424 }
1425 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1426 tex->tex.sIndirectSrc = s;
1427 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1428 }
1429 }
1430
1431 void
1432 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1433 {
1434 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1435 tex->tex.query = query;
1436 unsigned int c, d;
1437
1438 for (d = 0, c = 0; c < 4; ++c) {
1439 if (!dst0[c])
1440 continue;
1441 tex->tex.mask |= 1 << c;
1442 tex->setDef(d++, dst0[c]);
1443 }
1444 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1445
1446 setTexRS(tex, c, 1, -1);
1447
1448 bb->insertTail(tex);
1449 }
1450
1451 void
1452 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1453 {
1454 Value *proj = fetchSrc(0, 3);
1455 Instruction *insn = proj->getUniqueInsn();
1456 int c;
1457
1458 if (insn->op == OP_PINTERP) {
1459 bb->insertTail(insn = insn->clone(true));
1460 insn->op = OP_LINTERP;
1461 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1462 insn->setSrc(1, NULL);
1463 proj = insn->getDef(0);
1464 }
1465 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1466
1467 for (c = 0; c < 4; ++c) {
1468 if (!(mask & (1 << c)))
1469 continue;
1470 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1471 continue;
1472 mask &= ~(1 << c);
1473
1474 bb->insertTail(insn = insn->clone(true));
1475 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1476 insn->setSrc(1, proj);
1477 dst[c] = insn->getDef(0);
1478 }
1479 if (!mask)
1480 return;
1481
1482 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1483
1484 for (c = 0; c < 4; ++c)
1485 if (mask & (1 << c))
1486 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1487 }
1488
1489 // order of nv50 ir sources: x y z layer lod/bias shadow
1490 // order of TGSI TEX sources: x y z layer shadow lod/bias
1491 // lowering will finally set the hw specific order (like array first on nvc0)
1492 void
1493 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1494 {
1495 Value *val;
1496 Value *arg[4], *src[8];
1497 Value *lod = NULL, *shd = NULL;
1498 unsigned int s, c, d;
1499 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1500
1501 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1502
1503 for (s = 0; s < tgt.getArgCount(); ++s)
1504 arg[s] = src[s] = fetchSrc(0, s);
1505
1506 if (texi->op == OP_TXL || texi->op == OP_TXB)
1507 lod = fetchSrc(L >> 4, L & 3);
1508
1509 if (C == 0x0f)
1510 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1511
1512 if (tgt.isShadow())
1513 shd = fetchSrc(C >> 4, C & 3);
1514
1515 if (texi->op == OP_TXD) {
1516 for (c = 0; c < tgt.getDim(); ++c) {
1517 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1518 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1519 }
1520 }
1521
1522 // cube textures don't care about projection value, it's divided out
1523 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1524 unsigned int n = tgt.getDim();
1525 if (shd) {
1526 arg[n] = shd;
1527 ++n;
1528 assert(tgt.getDim() == tgt.getArgCount());
1529 }
1530 loadProjTexCoords(src, arg, (1 << n) - 1);
1531 if (shd)
1532 shd = src[n - 1];
1533 }
1534
1535 if (tgt.isCube()) {
1536 for (c = 0; c < 3; ++c)
1537 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1538 val = getScratch();
1539 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1540 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1541 mkOp1(OP_RCP, TYPE_F32, val, val);
1542 for (c = 0; c < 3; ++c)
1543 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1544 }
1545
1546 for (c = 0, d = 0; c < 4; ++c) {
1547 if (dst[c]) {
1548 texi->setDef(d++, dst[c]);
1549 texi->tex.mask |= 1 << c;
1550 } else {
1551 // NOTE: maybe hook up def too, for CSE
1552 }
1553 }
1554 for (s = 0; s < tgt.getArgCount(); ++s)
1555 texi->setSrc(s, src[s]);
1556 if (lod)
1557 texi->setSrc(s++, lod);
1558 if (shd)
1559 texi->setSrc(s++, shd);
1560
1561 setTexRS(texi, s, R, S);
1562
1563 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1564 texi->tex.levelZero = true;
1565
1566 bb->insertTail(texi);
1567 }
1568
1569 // 1st source: xyz = coordinates, w = lod
1570 // 2nd source: offset
1571 void
1572 Converter::handleTXF(Value *dst[4], int R)
1573 {
1574 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1575 unsigned int c, d, s;
1576
1577 texi->tex.target = tgsi.getTexture(code, R);
1578
1579 for (c = 0, d = 0; c < 4; ++c) {
1580 if (dst[c]) {
1581 texi->setDef(d++, dst[c]);
1582 texi->tex.mask |= 1 << c;
1583 }
1584 }
1585 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1586 texi->setSrc(c, fetchSrc(0, c));
1587 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1588
1589 setTexRS(texi, c, R, -1);
1590
1591 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1592 for (c = 0; c < 3; ++c) {
1593 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1594 if (texi->tex.offset[s][c])
1595 texi->tex.useOffsets = s + 1;
1596 }
1597 }
1598
1599 bb->insertTail(texi);
1600 }
1601
1602 void
1603 Converter::handleLIT(Value *dst0[4])
1604 {
1605 Value *val0 = NULL;
1606 unsigned int mask = tgsi.getDst(0).getMask();
1607
1608 if (mask & (1 << 0))
1609 loadImm(dst0[0], 1.0f);
1610
1611 if (mask & (1 << 3))
1612 loadImm(dst0[3], 1.0f);
1613
1614 if (mask & (3 << 1)) {
1615 val0 = getScratch();
1616 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1617 if (mask & (1 << 1))
1618 mkMov(dst0[1], val0);
1619 }
1620
1621 if (mask & (1 << 2)) {
1622 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1623 Value *val1 = getScratch(), *val3 = getScratch();
1624
1625 Value *pos128 = loadImm(NULL, +127.999999f);
1626 Value *neg128 = loadImm(NULL, -127.999999f);
1627
1628 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1629 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1630 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1631 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1632
1633 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1634 }
1635 }
1636
1637 bool
1638 Converter::isEndOfSubroutine(uint ip)
1639 {
1640 assert(ip < code->scan.num_instructions);
1641 tgsi::Instruction insn(&code->insns[ip]);
1642 return (insn.getOpcode() == TGSI_OPCODE_END ||
1643 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1644 // does END occur at end of main or the very end ?
1645 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1646 }
1647
1648 bool
1649 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1650 {
1651 Value *dst0[4], *rDst0[4];
1652 Value *src0, *src1, *src2;
1653 Value *val0, *val1;
1654 int c;
1655
1656 tgsi = tgsi::Instruction(insn);
1657
1658 bool useScratchDst = tgsi.checkDstSrcAliasing();
1659
1660 operation op = tgsi.getOP();
1661 dstTy = tgsi.inferDstType();
1662 srcTy = tgsi.inferSrcType();
1663
1664 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1665
1666 if (tgsi.dstCount()) {
1667 for (c = 0; c < 4; ++c) {
1668 rDst0[c] = acquireDst(0, c);
1669 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1670 }
1671 }
1672
1673 switch (tgsi.getOpcode()) {
1674 case TGSI_OPCODE_ADD:
1675 case TGSI_OPCODE_UADD:
1676 case TGSI_OPCODE_AND:
1677 case TGSI_OPCODE_DIV:
1678 case TGSI_OPCODE_IDIV:
1679 case TGSI_OPCODE_UDIV:
1680 case TGSI_OPCODE_MAX:
1681 case TGSI_OPCODE_MIN:
1682 case TGSI_OPCODE_IMAX:
1683 case TGSI_OPCODE_IMIN:
1684 case TGSI_OPCODE_UMAX:
1685 case TGSI_OPCODE_UMIN:
1686 case TGSI_OPCODE_MOD:
1687 case TGSI_OPCODE_UMOD:
1688 case TGSI_OPCODE_MUL:
1689 case TGSI_OPCODE_UMUL:
1690 case TGSI_OPCODE_OR:
1691 case TGSI_OPCODE_POW:
1692 case TGSI_OPCODE_SHL:
1693 case TGSI_OPCODE_ISHR:
1694 case TGSI_OPCODE_USHR:
1695 case TGSI_OPCODE_SUB:
1696 case TGSI_OPCODE_XOR:
1697 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1698 src0 = fetchSrc(0, c);
1699 src1 = fetchSrc(1, c);
1700 mkOp2(op, dstTy, dst0[c], src0, src1);
1701 }
1702 break;
1703 case TGSI_OPCODE_MAD:
1704 case TGSI_OPCODE_UMAD:
1705 case TGSI_OPCODE_SAD:
1706 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1707 src0 = fetchSrc(0, c);
1708 src1 = fetchSrc(1, c);
1709 src2 = fetchSrc(2, c);
1710 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1711 }
1712 break;
1713 case TGSI_OPCODE_MOV:
1714 case TGSI_OPCODE_ABS:
1715 case TGSI_OPCODE_CEIL:
1716 case TGSI_OPCODE_FLR:
1717 case TGSI_OPCODE_TRUNC:
1718 case TGSI_OPCODE_RCP:
1719 case TGSI_OPCODE_INEG:
1720 case TGSI_OPCODE_NOT:
1721 case TGSI_OPCODE_DDX:
1722 case TGSI_OPCODE_DDY:
1723 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1724 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1725 break;
1726 case TGSI_OPCODE_RSQ:
1727 src0 = fetchSrc(0, 0);
1728 val0 = getScratch();
1729 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1730 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1731 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1732 mkMov(dst0[c], val0);
1733 break;
1734 case TGSI_OPCODE_ARL:
1735 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1736 src0 = fetchSrc(0, c);
1737 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1738 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1739 }
1740 break;
1741 case TGSI_OPCODE_UARL:
1742 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1743 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1744 break;
1745 case TGSI_OPCODE_EX2:
1746 case TGSI_OPCODE_LG2:
1747 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1748 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1749 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1750 break;
1751 case TGSI_OPCODE_COS:
1752 case TGSI_OPCODE_SIN:
1753 val0 = getScratch();
1754 if (mask & 7) {
1755 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1756 mkOp1(op, TYPE_F32, val0, val0);
1757 for (c = 0; c < 3; ++c)
1758 if (dst0[c])
1759 mkMov(dst0[c], val0);
1760 }
1761 if (dst0[3]) {
1762 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1763 mkOp1(op, TYPE_F32, dst0[3], val0);
1764 }
1765 break;
1766 case TGSI_OPCODE_SCS:
1767 if (mask & 3) {
1768 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1769 if (dst0[0])
1770 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1771 if (dst0[1])
1772 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1773 }
1774 if (dst0[2])
1775 loadImm(dst0[2], 0.0f);
1776 if (dst0[3])
1777 loadImm(dst0[3], 1.0f);
1778 break;
1779 case TGSI_OPCODE_EXP:
1780 src0 = fetchSrc(0, 0);
1781 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1782 if (dst0[1])
1783 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1784 if (dst0[0])
1785 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1786 if (dst0[2])
1787 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1788 if (dst0[3])
1789 loadImm(dst0[3], 1.0f);
1790 break;
1791 case TGSI_OPCODE_LOG:
1792 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1793 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1794 if (dst0[0] || dst0[1])
1795 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1796 if (dst0[1]) {
1797 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1798 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1799 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1800 }
1801 if (dst0[3])
1802 loadImm(dst0[3], 1.0f);
1803 break;
1804 case TGSI_OPCODE_DP2:
1805 val0 = buildDot(2);
1806 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1807 mkMov(dst0[c], val0);
1808 break;
1809 case TGSI_OPCODE_DP3:
1810 val0 = buildDot(3);
1811 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1812 mkMov(dst0[c], val0);
1813 break;
1814 case TGSI_OPCODE_DP4:
1815 val0 = buildDot(4);
1816 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1817 mkMov(dst0[c], val0);
1818 break;
1819 case TGSI_OPCODE_DPH:
1820 val0 = buildDot(3);
1821 src1 = fetchSrc(1, 3);
1822 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1823 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1824 mkMov(dst0[c], val0);
1825 break;
1826 case TGSI_OPCODE_DST:
1827 if (dst0[0])
1828 loadImm(dst0[0], 1.0f);
1829 if (dst0[1]) {
1830 src0 = fetchSrc(0, 1);
1831 src1 = fetchSrc(1, 1);
1832 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1833 }
1834 if (dst0[2])
1835 mkMov(dst0[2], fetchSrc(0, 2));
1836 if (dst0[3])
1837 mkMov(dst0[3], fetchSrc(1, 3));
1838 break;
1839 case TGSI_OPCODE_LRP:
1840 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1841 src0 = fetchSrc(0, c);
1842 src1 = fetchSrc(1, c);
1843 src2 = fetchSrc(2, c);
1844 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1845 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1846 }
1847 break;
1848 case TGSI_OPCODE_LIT:
1849 handleLIT(dst0);
1850 break;
1851 case TGSI_OPCODE_XPD:
1852 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1853 if (c < 3) {
1854 val0 = getSSA();
1855 src0 = fetchSrc(1, (c + 1) % 3);
1856 src1 = fetchSrc(0, (c + 2) % 3);
1857 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1858 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1859
1860 src0 = fetchSrc(0, (c + 1) % 3);
1861 src1 = fetchSrc(1, (c + 2) % 3);
1862 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1863 } else {
1864 loadImm(dst0[c], 1.0f);
1865 }
1866 }
1867 break;
1868 case TGSI_OPCODE_SSG:
1869 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1870 src0 = fetchSrc(0, c);
1871 val0 = getScratch();
1872 val1 = getScratch();
1873 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, src0, zero);
1874 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, src0, zero);
1875 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1876 }
1877 break;
1878 case TGSI_OPCODE_UCMP:
1879 case TGSI_OPCODE_CMP:
1880 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1881 src0 = fetchSrc(0, c);
1882 src1 = fetchSrc(1, c);
1883 src2 = fetchSrc(2, c);
1884 if (src1 == src2)
1885 mkMov(dst0[c], src1);
1886 else
1887 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1888 srcTy, dst0[c], src1, src2, src0);
1889 }
1890 break;
1891 case TGSI_OPCODE_FRC:
1892 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1893 src0 = fetchSrc(0, c);
1894 val0 = getScratch();
1895 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1896 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1897 }
1898 break;
1899 case TGSI_OPCODE_ROUND:
1900 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1901 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1902 ->rnd = ROUND_NI;
1903 break;
1904 case TGSI_OPCODE_CLAMP:
1905 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1906 src0 = fetchSrc(0, c);
1907 src1 = fetchSrc(1, c);
1908 src2 = fetchSrc(2, c);
1909 val0 = getScratch();
1910 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1911 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1912 }
1913 break;
1914 case TGSI_OPCODE_SLT:
1915 case TGSI_OPCODE_SGE:
1916 case TGSI_OPCODE_SEQ:
1917 case TGSI_OPCODE_SFL:
1918 case TGSI_OPCODE_SGT:
1919 case TGSI_OPCODE_SLE:
1920 case TGSI_OPCODE_SNE:
1921 case TGSI_OPCODE_STR:
1922 case TGSI_OPCODE_ISGE:
1923 case TGSI_OPCODE_ISLT:
1924 case TGSI_OPCODE_USEQ:
1925 case TGSI_OPCODE_USGE:
1926 case TGSI_OPCODE_USLT:
1927 case TGSI_OPCODE_USNE:
1928 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1929 src0 = fetchSrc(0, c);
1930 src1 = fetchSrc(1, c);
1931 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1932 }
1933 break;
1934 case TGSI_OPCODE_KIL:
1935 val0 = new_LValue(func, FILE_PREDICATE);
1936 for (c = 0; c < 4; ++c) {
1937 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1938 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1939 }
1940 break;
1941 case TGSI_OPCODE_KILP:
1942 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1943 break;
1944 case TGSI_OPCODE_TEX:
1945 case TGSI_OPCODE_TXB:
1946 case TGSI_OPCODE_TXL:
1947 case TGSI_OPCODE_TXP:
1948 // R S L C Dx Dy
1949 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1950 break;
1951 case TGSI_OPCODE_TXD:
1952 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1953 break;
1954 case TGSI_OPCODE_SAMPLE:
1955 case TGSI_OPCODE_SAMPLE_B:
1956 case TGSI_OPCODE_SAMPLE_D:
1957 case TGSI_OPCODE_SAMPLE_L:
1958 case TGSI_OPCODE_SAMPLE_C:
1959 case TGSI_OPCODE_SAMPLE_C_LZ:
1960 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
1961 break;
1962 case TGSI_OPCODE_TXF:
1963 case TGSI_OPCODE_LOAD:
1964 handleTXF(dst0, 1);
1965 break;
1966 case TGSI_OPCODE_TXQ:
1967 case TGSI_OPCODE_RESINFO:
1968 handleTXQ(dst0, TXQ_DIMS);
1969 break;
1970 case TGSI_OPCODE_F2I:
1971 case TGSI_OPCODE_F2U:
1972 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1973 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
1974 break;
1975 case TGSI_OPCODE_I2F:
1976 case TGSI_OPCODE_U2F:
1977 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1978 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
1979 break;
1980 case TGSI_OPCODE_EMIT:
1981 case TGSI_OPCODE_ENDPRIM:
1982 // get vertex stream if specified (must be immediate)
1983 src0 = tgsi.srcCount() ?
1984 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
1985 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
1986 break;
1987 case TGSI_OPCODE_IF:
1988 {
1989 BasicBlock *ifBB = new BasicBlock(func);
1990
1991 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1992 condBBs.push(bb);
1993 joinBBs.push(bb);
1994
1995 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
1996
1997 setPosition(ifBB, true);
1998 }
1999 break;
2000 case TGSI_OPCODE_ELSE:
2001 {
2002 BasicBlock *elseBB = new BasicBlock(func);
2003 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2004
2005 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2006 condBBs.push(bb);
2007
2008 forkBB->getExit()->asFlow()->target.bb = elseBB;
2009 if (!bb->isTerminated())
2010 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2011
2012 setPosition(elseBB, true);
2013 }
2014 break;
2015 case TGSI_OPCODE_ENDIF:
2016 {
2017 BasicBlock *convBB = new BasicBlock(func);
2018 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2019 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2020
2021 if (!bb->isTerminated()) {
2022 // we only want join if none of the clauses ended with CONT/BREAK/RET
2023 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2024 insertConvergenceOps(convBB, forkBB);
2025 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2026 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2027 }
2028
2029 if (prevBB->getExit()->op == OP_BRA) {
2030 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2031 prevBB->getExit()->asFlow()->target.bb = convBB;
2032 }
2033 setPosition(convBB, true);
2034 }
2035 break;
2036 case TGSI_OPCODE_BGNLOOP:
2037 {
2038 BasicBlock *lbgnBB = new BasicBlock(func);
2039 BasicBlock *lbrkBB = new BasicBlock(func);
2040
2041 loopBBs.push(lbgnBB);
2042 breakBBs.push(lbrkBB);
2043 if (loopBBs.getSize() > func->loopNestingBound)
2044 func->loopNestingBound++;
2045
2046 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2047
2048 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2049 setPosition(lbgnBB, true);
2050 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2051 }
2052 break;
2053 case TGSI_OPCODE_ENDLOOP:
2054 {
2055 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2056
2057 if (!bb->isTerminated()) {
2058 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2059 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2060 }
2061 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2062 }
2063 break;
2064 case TGSI_OPCODE_BRK:
2065 {
2066 if (bb->isTerminated())
2067 break;
2068 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2069 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2070 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2071 }
2072 break;
2073 case TGSI_OPCODE_CONT:
2074 {
2075 if (bb->isTerminated())
2076 break;
2077 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2078 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2079 contBB->explicitCont = true;
2080 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2081 }
2082 break;
2083 case TGSI_OPCODE_BGNSUB:
2084 {
2085 if (!retIPs.getSize()) {
2086 // end of main function
2087 ip = code->scan.num_instructions - 2; // goto END
2088 return true;
2089 }
2090 BasicBlock *entry = new BasicBlock(func);
2091 BasicBlock *leave = new BasicBlock(func);
2092 entryBBs.push(entry);
2093 leaveBBs.push(leave);
2094 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2095 setPosition(entry, true);
2096 }
2097 return true;
2098 case TGSI_OPCODE_ENDSUB:
2099 {
2100 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2101 entryBBs.pop();
2102 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2103 setPosition(leave, true);
2104 ip = retIPs.pop().u.u;
2105 }
2106 return true;
2107 case TGSI_OPCODE_CAL:
2108 // we don't have function declarations, so inline everything
2109 retIPs.push(ip);
2110 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2111 return true;
2112 case TGSI_OPCODE_RET:
2113 {
2114 if (bb->isTerminated())
2115 return true;
2116 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2117 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2118 if (!isEndOfSubroutine(ip + 1)) {
2119 // insert a PRERET at the entry if this is an early return
2120 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2121 preRet->fixed = 1;
2122 entry->insertHead(preRet);
2123 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2124 }
2125 // everything inlined so RET serves only to wrap up the stack
2126 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2127 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2128 }
2129 break;
2130 case TGSI_OPCODE_END:
2131 {
2132 // attach and generate epilogue code
2133 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2134 entryBBs.pop();
2135 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2136 setPosition(epilogue, true);
2137 if (prog->getType() == Program::TYPE_FRAGMENT)
2138 exportOutputs();
2139 if (info->io.clipDistanceCount)
2140 handleUserClipPlanes();
2141 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2142 }
2143 break;
2144 case TGSI_OPCODE_SWITCH:
2145 case TGSI_OPCODE_CASE:
2146 ERROR("switch/case opcode encountered, should have been lowered\n");
2147 abort();
2148 break;
2149 default:
2150 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2151 assert(0);
2152 break;
2153 }
2154
2155 if (tgsi.dstCount()) {
2156 for (c = 0; c < 4; ++c) {
2157 if (!dst0[c])
2158 continue;
2159 if (dst0[c] != rDst0[c])
2160 mkMov(rDst0[c], dst0[c]);
2161 storeDst(0, c, rDst0[c]);
2162 }
2163 }
2164 vtxBaseValid = 0;
2165
2166 return true;
2167 }
2168
2169 void
2170 Converter::handleUserClipPlanes()
2171 {
2172 Value *res[8];
2173 int i, c;
2174
2175 for (c = 0; c < 4; ++c) {
2176 for (i = 0; i < info->io.clipDistanceCount; ++i) {
2177 Value *ucp;
2178 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2179 i * 16 + c * 4), NULL);
2180 if (c == 0)
2181 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2182 else
2183 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2184 }
2185 }
2186
2187 for (i = 0; i < info->io.clipDistanceCount; ++i)
2188 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2189 }
2190
2191 void
2192 Converter::exportOutputs()
2193 {
2194 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2195 for (unsigned int c = 0; c < 4; ++c) {
2196 if (!oData.exists(i, c))
2197 continue;
2198 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2199 info->out[i].slot[c] * 4);
2200 Value *val = oData.load(i, c, NULL);
2201 if (val)
2202 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2203 }
2204 }
2205 }
2206
2207 Converter::Converter(Program *ir, const tgsi::Source *src)
2208 : code(src),
2209 tgsi(NULL),
2210 tData(this), aData(this), pData(this), oData(this)
2211 {
2212 prog = ir;
2213 info = code->info;
2214
2215 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2216
2217 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2218 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2219 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2220 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2221
2222 lData = NULL;
2223 iData = NULL;
2224
2225 zero = mkImm((uint32_t)0);
2226
2227 vtxBaseValid = 0;
2228 }
2229
2230 Converter::~Converter()
2231 {
2232 if (lData)
2233 delete[] lData;
2234 if (iData)
2235 delete[] iData;
2236 }
2237
2238 bool
2239 Converter::run()
2240 {
2241 BasicBlock *entry = new BasicBlock(prog->main);
2242 BasicBlock *leave = new BasicBlock(prog->main);
2243
2244 if (code->tempArrayCount && !lData) {
2245 uint32_t volume = 0;
2246 lData = new DataArray[code->tempArrayCount];
2247 if (!lData)
2248 return false;
2249 for (int i = 0; i < code->tempArrayCount; ++i) {
2250 int len = code->tempArrays[i].u32 >> 2;
2251 int dim = code->tempArrays[i].u32 & 3;
2252 lData[i].setParent(this);
2253 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2254 volume += (len * dim * 4 + 0xf) & ~0xf;
2255 }
2256 }
2257 if (code->immdArrayCount && !iData) {
2258 uint32_t volume = 0;
2259 iData = new DataArray[code->immdArrayCount];
2260 if (!iData)
2261 return false;
2262 for (int i = 0; i < code->immdArrayCount; ++i) {
2263 int len = code->immdArrays[i].u32 >> 2;
2264 int dim = code->immdArrays[i].u32 & 3;
2265 iData[i].setParent(this);
2266 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2267 volume += (len * dim * 4 + 0xf) & ~0xf;
2268 }
2269 }
2270
2271 prog->main->setEntry(entry);
2272 prog->main->setExit(leave);
2273
2274 setPosition(entry, true);
2275 entryBBs.push(entry);
2276 leaveBBs.push(leave);
2277
2278 if (info->io.clipDistanceCount) {
2279 for (int c = 0; c < 4; ++c)
2280 clipVtx[c] = getScratch();
2281 }
2282
2283 if (prog->getType() == Program::TYPE_FRAGMENT) {
2284 Symbol *sv = mkSysVal(SV_POSITION, 3);
2285 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2286 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2287 }
2288
2289 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2290 if (!handleInstruction(&code->insns[ip]))
2291 return false;
2292 }
2293 return true;
2294 }
2295
2296 } // unnamed namespace
2297
2298 namespace nv50_ir {
2299
2300 bool
2301 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2302 {
2303 tgsi::Source src(info);
2304 if (!src.scanSource())
2305 return false;
2306
2307 Converter builder(this, &src);
2308 return builder.run();
2309 }
2310
2311 } // namespace nv50_ir