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nv50/ir: handle TGSI_TEXTURE_SHADOWCUBE
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
325 default:
326 assert(0);
327 return nv50_ir::SV_CLOCK;
328 }
329 }
330
331 #define NV50_IR_TEX_TARG_CASE(a, b) \
332 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
333
334 static nv50_ir::TexTarget translateTexture(uint tex)
335 {
336 switch (tex) {
337 NV50_IR_TEX_TARG_CASE(1D, 1D);
338 NV50_IR_TEX_TARG_CASE(2D, 2D);
339 NV50_IR_TEX_TARG_CASE(3D, 3D);
340 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
341 NV50_IR_TEX_TARG_CASE(RECT, RECT);
342 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
344 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
348 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
349 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
350
351 case TGSI_TEXTURE_UNKNOWN:
352 default:
353 assert(!"invalid texture target");
354 return nv50_ir::TEX_TARGET_2D;
355 }
356 }
357
358 nv50_ir::DataType Instruction::inferSrcType() const
359 {
360 switch (getOpcode()) {
361 case TGSI_OPCODE_AND:
362 case TGSI_OPCODE_OR:
363 case TGSI_OPCODE_XOR:
364 case TGSI_OPCODE_U2F:
365 case TGSI_OPCODE_UADD:
366 case TGSI_OPCODE_UDIV:
367 case TGSI_OPCODE_UMOD:
368 case TGSI_OPCODE_UMAD:
369 case TGSI_OPCODE_UMUL:
370 case TGSI_OPCODE_UMAX:
371 case TGSI_OPCODE_UMIN:
372 case TGSI_OPCODE_USEQ:
373 case TGSI_OPCODE_USGE:
374 case TGSI_OPCODE_USLT:
375 case TGSI_OPCODE_USNE:
376 case TGSI_OPCODE_USHR:
377 case TGSI_OPCODE_UCMP:
378 return nv50_ir::TYPE_U32;
379 case TGSI_OPCODE_I2F:
380 case TGSI_OPCODE_IDIV:
381 case TGSI_OPCODE_IMAX:
382 case TGSI_OPCODE_IMIN:
383 case TGSI_OPCODE_IABS:
384 case TGSI_OPCODE_INEG:
385 case TGSI_OPCODE_ISGE:
386 case TGSI_OPCODE_ISHR:
387 case TGSI_OPCODE_ISLT:
388 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
389 case TGSI_OPCODE_MOD:
390 case TGSI_OPCODE_UARL:
391 return nv50_ir::TYPE_S32;
392 default:
393 return nv50_ir::TYPE_F32;
394 }
395 }
396
397 nv50_ir::DataType Instruction::inferDstType() const
398 {
399 switch (getOpcode()) {
400 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
401 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
402 case TGSI_OPCODE_I2F:
403 case TGSI_OPCODE_U2F:
404 return nv50_ir::TYPE_F32;
405 default:
406 return inferSrcType();
407 }
408 }
409
410 nv50_ir::CondCode Instruction::getSetCond() const
411 {
412 using namespace nv50_ir;
413
414 switch (getOpcode()) {
415 case TGSI_OPCODE_SLT:
416 case TGSI_OPCODE_ISLT:
417 case TGSI_OPCODE_USLT:
418 return CC_LT;
419 case TGSI_OPCODE_SLE:
420 return CC_LE;
421 case TGSI_OPCODE_SGE:
422 case TGSI_OPCODE_ISGE:
423 case TGSI_OPCODE_USGE:
424 return CC_GE;
425 case TGSI_OPCODE_SGT:
426 return CC_GT;
427 case TGSI_OPCODE_SEQ:
428 case TGSI_OPCODE_USEQ:
429 return CC_EQ;
430 case TGSI_OPCODE_SNE:
431 return CC_NEU;
432 case TGSI_OPCODE_USNE:
433 return CC_NE;
434 case TGSI_OPCODE_SFL:
435 return CC_NEVER;
436 case TGSI_OPCODE_STR:
437 default:
438 return CC_ALWAYS;
439 }
440 }
441
442 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
443
444 static nv50_ir::operation translateOpcode(uint opcode)
445 {
446 switch (opcode) {
447 NV50_IR_OPCODE_CASE(ARL, SHL);
448 NV50_IR_OPCODE_CASE(MOV, MOV);
449
450 NV50_IR_OPCODE_CASE(RCP, RCP);
451 NV50_IR_OPCODE_CASE(RSQ, RSQ);
452
453 NV50_IR_OPCODE_CASE(MUL, MUL);
454 NV50_IR_OPCODE_CASE(ADD, ADD);
455
456 NV50_IR_OPCODE_CASE(MIN, MIN);
457 NV50_IR_OPCODE_CASE(MAX, MAX);
458 NV50_IR_OPCODE_CASE(SLT, SET);
459 NV50_IR_OPCODE_CASE(SGE, SET);
460 NV50_IR_OPCODE_CASE(MAD, MAD);
461 NV50_IR_OPCODE_CASE(SUB, SUB);
462
463 NV50_IR_OPCODE_CASE(FLR, FLOOR);
464 NV50_IR_OPCODE_CASE(ROUND, CVT);
465 NV50_IR_OPCODE_CASE(EX2, EX2);
466 NV50_IR_OPCODE_CASE(LG2, LG2);
467 NV50_IR_OPCODE_CASE(POW, POW);
468
469 NV50_IR_OPCODE_CASE(ABS, ABS);
470
471 NV50_IR_OPCODE_CASE(COS, COS);
472 NV50_IR_OPCODE_CASE(DDX, DFDX);
473 NV50_IR_OPCODE_CASE(DDY, DFDY);
474 NV50_IR_OPCODE_CASE(KILP, DISCARD);
475
476 NV50_IR_OPCODE_CASE(SEQ, SET);
477 NV50_IR_OPCODE_CASE(SFL, SET);
478 NV50_IR_OPCODE_CASE(SGT, SET);
479 NV50_IR_OPCODE_CASE(SIN, SIN);
480 NV50_IR_OPCODE_CASE(SLE, SET);
481 NV50_IR_OPCODE_CASE(SNE, SET);
482 NV50_IR_OPCODE_CASE(STR, SET);
483 NV50_IR_OPCODE_CASE(TEX, TEX);
484 NV50_IR_OPCODE_CASE(TXD, TXD);
485 NV50_IR_OPCODE_CASE(TXP, TEX);
486
487 NV50_IR_OPCODE_CASE(BRA, BRA);
488 NV50_IR_OPCODE_CASE(CAL, CALL);
489 NV50_IR_OPCODE_CASE(RET, RET);
490 NV50_IR_OPCODE_CASE(CMP, SLCT);
491
492 NV50_IR_OPCODE_CASE(TXB, TXB);
493
494 NV50_IR_OPCODE_CASE(DIV, DIV);
495
496 NV50_IR_OPCODE_CASE(TXL, TXL);
497
498 NV50_IR_OPCODE_CASE(CEIL, CEIL);
499 NV50_IR_OPCODE_CASE(I2F, CVT);
500 NV50_IR_OPCODE_CASE(NOT, NOT);
501 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
502 NV50_IR_OPCODE_CASE(SHL, SHL);
503
504 NV50_IR_OPCODE_CASE(AND, AND);
505 NV50_IR_OPCODE_CASE(OR, OR);
506 NV50_IR_OPCODE_CASE(MOD, MOD);
507 NV50_IR_OPCODE_CASE(XOR, XOR);
508 NV50_IR_OPCODE_CASE(SAD, SAD);
509 NV50_IR_OPCODE_CASE(TXF, TXF);
510 NV50_IR_OPCODE_CASE(TXQ, TXQ);
511
512 NV50_IR_OPCODE_CASE(EMIT, EMIT);
513 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
514
515 NV50_IR_OPCODE_CASE(KIL, DISCARD);
516
517 NV50_IR_OPCODE_CASE(F2I, CVT);
518 NV50_IR_OPCODE_CASE(IDIV, DIV);
519 NV50_IR_OPCODE_CASE(IMAX, MAX);
520 NV50_IR_OPCODE_CASE(IMIN, MIN);
521 NV50_IR_OPCODE_CASE(IABS, ABS);
522 NV50_IR_OPCODE_CASE(INEG, NEG);
523 NV50_IR_OPCODE_CASE(ISGE, SET);
524 NV50_IR_OPCODE_CASE(ISHR, SHR);
525 NV50_IR_OPCODE_CASE(ISLT, SET);
526 NV50_IR_OPCODE_CASE(F2U, CVT);
527 NV50_IR_OPCODE_CASE(U2F, CVT);
528 NV50_IR_OPCODE_CASE(UADD, ADD);
529 NV50_IR_OPCODE_CASE(UDIV, DIV);
530 NV50_IR_OPCODE_CASE(UMAD, MAD);
531 NV50_IR_OPCODE_CASE(UMAX, MAX);
532 NV50_IR_OPCODE_CASE(UMIN, MIN);
533 NV50_IR_OPCODE_CASE(UMOD, MOD);
534 NV50_IR_OPCODE_CASE(UMUL, MUL);
535 NV50_IR_OPCODE_CASE(USEQ, SET);
536 NV50_IR_OPCODE_CASE(USGE, SET);
537 NV50_IR_OPCODE_CASE(USHR, SHR);
538 NV50_IR_OPCODE_CASE(USLT, SET);
539 NV50_IR_OPCODE_CASE(USNE, SET);
540
541 NV50_IR_OPCODE_CASE(LOAD, TXF);
542 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
543 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
544 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
545 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
546 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
547 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
548 NV50_IR_OPCODE_CASE(GATHER4, TXG);
549 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
550
551 NV50_IR_OPCODE_CASE(END, EXIT);
552
553 default:
554 return nv50_ir::OP_NOP;
555 }
556 }
557
558 bool Instruction::checkDstSrcAliasing() const
559 {
560 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
561 return false;
562
563 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
564 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
565 break;
566 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
567 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
568 return true;
569 }
570 return false;
571 }
572
573 class Source
574 {
575 public:
576 Source(struct nv50_ir_prog_info *);
577 ~Source();
578
579 struct Subroutine
580 {
581 unsigned pc;
582 };
583
584 public:
585 bool scanSource();
586 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
587
588 public:
589 struct tgsi_shader_info scan;
590 struct tgsi_full_instruction *insns;
591 const struct tgsi_token *tokens;
592 struct nv50_ir_prog_info *info;
593
594 nv50_ir::DynArray tempArrays;
595 nv50_ir::DynArray immdArrays;
596 int tempArrayCount;
597 int immdArrayCount;
598
599 bool mainTempsInLMem;
600
601 int clipVertexOutput;
602
603 uint8_t *resourceTargets; // TGSI_TEXTURE_*
604 unsigned resourceCount;
605
606 Subroutine *subroutines;
607 unsigned subroutineCount;
608
609 private:
610 int inferSysValDirection(unsigned sn) const;
611 bool scanDeclaration(const struct tgsi_full_declaration *);
612 bool scanInstruction(const struct tgsi_full_instruction *);
613 void scanProperty(const struct tgsi_full_property *);
614 void scanImmediate(const struct tgsi_full_immediate *);
615
616 inline bool isEdgeFlagPassthrough(const Instruction&) const;
617 };
618
619 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
620 {
621 tokens = (const struct tgsi_token *)info->bin.source;
622
623 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
624 tgsi_dump(tokens, 0);
625
626 resourceTargets = NULL;
627 subroutines = NULL;
628
629 mainTempsInLMem = FALSE;
630 }
631
632 Source::~Source()
633 {
634 if (insns)
635 FREE(insns);
636
637 if (info->immd.data)
638 FREE(info->immd.data);
639 if (info->immd.type)
640 FREE(info->immd.type);
641
642 if (resourceTargets)
643 delete[] resourceTargets;
644 if (subroutines)
645 delete[] subroutines;
646 }
647
648 bool Source::scanSource()
649 {
650 unsigned insnCount = 0;
651 unsigned subrCount = 0;
652 struct tgsi_parse_context parse;
653
654 tgsi_scan_shader(tokens, &scan);
655
656 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
657 sizeof(insns[0]));
658 if (!insns)
659 return false;
660
661 clipVertexOutput = -1;
662
663 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
664 resourceTargets = new uint8_t[resourceCount];
665
666 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
667 subroutines = new Subroutine[subroutineCount];
668
669 info->immd.bufSize = 0;
670 tempArrayCount = 0;
671 immdArrayCount = 0;
672
673 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
674 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
675 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
676
677 if (info->type == PIPE_SHADER_FRAGMENT) {
678 info->prop.fp.writesDepth = scan.writes_z;
679 info->prop.fp.usesDiscard = scan.uses_kill;
680 } else
681 if (info->type == PIPE_SHADER_GEOMETRY) {
682 info->prop.gp.instanceCount = 1; // default value
683 }
684
685 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
686 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
687
688 tgsi_parse_init(&parse, tokens);
689 while (!tgsi_parse_end_of_tokens(&parse)) {
690 tgsi_parse_token(&parse);
691
692 switch (parse.FullToken.Token.Type) {
693 case TGSI_TOKEN_TYPE_IMMEDIATE:
694 scanImmediate(&parse.FullToken.FullImmediate);
695 break;
696 case TGSI_TOKEN_TYPE_DECLARATION:
697 scanDeclaration(&parse.FullToken.FullDeclaration);
698 break;
699 case TGSI_TOKEN_TYPE_INSTRUCTION:
700 insns[insnCount++] = parse.FullToken.FullInstruction;
701 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
702 subroutines[++subrCount].pc = insnCount - 1;
703 else
704 scanInstruction(&parse.FullToken.FullInstruction);
705 break;
706 case TGSI_TOKEN_TYPE_PROPERTY:
707 scanProperty(&parse.FullToken.FullProperty);
708 break;
709 default:
710 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
711 break;
712 }
713 }
714 tgsi_parse_free(&parse);
715
716 if (mainTempsInLMem)
717 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
718
719 if (info->io.genUserClip > 0)
720 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
721
722 return info->assignSlots(info) == 0;
723 }
724
725 void Source::scanProperty(const struct tgsi_full_property *prop)
726 {
727 switch (prop->Property.PropertyName) {
728 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
729 info->prop.gp.outputPrim = prop->u[0].Data;
730 break;
731 case TGSI_PROPERTY_GS_INPUT_PRIM:
732 info->prop.gp.inputPrim = prop->u[0].Data;
733 break;
734 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
735 info->prop.gp.maxVertices = prop->u[0].Data;
736 break;
737 #if 0
738 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
739 info->prop.gp.instanceCount = prop->u[0].Data;
740 break;
741 #endif
742 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
743 info->prop.fp.separateFragData = TRUE;
744 break;
745 case TGSI_PROPERTY_FS_COORD_ORIGIN:
746 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
747 // we don't care
748 break;
749 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
750 info->io.genUserClip = -1;
751 break;
752 default:
753 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
754 break;
755 }
756 }
757
758 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
759 {
760 const unsigned n = info->immd.count++;
761
762 assert(n < scan.immediate_count);
763
764 for (int c = 0; c < 4; ++c)
765 info->immd.data[n * 4 + c] = imm->u[c].Uint;
766
767 info->immd.type[n] = imm->Immediate.DataType;
768 }
769
770 int Source::inferSysValDirection(unsigned sn) const
771 {
772 switch (sn) {
773 case TGSI_SEMANTIC_INSTANCEID:
774 case TGSI_SEMANTIC_VERTEXID:
775 return 1;
776 #if 0
777 case TGSI_SEMANTIC_LAYER:
778 case TGSI_SEMANTIC_VIEWPORTINDEX:
779 return 0;
780 #endif
781 case TGSI_SEMANTIC_PRIMID:
782 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
783 default:
784 return 0;
785 }
786 }
787
788 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
789 {
790 unsigned i;
791 unsigned sn = TGSI_SEMANTIC_GENERIC;
792 unsigned si = 0;
793 const unsigned first = decl->Range.First, last = decl->Range.Last;
794
795 if (decl->Declaration.Semantic) {
796 sn = decl->Semantic.Name;
797 si = decl->Semantic.Index;
798 }
799
800 switch (decl->Declaration.File) {
801 case TGSI_FILE_INPUT:
802 if (info->type == PIPE_SHADER_VERTEX) {
803 // all vertex attributes are equal
804 for (i = first; i <= last; ++i) {
805 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
806 info->in[i].si = i;
807 }
808 } else {
809 for (i = first; i <= last; ++i, ++si) {
810 info->in[i].id = i;
811 info->in[i].sn = sn;
812 info->in[i].si = si;
813 if (info->type == PIPE_SHADER_FRAGMENT) {
814 // translate interpolation mode
815 switch (decl->Declaration.Interpolate) {
816 case TGSI_INTERPOLATE_CONSTANT:
817 info->in[i].flat = 1;
818 break;
819 case TGSI_INTERPOLATE_LINEAR:
820 if (sn != TGSI_SEMANTIC_COLOR) // GL_NICEST
821 info->in[i].linear = 1;
822 break;
823 default:
824 break;
825 }
826 if (decl->Declaration.Centroid)
827 info->in[i].centroid = 1;
828 }
829 }
830 }
831 break;
832 case TGSI_FILE_OUTPUT:
833 for (i = first; i <= last; ++i, ++si) {
834 switch (sn) {
835 case TGSI_SEMANTIC_POSITION:
836 if (info->type == PIPE_SHADER_FRAGMENT)
837 info->io.fragDepth = i;
838 else
839 if (clipVertexOutput < 0)
840 clipVertexOutput = i;
841 break;
842 case TGSI_SEMANTIC_COLOR:
843 if (info->type == PIPE_SHADER_FRAGMENT)
844 info->prop.fp.numColourResults++;
845 break;
846 case TGSI_SEMANTIC_EDGEFLAG:
847 info->io.edgeFlagOut = i;
848 break;
849 case TGSI_SEMANTIC_CLIPVERTEX:
850 clipVertexOutput = i;
851 break;
852 case TGSI_SEMANTIC_CLIPDIST:
853 info->io.clipDistanceMask |=
854 decl->Declaration.UsageMask << (si * 4);
855 info->io.genUserClip = -1;
856 break;
857 default:
858 break;
859 }
860 info->out[i].id = i;
861 info->out[i].sn = sn;
862 info->out[i].si = si;
863 }
864 break;
865 case TGSI_FILE_SYSTEM_VALUE:
866 for (i = first; i <= last; ++i, ++si) {
867 info->sv[i].sn = sn;
868 info->sv[i].si = si;
869 info->sv[i].input = inferSysValDirection(sn);
870 }
871 break;
872 case TGSI_FILE_RESOURCE:
873 for (i = first; i <= last; ++i)
874 resourceTargets[i] = decl->Resource.Resource;
875 break;
876 case TGSI_FILE_IMMEDIATE_ARRAY:
877 {
878 if (decl->Dim.Index2D >= immdArrayCount)
879 immdArrayCount = decl->Dim.Index2D + 1;
880 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
881 int c;
882 uint32_t base, count;
883 switch (decl->Declaration.UsageMask) {
884 case 0x1: c = 1; break;
885 case 0x3: c = 2; break;
886 default:
887 c = 4;
888 break;
889 }
890 immdArrays[decl->Dim.Index2D].u32 |= c;
891 count = (last + 1) * c;
892 base = info->immd.bufSize / 4;
893 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
894 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
895 info->immd.bufSize);
896 // NOTE: this assumes array declarations are ordered by Dim.Index2D
897 for (i = 0; i < count; ++i)
898 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
899 }
900 break;
901 case TGSI_FILE_TEMPORARY_ARRAY:
902 {
903 if (decl->Dim.Index2D >= tempArrayCount)
904 tempArrayCount = decl->Dim.Index2D + 1;
905 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
906 int c;
907 uint32_t count;
908 switch (decl->Declaration.UsageMask) {
909 case 0x1: c = 1; break;
910 case 0x3: c = 2; break;
911 default:
912 c = 4;
913 break;
914 }
915 tempArrays[decl->Dim.Index2D].u32 |= c;
916 count = (last + 1) * c;
917 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
918 }
919 break;
920 case TGSI_FILE_NULL:
921 case TGSI_FILE_TEMPORARY:
922 case TGSI_FILE_ADDRESS:
923 case TGSI_FILE_CONSTANT:
924 case TGSI_FILE_IMMEDIATE:
925 case TGSI_FILE_PREDICATE:
926 case TGSI_FILE_SAMPLER:
927 break;
928 default:
929 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
930 return false;
931 }
932 return true;
933 }
934
935 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
936 {
937 return insn.getOpcode() == TGSI_OPCODE_MOV &&
938 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
939 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
940 }
941
942 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
943 {
944 Instruction insn(inst);
945
946 if (insn.dstCount()) {
947 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
948 Instruction::DstRegister dst = insn.getDst(0);
949
950 if (dst.isIndirect(0))
951 for (unsigned i = 0; i < info->numOutputs; ++i)
952 info->out[i].mask = 0xf;
953 else
954 info->out[dst.getIndex(0)].mask |= dst.getMask();
955
956 if (isEdgeFlagPassthrough(insn))
957 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
958 } else
959 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
960 if (insn.getDst(0).isIndirect(0))
961 mainTempsInLMem = TRUE;
962 }
963 }
964
965 for (unsigned s = 0; s < insn.srcCount(); ++s) {
966 Instruction::SrcRegister src = insn.getSrc(s);
967 if (src.getFile() == TGSI_FILE_TEMPORARY)
968 if (src.isIndirect(0))
969 mainTempsInLMem = TRUE;
970 if (src.getFile() != TGSI_FILE_INPUT)
971 continue;
972 unsigned mask = insn.srcMask(s);
973
974 if (src.isIndirect(0)) {
975 for (unsigned i = 0; i < info->numInputs; ++i)
976 info->in[i].mask = 0xf;
977 } else {
978 for (unsigned c = 0; c < 4; ++c) {
979 if (!(mask & (1 << c)))
980 continue;
981 int k = src.getSwizzle(c);
982 int i = src.getIndex(0);
983 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
984 if (k <= TGSI_SWIZZLE_W)
985 info->in[i].mask |= 1 << k;
986 }
987 }
988 }
989 return true;
990 }
991
992 nv50_ir::TexInstruction::Target
993 Instruction::getTexture(const tgsi::Source *code, int s) const
994 {
995 if (insn->Instruction.Texture) {
996 return translateTexture(insn->Texture.Texture);
997 } else {
998 // XXX: indirect access
999 unsigned int r = getSrc(s).getIndex(0);
1000 assert(r < code->resourceCount);
1001 return translateTexture(code->resourceTargets[r]);
1002 }
1003 }
1004
1005 } // namespace tgsi
1006
1007 namespace {
1008
1009 using namespace nv50_ir;
1010
1011 class Converter : public BuildUtil
1012 {
1013 public:
1014 Converter(Program *, const tgsi::Source *);
1015 ~Converter();
1016
1017 bool run();
1018
1019 private:
1020 Value *getVertexBase(int s);
1021 Value *fetchSrc(int s, int c);
1022 Value *acquireDst(int d, int c);
1023 void storeDst(int d, int c, Value *);
1024
1025 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1026 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1027 Value *val, Value *ptr);
1028
1029 Value *applySrcMod(Value *, int s, int c);
1030
1031 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1032 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1033 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1034
1035 bool handleInstruction(const struct tgsi_full_instruction *);
1036 void exportOutputs();
1037 inline bool isEndOfSubroutine(uint ip);
1038
1039 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1040
1041 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1042 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1043 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1044 void handleTXF(Value *dst0[4], int R);
1045 void handleTXQ(Value *dst0[4], enum TexQuery);
1046 void handleLIT(Value *dst0[4]);
1047 void handleUserClipPlanes();
1048
1049 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1050
1051 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1052
1053 Value *buildDot(int dim);
1054
1055 private:
1056 const struct tgsi::Source *code;
1057 const struct nv50_ir_prog_info *info;
1058
1059 uint ip; // instruction pointer
1060
1061 tgsi::Instruction tgsi;
1062
1063 DataType dstTy;
1064 DataType srcTy;
1065
1066 DataArray tData; // TGSI_FILE_TEMPORARY
1067 DataArray aData; // TGSI_FILE_ADDRESS
1068 DataArray pData; // TGSI_FILE_PREDICATE
1069 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1070 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1071 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1072
1073 Value *zero;
1074 Value *fragCoord[4];
1075 Value *clipVtx[4];
1076
1077 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1078 uint8_t vtxBaseValid;
1079
1080 Stack condBBs; // fork BB, then else clause BB
1081 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1082 Stack loopBBs; // loop headers
1083 Stack breakBBs; // end of / after loop
1084 Stack entryBBs; // start of current (inlined) subroutine
1085 Stack leaveBBs; // end of current (inlined) subroutine
1086 Stack retIPs; // return instruction pointer
1087 };
1088
1089 Symbol *
1090 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1091 {
1092 const int swz = src.getSwizzle(c);
1093
1094 return makeSym(src.getFile(),
1095 src.is2D() ? src.getIndex(1) : 0,
1096 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1097 src.getIndex(0) * 16 + swz * 4);
1098 }
1099
1100 Symbol *
1101 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1102 {
1103 return makeSym(dst.getFile(),
1104 dst.is2D() ? dst.getIndex(1) : 0,
1105 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1106 dst.getIndex(0) * 16 + c * 4);
1107 }
1108
1109 Symbol *
1110 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1111 {
1112 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1113
1114 sym->reg.fileIndex = fileIdx;
1115
1116 if (idx >= 0) {
1117 if (sym->reg.file == FILE_SHADER_INPUT)
1118 sym->setOffset(info->in[idx].slot[c] * 4);
1119 else
1120 if (sym->reg.file == FILE_SHADER_OUTPUT)
1121 sym->setOffset(info->out[idx].slot[c] * 4);
1122 else
1123 if (sym->reg.file == FILE_SYSTEM_VALUE)
1124 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1125 else
1126 sym->setOffset(address);
1127 } else {
1128 sym->setOffset(address);
1129 }
1130 return sym;
1131 }
1132
1133 static inline uint8_t
1134 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1135 {
1136 uint8_t mode;
1137
1138 if (var->flat)
1139 mode = NV50_IR_INTERP_FLAT;
1140 else
1141 if (var->linear)
1142 mode = NV50_IR_INTERP_LINEAR;
1143 else
1144 mode = NV50_IR_INTERP_PERSPECTIVE;
1145
1146 op = (mode == NV50_IR_INTERP_PERSPECTIVE) ? OP_PINTERP : OP_LINTERP;
1147
1148 if (var->centroid)
1149 mode |= NV50_IR_INTERP_CENTROID;
1150
1151 return mode;
1152 }
1153
1154 Value *
1155 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1156 {
1157 operation op;
1158
1159 // XXX: no way to know interpolation mode if we don't know what's accessed
1160 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1161 src.getIndex(0)], op);
1162
1163 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1164
1165 insn->setDef(0, getScratch());
1166 insn->setSrc(0, srcToSym(src, c));
1167 if (op == OP_PINTERP)
1168 insn->setSrc(1, fragCoord[3]);
1169 if (ptr)
1170 insn->setIndirect(0, 0, ptr);
1171
1172 insn->setInterpolate(mode);
1173
1174 bb->insertTail(insn);
1175 return insn->getDef(0);
1176 }
1177
1178 Value *
1179 Converter::applySrcMod(Value *val, int s, int c)
1180 {
1181 Modifier m = tgsi.getSrc(s).getMod(c);
1182 DataType ty = tgsi.inferSrcType();
1183
1184 if (m & Modifier(NV50_IR_MOD_ABS))
1185 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1186
1187 if (m & Modifier(NV50_IR_MOD_NEG))
1188 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1189
1190 return val;
1191 }
1192
1193 Value *
1194 Converter::getVertexBase(int s)
1195 {
1196 assert(s < 5);
1197 if (!(vtxBaseValid & (1 << s))) {
1198 const int index = tgsi.getSrc(s).getIndex(1);
1199 Value *rel = NULL;
1200 if (tgsi.getSrc(s).isIndirect(1))
1201 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1202 vtxBaseValid |= 1 << s;
1203 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1204 }
1205 return vtxBase[s];
1206 }
1207
1208 Value *
1209 Converter::fetchSrc(int s, int c)
1210 {
1211 Value *res;
1212 Value *ptr = NULL, *dimRel = NULL;
1213
1214 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1215
1216 if (src.isIndirect(0))
1217 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1218
1219 if (src.is2D()) {
1220 switch (src.getFile()) {
1221 case TGSI_FILE_INPUT:
1222 dimRel = getVertexBase(s);
1223 break;
1224 case TGSI_FILE_CONSTANT:
1225 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1226 if (src.isIndirect(1))
1227 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1228 break;
1229 default:
1230 break;
1231 }
1232 }
1233
1234 res = fetchSrc(src, c, ptr);
1235
1236 if (dimRel)
1237 res->getInsn()->setIndirect(0, 1, dimRel);
1238
1239 return applySrcMod(res, s, c);
1240 }
1241
1242 Value *
1243 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1244 {
1245 const int idx = src.getIndex(0);
1246 const int swz = src.getSwizzle(c);
1247
1248 switch (src.getFile()) {
1249 case TGSI_FILE_TEMPORARY:
1250 return tData.load(idx, swz, ptr);
1251 case TGSI_FILE_PREDICATE:
1252 return pData.load(idx, swz, ptr);
1253 case TGSI_FILE_ADDRESS:
1254 return aData.load(idx, swz, ptr);
1255
1256 case TGSI_FILE_TEMPORARY_ARRAY:
1257 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1258 return lData[src.getIndex(1)].load(idx, swz, ptr);
1259 case TGSI_FILE_IMMEDIATE_ARRAY:
1260 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1261 return iData[src.getIndex(1)].load(idx, swz, ptr);
1262
1263 case TGSI_FILE_IMMEDIATE:
1264 assert(!ptr);
1265 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1266
1267 case TGSI_FILE_CONSTANT:
1268 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1269
1270 case TGSI_FILE_INPUT:
1271 if (prog->getType() == Program::TYPE_FRAGMENT) {
1272 // don't load masked inputs, won't be assigned a slot
1273 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1274 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1275 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1276 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1277 return interpolate(src, c, ptr);
1278 }
1279 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1280
1281 case TGSI_FILE_SYSTEM_VALUE:
1282 assert(!ptr);
1283 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1284
1285 case TGSI_FILE_OUTPUT:
1286 case TGSI_FILE_RESOURCE:
1287 case TGSI_FILE_SAMPLER:
1288 case TGSI_FILE_NULL:
1289 default:
1290 assert(!"invalid/unhandled TGSI source file");
1291 return NULL;
1292 }
1293 }
1294
1295 Value *
1296 Converter::acquireDst(int d, int c)
1297 {
1298 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1299
1300 if (dst.isMasked(c))
1301 return NULL;
1302 if (dst.isIndirect(0))
1303 return getScratch();
1304
1305 const int idx = dst.getIndex(0);
1306
1307 switch (dst.getFile()) {
1308 case TGSI_FILE_TEMPORARY:
1309 return tData.acquire(idx, c);
1310 case TGSI_FILE_TEMPORARY_ARRAY:
1311 return getScratch();
1312 case TGSI_FILE_PREDICATE:
1313 return pData.acquire(idx, c);
1314 case TGSI_FILE_ADDRESS:
1315 return aData.acquire(idx, c);
1316
1317 case TGSI_FILE_OUTPUT:
1318 if (prog->getType() == Program::TYPE_FRAGMENT)
1319 return oData.acquire(idx, c);
1320 // fall through
1321 case TGSI_FILE_SYSTEM_VALUE:
1322 return getScratch();
1323
1324 default:
1325 assert(!"invalid dst file");
1326 return NULL;
1327 }
1328 }
1329
1330 void
1331 Converter::storeDst(int d, int c, Value *val)
1332 {
1333 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1334
1335 switch (tgsi.getSaturate()) {
1336 case TGSI_SAT_NONE:
1337 break;
1338 case TGSI_SAT_ZERO_ONE:
1339 mkOp1(OP_SAT, dstTy, val, val);
1340 break;
1341 case TGSI_SAT_MINUS_PLUS_ONE:
1342 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1343 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1344 break;
1345 default:
1346 assert(!"invalid saturation mode");
1347 break;
1348 }
1349
1350 Value *ptr = dst.isIndirect(0) ?
1351 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1352
1353 if (info->io.genUserClip > 0 &&
1354 dst.getFile() == TGSI_FILE_OUTPUT &&
1355 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1356 mkMov(clipVtx[c], val);
1357 val = clipVtx[c];
1358 }
1359
1360 storeDst(dst, c, val, ptr);
1361 }
1362
1363 void
1364 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1365 Value *val, Value *ptr)
1366 {
1367 const int idx = dst.getIndex(0);
1368
1369 switch (dst.getFile()) {
1370 case TGSI_FILE_TEMPORARY:
1371 tData.store(idx, c, ptr, val);
1372 break;
1373 case TGSI_FILE_TEMPORARY_ARRAY:
1374 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1375 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1376 break;
1377 case TGSI_FILE_PREDICATE:
1378 pData.store(idx, c, ptr, val);
1379 break;
1380 case TGSI_FILE_ADDRESS:
1381 aData.store(idx, c, ptr, val);
1382 break;
1383
1384 case TGSI_FILE_OUTPUT:
1385 if (prog->getType() == Program::TYPE_FRAGMENT)
1386 oData.store(idx, c, ptr, val);
1387 else
1388 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1389 break;
1390
1391 case TGSI_FILE_SYSTEM_VALUE:
1392 assert(!ptr);
1393 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1394 break;
1395
1396 default:
1397 assert(!"invalid dst file");
1398 break;
1399 }
1400 }
1401
1402 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1403 for (chan = 0; chan < 4; ++chan) \
1404 if (!inst.getDst(d).isMasked(chan))
1405
1406 Value *
1407 Converter::buildDot(int dim)
1408 {
1409 assert(dim > 0);
1410
1411 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1412 Value *dotp = getScratch();
1413
1414 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1415
1416 for (int c = 1; c < dim; ++c) {
1417 src0 = fetchSrc(0, c);
1418 src1 = fetchSrc(1, c);
1419 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1420 }
1421 return dotp;
1422 }
1423
1424 void
1425 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1426 {
1427 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1428 join->fixed = 1;
1429 conv->insertHead(join);
1430
1431 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1432 fork->insertBefore(fork->getExit(), fork->joinAt);
1433 }
1434
1435 void
1436 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1437 {
1438 unsigned rIdx = 0, sIdx = 0;
1439
1440 if (R >= 0)
1441 rIdx = tgsi.getSrc(R).getIndex(0);
1442 if (S >= 0)
1443 sIdx = tgsi.getSrc(S).getIndex(0);
1444
1445 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1446
1447 if (tgsi.getSrc(R).isIndirect(0)) {
1448 tex->tex.rIndirectSrc = s;
1449 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1450 }
1451 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1452 tex->tex.sIndirectSrc = s;
1453 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1454 }
1455 }
1456
1457 void
1458 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1459 {
1460 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1461 tex->tex.query = query;
1462 unsigned int c, d;
1463
1464 for (d = 0, c = 0; c < 4; ++c) {
1465 if (!dst0[c])
1466 continue;
1467 tex->tex.mask |= 1 << c;
1468 tex->setDef(d++, dst0[c]);
1469 }
1470 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1471
1472 setTexRS(tex, c, 1, -1);
1473
1474 bb->insertTail(tex);
1475 }
1476
1477 void
1478 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1479 {
1480 Value *proj = fetchSrc(0, 3);
1481 Instruction *insn = proj->getUniqueInsn();
1482 int c;
1483
1484 if (insn->op == OP_PINTERP) {
1485 bb->insertTail(insn = insn->clone(true));
1486 insn->op = OP_LINTERP;
1487 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1488 insn->setSrc(1, NULL);
1489 proj = insn->getDef(0);
1490 }
1491 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1492
1493 for (c = 0; c < 4; ++c) {
1494 if (!(mask & (1 << c)))
1495 continue;
1496 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1497 continue;
1498 mask &= ~(1 << c);
1499
1500 bb->insertTail(insn = insn->clone(true));
1501 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1502 insn->setSrc(1, proj);
1503 dst[c] = insn->getDef(0);
1504 }
1505 if (!mask)
1506 return;
1507
1508 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1509
1510 for (c = 0; c < 4; ++c)
1511 if (mask & (1 << c))
1512 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1513 }
1514
1515 // order of nv50 ir sources: x y z layer lod/bias shadow
1516 // order of TGSI TEX sources: x y z layer shadow lod/bias
1517 // lowering will finally set the hw specific order (like array first on nvc0)
1518 void
1519 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1520 {
1521 Value *val;
1522 Value *arg[4], *src[8];
1523 Value *lod = NULL, *shd = NULL;
1524 unsigned int s, c, d;
1525 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1526
1527 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1528
1529 for (s = 0; s < tgt.getArgCount(); ++s)
1530 arg[s] = src[s] = fetchSrc(0, s);
1531
1532 if (texi->op == OP_TXL || texi->op == OP_TXB)
1533 lod = fetchSrc(L >> 4, L & 3);
1534
1535 if (C == 0x0f)
1536 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1537
1538 if (tgt.isShadow())
1539 shd = fetchSrc(C >> 4, C & 3);
1540
1541 if (texi->op == OP_TXD) {
1542 for (c = 0; c < tgt.getDim(); ++c) {
1543 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1544 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1545 }
1546 }
1547
1548 // cube textures don't care about projection value, it's divided out
1549 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1550 unsigned int n = tgt.getDim();
1551 if (shd) {
1552 arg[n] = shd;
1553 ++n;
1554 assert(tgt.getDim() == tgt.getArgCount());
1555 }
1556 loadProjTexCoords(src, arg, (1 << n) - 1);
1557 if (shd)
1558 shd = src[n - 1];
1559 }
1560
1561 if (tgt.isCube()) {
1562 for (c = 0; c < 3; ++c)
1563 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1564 val = getScratch();
1565 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1566 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1567 mkOp1(OP_RCP, TYPE_F32, val, val);
1568 for (c = 0; c < 3; ++c)
1569 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1570 }
1571
1572 for (c = 0, d = 0; c < 4; ++c) {
1573 if (dst[c]) {
1574 texi->setDef(d++, dst[c]);
1575 texi->tex.mask |= 1 << c;
1576 } else {
1577 // NOTE: maybe hook up def too, for CSE
1578 }
1579 }
1580 for (s = 0; s < tgt.getArgCount(); ++s)
1581 texi->setSrc(s, src[s]);
1582 if (lod)
1583 texi->setSrc(s++, lod);
1584 if (shd)
1585 texi->setSrc(s++, shd);
1586
1587 setTexRS(texi, s, R, S);
1588
1589 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1590 texi->tex.levelZero = true;
1591
1592 bb->insertTail(texi);
1593 }
1594
1595 // 1st source: xyz = coordinates, w = lod
1596 // 2nd source: offset
1597 void
1598 Converter::handleTXF(Value *dst[4], int R)
1599 {
1600 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1601 unsigned int c, d, s;
1602
1603 texi->tex.target = tgsi.getTexture(code, R);
1604
1605 for (c = 0, d = 0; c < 4; ++c) {
1606 if (dst[c]) {
1607 texi->setDef(d++, dst[c]);
1608 texi->tex.mask |= 1 << c;
1609 }
1610 }
1611 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1612 texi->setSrc(c, fetchSrc(0, c));
1613 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1614
1615 setTexRS(texi, c, R, -1);
1616
1617 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1618 for (c = 0; c < 3; ++c) {
1619 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1620 if (texi->tex.offset[s][c])
1621 texi->tex.useOffsets = s + 1;
1622 }
1623 }
1624
1625 bb->insertTail(texi);
1626 }
1627
1628 void
1629 Converter::handleLIT(Value *dst0[4])
1630 {
1631 Value *val0 = NULL;
1632 unsigned int mask = tgsi.getDst(0).getMask();
1633
1634 if (mask & (1 << 0))
1635 loadImm(dst0[0], 1.0f);
1636
1637 if (mask & (1 << 3))
1638 loadImm(dst0[3], 1.0f);
1639
1640 if (mask & (3 << 1)) {
1641 val0 = getScratch();
1642 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1643 if (mask & (1 << 1))
1644 mkMov(dst0[1], val0);
1645 }
1646
1647 if (mask & (1 << 2)) {
1648 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1649 Value *val1 = getScratch(), *val3 = getScratch();
1650
1651 Value *pos128 = loadImm(NULL, +127.999999f);
1652 Value *neg128 = loadImm(NULL, -127.999999f);
1653
1654 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1655 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1656 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1657 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1658
1659 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1660 }
1661 }
1662
1663 bool
1664 Converter::isEndOfSubroutine(uint ip)
1665 {
1666 assert(ip < code->scan.num_instructions);
1667 tgsi::Instruction insn(&code->insns[ip]);
1668 return (insn.getOpcode() == TGSI_OPCODE_END ||
1669 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1670 // does END occur at end of main or the very end ?
1671 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1672 }
1673
1674 bool
1675 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1676 {
1677 Value *dst0[4], *rDst0[4];
1678 Value *src0, *src1, *src2;
1679 Value *val0, *val1;
1680 int c;
1681
1682 tgsi = tgsi::Instruction(insn);
1683
1684 bool useScratchDst = tgsi.checkDstSrcAliasing();
1685
1686 operation op = tgsi.getOP();
1687 dstTy = tgsi.inferDstType();
1688 srcTy = tgsi.inferSrcType();
1689
1690 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1691
1692 if (tgsi.dstCount()) {
1693 for (c = 0; c < 4; ++c) {
1694 rDst0[c] = acquireDst(0, c);
1695 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1696 }
1697 }
1698
1699 switch (tgsi.getOpcode()) {
1700 case TGSI_OPCODE_ADD:
1701 case TGSI_OPCODE_UADD:
1702 case TGSI_OPCODE_AND:
1703 case TGSI_OPCODE_DIV:
1704 case TGSI_OPCODE_IDIV:
1705 case TGSI_OPCODE_UDIV:
1706 case TGSI_OPCODE_MAX:
1707 case TGSI_OPCODE_MIN:
1708 case TGSI_OPCODE_IMAX:
1709 case TGSI_OPCODE_IMIN:
1710 case TGSI_OPCODE_UMAX:
1711 case TGSI_OPCODE_UMIN:
1712 case TGSI_OPCODE_MOD:
1713 case TGSI_OPCODE_UMOD:
1714 case TGSI_OPCODE_MUL:
1715 case TGSI_OPCODE_UMUL:
1716 case TGSI_OPCODE_OR:
1717 case TGSI_OPCODE_POW:
1718 case TGSI_OPCODE_SHL:
1719 case TGSI_OPCODE_ISHR:
1720 case TGSI_OPCODE_USHR:
1721 case TGSI_OPCODE_SUB:
1722 case TGSI_OPCODE_XOR:
1723 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1724 src0 = fetchSrc(0, c);
1725 src1 = fetchSrc(1, c);
1726 mkOp2(op, dstTy, dst0[c], src0, src1);
1727 }
1728 break;
1729 case TGSI_OPCODE_MAD:
1730 case TGSI_OPCODE_UMAD:
1731 case TGSI_OPCODE_SAD:
1732 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1733 src0 = fetchSrc(0, c);
1734 src1 = fetchSrc(1, c);
1735 src2 = fetchSrc(2, c);
1736 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1737 }
1738 break;
1739 case TGSI_OPCODE_MOV:
1740 case TGSI_OPCODE_ABS:
1741 case TGSI_OPCODE_CEIL:
1742 case TGSI_OPCODE_FLR:
1743 case TGSI_OPCODE_TRUNC:
1744 case TGSI_OPCODE_RCP:
1745 case TGSI_OPCODE_IABS:
1746 case TGSI_OPCODE_INEG:
1747 case TGSI_OPCODE_NOT:
1748 case TGSI_OPCODE_DDX:
1749 case TGSI_OPCODE_DDY:
1750 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1751 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1752 break;
1753 case TGSI_OPCODE_RSQ:
1754 src0 = fetchSrc(0, 0);
1755 val0 = getScratch();
1756 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1757 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1758 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1759 mkMov(dst0[c], val0);
1760 break;
1761 case TGSI_OPCODE_ARL:
1762 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1763 src0 = fetchSrc(0, c);
1764 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1765 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1766 }
1767 break;
1768 case TGSI_OPCODE_UARL:
1769 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1770 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1771 break;
1772 case TGSI_OPCODE_EX2:
1773 case TGSI_OPCODE_LG2:
1774 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1775 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1776 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1777 break;
1778 case TGSI_OPCODE_COS:
1779 case TGSI_OPCODE_SIN:
1780 val0 = getScratch();
1781 if (mask & 7) {
1782 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1783 mkOp1(op, TYPE_F32, val0, val0);
1784 for (c = 0; c < 3; ++c)
1785 if (dst0[c])
1786 mkMov(dst0[c], val0);
1787 }
1788 if (dst0[3]) {
1789 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1790 mkOp1(op, TYPE_F32, dst0[3], val0);
1791 }
1792 break;
1793 case TGSI_OPCODE_SCS:
1794 if (mask & 3) {
1795 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1796 if (dst0[0])
1797 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1798 if (dst0[1])
1799 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1800 }
1801 if (dst0[2])
1802 loadImm(dst0[2], 0.0f);
1803 if (dst0[3])
1804 loadImm(dst0[3], 1.0f);
1805 break;
1806 case TGSI_OPCODE_EXP:
1807 src0 = fetchSrc(0, 0);
1808 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1809 if (dst0[1])
1810 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1811 if (dst0[0])
1812 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1813 if (dst0[2])
1814 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1815 if (dst0[3])
1816 loadImm(dst0[3], 1.0f);
1817 break;
1818 case TGSI_OPCODE_LOG:
1819 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1820 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1821 if (dst0[0] || dst0[1])
1822 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1823 if (dst0[1]) {
1824 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1825 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1826 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1827 }
1828 if (dst0[3])
1829 loadImm(dst0[3], 1.0f);
1830 break;
1831 case TGSI_OPCODE_DP2:
1832 val0 = buildDot(2);
1833 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1834 mkMov(dst0[c], val0);
1835 break;
1836 case TGSI_OPCODE_DP3:
1837 val0 = buildDot(3);
1838 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1839 mkMov(dst0[c], val0);
1840 break;
1841 case TGSI_OPCODE_DP4:
1842 val0 = buildDot(4);
1843 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1844 mkMov(dst0[c], val0);
1845 break;
1846 case TGSI_OPCODE_DPH:
1847 val0 = buildDot(3);
1848 src1 = fetchSrc(1, 3);
1849 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1850 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1851 mkMov(dst0[c], val0);
1852 break;
1853 case TGSI_OPCODE_DST:
1854 if (dst0[0])
1855 loadImm(dst0[0], 1.0f);
1856 if (dst0[1]) {
1857 src0 = fetchSrc(0, 1);
1858 src1 = fetchSrc(1, 1);
1859 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1860 }
1861 if (dst0[2])
1862 mkMov(dst0[2], fetchSrc(0, 2));
1863 if (dst0[3])
1864 mkMov(dst0[3], fetchSrc(1, 3));
1865 break;
1866 case TGSI_OPCODE_LRP:
1867 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1868 src0 = fetchSrc(0, c);
1869 src1 = fetchSrc(1, c);
1870 src2 = fetchSrc(2, c);
1871 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1872 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1873 }
1874 break;
1875 case TGSI_OPCODE_LIT:
1876 handleLIT(dst0);
1877 break;
1878 case TGSI_OPCODE_XPD:
1879 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1880 if (c < 3) {
1881 val0 = getSSA();
1882 src0 = fetchSrc(1, (c + 1) % 3);
1883 src1 = fetchSrc(0, (c + 2) % 3);
1884 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1885 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1886
1887 src0 = fetchSrc(0, (c + 1) % 3);
1888 src1 = fetchSrc(1, (c + 2) % 3);
1889 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1890 } else {
1891 loadImm(dst0[c], 1.0f);
1892 }
1893 }
1894 break;
1895 case TGSI_OPCODE_SSG:
1896 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1897 src0 = fetchSrc(0, c);
1898 val0 = getScratch();
1899 val1 = getScratch();
1900 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, src0, zero);
1901 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, src0, zero);
1902 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1903 }
1904 break;
1905 case TGSI_OPCODE_UCMP:
1906 case TGSI_OPCODE_CMP:
1907 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1908 src0 = fetchSrc(0, c);
1909 src1 = fetchSrc(1, c);
1910 src2 = fetchSrc(2, c);
1911 if (src1 == src2)
1912 mkMov(dst0[c], src1);
1913 else
1914 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1915 srcTy, dst0[c], src1, src2, src0);
1916 }
1917 break;
1918 case TGSI_OPCODE_FRC:
1919 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1920 src0 = fetchSrc(0, c);
1921 val0 = getScratch();
1922 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1923 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1924 }
1925 break;
1926 case TGSI_OPCODE_ROUND:
1927 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1928 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1929 ->rnd = ROUND_NI;
1930 break;
1931 case TGSI_OPCODE_CLAMP:
1932 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1933 src0 = fetchSrc(0, c);
1934 src1 = fetchSrc(1, c);
1935 src2 = fetchSrc(2, c);
1936 val0 = getScratch();
1937 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1938 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1939 }
1940 break;
1941 case TGSI_OPCODE_SLT:
1942 case TGSI_OPCODE_SGE:
1943 case TGSI_OPCODE_SEQ:
1944 case TGSI_OPCODE_SFL:
1945 case TGSI_OPCODE_SGT:
1946 case TGSI_OPCODE_SLE:
1947 case TGSI_OPCODE_SNE:
1948 case TGSI_OPCODE_STR:
1949 case TGSI_OPCODE_ISGE:
1950 case TGSI_OPCODE_ISLT:
1951 case TGSI_OPCODE_USEQ:
1952 case TGSI_OPCODE_USGE:
1953 case TGSI_OPCODE_USLT:
1954 case TGSI_OPCODE_USNE:
1955 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1956 src0 = fetchSrc(0, c);
1957 src1 = fetchSrc(1, c);
1958 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1959 }
1960 break;
1961 case TGSI_OPCODE_KIL:
1962 val0 = new_LValue(func, FILE_PREDICATE);
1963 for (c = 0; c < 4; ++c) {
1964 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1965 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1966 }
1967 break;
1968 case TGSI_OPCODE_KILP:
1969 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1970 break;
1971 case TGSI_OPCODE_TEX:
1972 case TGSI_OPCODE_TXB:
1973 case TGSI_OPCODE_TXL:
1974 case TGSI_OPCODE_TXP:
1975 // R S L C Dx Dy
1976 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1977 break;
1978 case TGSI_OPCODE_TXD:
1979 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1980 break;
1981 case TGSI_OPCODE_SAMPLE:
1982 case TGSI_OPCODE_SAMPLE_B:
1983 case TGSI_OPCODE_SAMPLE_D:
1984 case TGSI_OPCODE_SAMPLE_L:
1985 case TGSI_OPCODE_SAMPLE_C:
1986 case TGSI_OPCODE_SAMPLE_C_LZ:
1987 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
1988 break;
1989 case TGSI_OPCODE_TXF:
1990 case TGSI_OPCODE_LOAD:
1991 handleTXF(dst0, 1);
1992 break;
1993 case TGSI_OPCODE_TXQ:
1994 case TGSI_OPCODE_RESINFO:
1995 handleTXQ(dst0, TXQ_DIMS);
1996 break;
1997 case TGSI_OPCODE_F2I:
1998 case TGSI_OPCODE_F2U:
1999 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2000 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2001 break;
2002 case TGSI_OPCODE_I2F:
2003 case TGSI_OPCODE_U2F:
2004 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2005 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2006 break;
2007 case TGSI_OPCODE_EMIT:
2008 case TGSI_OPCODE_ENDPRIM:
2009 // get vertex stream if specified (must be immediate)
2010 src0 = tgsi.srcCount() ?
2011 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2012 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2013 break;
2014 case TGSI_OPCODE_IF:
2015 {
2016 BasicBlock *ifBB = new BasicBlock(func);
2017
2018 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2019 condBBs.push(bb);
2020 joinBBs.push(bb);
2021
2022 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2023
2024 setPosition(ifBB, true);
2025 }
2026 break;
2027 case TGSI_OPCODE_ELSE:
2028 {
2029 BasicBlock *elseBB = new BasicBlock(func);
2030 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2031
2032 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2033 condBBs.push(bb);
2034
2035 forkBB->getExit()->asFlow()->target.bb = elseBB;
2036 if (!bb->isTerminated())
2037 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2038
2039 setPosition(elseBB, true);
2040 }
2041 break;
2042 case TGSI_OPCODE_ENDIF:
2043 {
2044 BasicBlock *convBB = new BasicBlock(func);
2045 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2046 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2047
2048 if (!bb->isTerminated()) {
2049 // we only want join if none of the clauses ended with CONT/BREAK/RET
2050 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2051 insertConvergenceOps(convBB, forkBB);
2052 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2053 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2054 }
2055
2056 if (prevBB->getExit()->op == OP_BRA) {
2057 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2058 prevBB->getExit()->asFlow()->target.bb = convBB;
2059 }
2060 setPosition(convBB, true);
2061 }
2062 break;
2063 case TGSI_OPCODE_BGNLOOP:
2064 {
2065 BasicBlock *lbgnBB = new BasicBlock(func);
2066 BasicBlock *lbrkBB = new BasicBlock(func);
2067
2068 loopBBs.push(lbgnBB);
2069 breakBBs.push(lbrkBB);
2070 if (loopBBs.getSize() > func->loopNestingBound)
2071 func->loopNestingBound++;
2072
2073 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2074
2075 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2076 setPosition(lbgnBB, true);
2077 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2078 }
2079 break;
2080 case TGSI_OPCODE_ENDLOOP:
2081 {
2082 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2083
2084 if (!bb->isTerminated()) {
2085 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2086 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2087 }
2088 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2089 }
2090 break;
2091 case TGSI_OPCODE_BRK:
2092 {
2093 if (bb->isTerminated())
2094 break;
2095 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2096 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2097 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2098 }
2099 break;
2100 case TGSI_OPCODE_CONT:
2101 {
2102 if (bb->isTerminated())
2103 break;
2104 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2105 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2106 contBB->explicitCont = true;
2107 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2108 }
2109 break;
2110 case TGSI_OPCODE_BGNSUB:
2111 {
2112 if (!retIPs.getSize()) {
2113 // end of main function
2114 ip = code->scan.num_instructions - 2; // goto END
2115 return true;
2116 }
2117 BasicBlock *entry = new BasicBlock(func);
2118 BasicBlock *leave = new BasicBlock(func);
2119 entryBBs.push(entry);
2120 leaveBBs.push(leave);
2121 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2122 setPosition(entry, true);
2123 }
2124 return true;
2125 case TGSI_OPCODE_ENDSUB:
2126 {
2127 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2128 entryBBs.pop();
2129 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2130 setPosition(leave, true);
2131 ip = retIPs.pop().u.u;
2132 }
2133 return true;
2134 case TGSI_OPCODE_CAL:
2135 // we don't have function declarations, so inline everything
2136 retIPs.push(ip);
2137 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2138 return true;
2139 case TGSI_OPCODE_RET:
2140 {
2141 if (bb->isTerminated())
2142 return true;
2143 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2144 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2145 if (!isEndOfSubroutine(ip + 1)) {
2146 // insert a PRERET at the entry if this is an early return
2147 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2148 preRet->fixed = 1;
2149 entry->insertHead(preRet);
2150 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2151 }
2152 // everything inlined so RET serves only to wrap up the stack
2153 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2154 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2155 }
2156 break;
2157 case TGSI_OPCODE_END:
2158 {
2159 // attach and generate epilogue code
2160 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2161 entryBBs.pop();
2162 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2163 setPosition(epilogue, true);
2164 if (prog->getType() == Program::TYPE_FRAGMENT)
2165 exportOutputs();
2166 if (info->io.genUserClip > 0)
2167 handleUserClipPlanes();
2168 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2169 }
2170 break;
2171 case TGSI_OPCODE_SWITCH:
2172 case TGSI_OPCODE_CASE:
2173 ERROR("switch/case opcode encountered, should have been lowered\n");
2174 abort();
2175 break;
2176 default:
2177 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2178 assert(0);
2179 break;
2180 }
2181
2182 if (tgsi.dstCount()) {
2183 for (c = 0; c < 4; ++c) {
2184 if (!dst0[c])
2185 continue;
2186 if (dst0[c] != rDst0[c])
2187 mkMov(rDst0[c], dst0[c]);
2188 storeDst(0, c, rDst0[c]);
2189 }
2190 }
2191 vtxBaseValid = 0;
2192
2193 return true;
2194 }
2195
2196 void
2197 Converter::handleUserClipPlanes()
2198 {
2199 Value *res[8];
2200 int i, c;
2201
2202 for (c = 0; c < 4; ++c) {
2203 for (i = 0; i < info->io.genUserClip; ++i) {
2204 Value *ucp;
2205 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2206 i * 16 + c * 4), NULL);
2207 if (c == 0)
2208 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2209 else
2210 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2211 }
2212 }
2213
2214 for (i = 0; i < info->io.genUserClip; ++i)
2215 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2216 }
2217
2218 void
2219 Converter::exportOutputs()
2220 {
2221 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2222 for (unsigned int c = 0; c < 4; ++c) {
2223 if (!oData.exists(i, c))
2224 continue;
2225 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2226 info->out[i].slot[c] * 4);
2227 Value *val = oData.load(i, c, NULL);
2228 if (val)
2229 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2230 }
2231 }
2232 }
2233
2234 Converter::Converter(Program *ir, const tgsi::Source *src)
2235 : code(src),
2236 tgsi(NULL),
2237 tData(this), aData(this), pData(this), oData(this)
2238 {
2239 prog = ir;
2240 info = code->info;
2241
2242 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2243
2244 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2245 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2246 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2247 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2248
2249 lData = NULL;
2250 iData = NULL;
2251
2252 zero = mkImm((uint32_t)0);
2253
2254 vtxBaseValid = 0;
2255 }
2256
2257 Converter::~Converter()
2258 {
2259 if (lData)
2260 delete[] lData;
2261 if (iData)
2262 delete[] iData;
2263 }
2264
2265 bool
2266 Converter::run()
2267 {
2268 BasicBlock *entry = new BasicBlock(prog->main);
2269 BasicBlock *leave = new BasicBlock(prog->main);
2270
2271 if (code->tempArrayCount && !lData) {
2272 uint32_t volume = 0;
2273 lData = new DataArray[code->tempArrayCount];
2274 if (!lData)
2275 return false;
2276 for (int i = 0; i < code->tempArrayCount; ++i) {
2277 int len = code->tempArrays[i].u32 >> 2;
2278 int dim = code->tempArrays[i].u32 & 3;
2279 lData[i].setParent(this);
2280 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2281 volume += (len * dim * 4 + 0xf) & ~0xf;
2282 }
2283 }
2284 if (code->immdArrayCount && !iData) {
2285 uint32_t volume = 0;
2286 iData = new DataArray[code->immdArrayCount];
2287 if (!iData)
2288 return false;
2289 for (int i = 0; i < code->immdArrayCount; ++i) {
2290 int len = code->immdArrays[i].u32 >> 2;
2291 int dim = code->immdArrays[i].u32 & 3;
2292 iData[i].setParent(this);
2293 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2294 volume += (len * dim * 4 + 0xf) & ~0xf;
2295 }
2296 }
2297
2298 prog->main->setEntry(entry);
2299 prog->main->setExit(leave);
2300
2301 setPosition(entry, true);
2302 entryBBs.push(entry);
2303 leaveBBs.push(leave);
2304
2305 if (info->io.genUserClip > 0) {
2306 for (int c = 0; c < 4; ++c)
2307 clipVtx[c] = getScratch();
2308 }
2309
2310 if (prog->getType() == Program::TYPE_FRAGMENT) {
2311 Symbol *sv = mkSysVal(SV_POSITION, 3);
2312 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2313 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2314 }
2315
2316 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2317 if (!handleInstruction(&code->insns[ip]))
2318 return false;
2319 }
2320 return true;
2321 }
2322
2323 } // unnamed namespace
2324
2325 namespace nv50_ir {
2326
2327 bool
2328 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2329 {
2330 tgsi::Source src(info);
2331 if (!src.scanSource())
2332 return false;
2333
2334 Converter builder(this, &src);
2335 return builder.run();
2336 }
2337
2338 } // namespace nv50_ir