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nv50/ir: add function for splitting a BasicBlock
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
325 default:
326 assert(0);
327 return nv50_ir::SV_CLOCK;
328 }
329 }
330
331 #define NV50_IR_TEX_TARG_CASE(a, b) \
332 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
333
334 static nv50_ir::TexTarget translateTexture(uint tex)
335 {
336 switch (tex) {
337 NV50_IR_TEX_TARG_CASE(1D, 1D);
338 NV50_IR_TEX_TARG_CASE(2D, 2D);
339 NV50_IR_TEX_TARG_CASE(3D, 3D);
340 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
341 NV50_IR_TEX_TARG_CASE(RECT, RECT);
342 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
344 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
348 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
349 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
350
351 case TGSI_TEXTURE_UNKNOWN:
352 default:
353 assert(!"invalid texture target");
354 return nv50_ir::TEX_TARGET_2D;
355 }
356 }
357
358 nv50_ir::DataType Instruction::inferSrcType() const
359 {
360 switch (getOpcode()) {
361 case TGSI_OPCODE_AND:
362 case TGSI_OPCODE_OR:
363 case TGSI_OPCODE_XOR:
364 case TGSI_OPCODE_NOT:
365 case TGSI_OPCODE_U2F:
366 case TGSI_OPCODE_UADD:
367 case TGSI_OPCODE_UDIV:
368 case TGSI_OPCODE_UMOD:
369 case TGSI_OPCODE_UMAD:
370 case TGSI_OPCODE_UMUL:
371 case TGSI_OPCODE_UMAX:
372 case TGSI_OPCODE_UMIN:
373 case TGSI_OPCODE_USEQ:
374 case TGSI_OPCODE_USGE:
375 case TGSI_OPCODE_USLT:
376 case TGSI_OPCODE_USNE:
377 case TGSI_OPCODE_USHR:
378 case TGSI_OPCODE_UCMP:
379 return nv50_ir::TYPE_U32;
380 case TGSI_OPCODE_I2F:
381 case TGSI_OPCODE_IDIV:
382 case TGSI_OPCODE_IMAX:
383 case TGSI_OPCODE_IMIN:
384 case TGSI_OPCODE_IABS:
385 case TGSI_OPCODE_INEG:
386 case TGSI_OPCODE_ISGE:
387 case TGSI_OPCODE_ISHR:
388 case TGSI_OPCODE_ISLT:
389 case TGSI_OPCODE_ISSG:
390 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
391 case TGSI_OPCODE_MOD:
392 case TGSI_OPCODE_UARL:
393 return nv50_ir::TYPE_S32;
394 default:
395 return nv50_ir::TYPE_F32;
396 }
397 }
398
399 nv50_ir::DataType Instruction::inferDstType() const
400 {
401 switch (getOpcode()) {
402 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
403 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
404 case TGSI_OPCODE_I2F:
405 case TGSI_OPCODE_U2F:
406 return nv50_ir::TYPE_F32;
407 default:
408 return inferSrcType();
409 }
410 }
411
412 nv50_ir::CondCode Instruction::getSetCond() const
413 {
414 using namespace nv50_ir;
415
416 switch (getOpcode()) {
417 case TGSI_OPCODE_SLT:
418 case TGSI_OPCODE_ISLT:
419 case TGSI_OPCODE_USLT:
420 return CC_LT;
421 case TGSI_OPCODE_SLE:
422 return CC_LE;
423 case TGSI_OPCODE_SGE:
424 case TGSI_OPCODE_ISGE:
425 case TGSI_OPCODE_USGE:
426 return CC_GE;
427 case TGSI_OPCODE_SGT:
428 return CC_GT;
429 case TGSI_OPCODE_SEQ:
430 case TGSI_OPCODE_USEQ:
431 return CC_EQ;
432 case TGSI_OPCODE_SNE:
433 return CC_NEU;
434 case TGSI_OPCODE_USNE:
435 return CC_NE;
436 case TGSI_OPCODE_SFL:
437 return CC_NEVER;
438 case TGSI_OPCODE_STR:
439 default:
440 return CC_ALWAYS;
441 }
442 }
443
444 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
445
446 static nv50_ir::operation translateOpcode(uint opcode)
447 {
448 switch (opcode) {
449 NV50_IR_OPCODE_CASE(ARL, SHL);
450 NV50_IR_OPCODE_CASE(MOV, MOV);
451
452 NV50_IR_OPCODE_CASE(RCP, RCP);
453 NV50_IR_OPCODE_CASE(RSQ, RSQ);
454
455 NV50_IR_OPCODE_CASE(MUL, MUL);
456 NV50_IR_OPCODE_CASE(ADD, ADD);
457
458 NV50_IR_OPCODE_CASE(MIN, MIN);
459 NV50_IR_OPCODE_CASE(MAX, MAX);
460 NV50_IR_OPCODE_CASE(SLT, SET);
461 NV50_IR_OPCODE_CASE(SGE, SET);
462 NV50_IR_OPCODE_CASE(MAD, MAD);
463 NV50_IR_OPCODE_CASE(SUB, SUB);
464
465 NV50_IR_OPCODE_CASE(FLR, FLOOR);
466 NV50_IR_OPCODE_CASE(ROUND, CVT);
467 NV50_IR_OPCODE_CASE(EX2, EX2);
468 NV50_IR_OPCODE_CASE(LG2, LG2);
469 NV50_IR_OPCODE_CASE(POW, POW);
470
471 NV50_IR_OPCODE_CASE(ABS, ABS);
472
473 NV50_IR_OPCODE_CASE(COS, COS);
474 NV50_IR_OPCODE_CASE(DDX, DFDX);
475 NV50_IR_OPCODE_CASE(DDY, DFDY);
476 NV50_IR_OPCODE_CASE(KILP, DISCARD);
477
478 NV50_IR_OPCODE_CASE(SEQ, SET);
479 NV50_IR_OPCODE_CASE(SFL, SET);
480 NV50_IR_OPCODE_CASE(SGT, SET);
481 NV50_IR_OPCODE_CASE(SIN, SIN);
482 NV50_IR_OPCODE_CASE(SLE, SET);
483 NV50_IR_OPCODE_CASE(SNE, SET);
484 NV50_IR_OPCODE_CASE(STR, SET);
485 NV50_IR_OPCODE_CASE(TEX, TEX);
486 NV50_IR_OPCODE_CASE(TXD, TXD);
487 NV50_IR_OPCODE_CASE(TXP, TEX);
488
489 NV50_IR_OPCODE_CASE(BRA, BRA);
490 NV50_IR_OPCODE_CASE(CAL, CALL);
491 NV50_IR_OPCODE_CASE(RET, RET);
492 NV50_IR_OPCODE_CASE(CMP, SLCT);
493
494 NV50_IR_OPCODE_CASE(TXB, TXB);
495
496 NV50_IR_OPCODE_CASE(DIV, DIV);
497
498 NV50_IR_OPCODE_CASE(TXL, TXL);
499
500 NV50_IR_OPCODE_CASE(CEIL, CEIL);
501 NV50_IR_OPCODE_CASE(I2F, CVT);
502 NV50_IR_OPCODE_CASE(NOT, NOT);
503 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
504 NV50_IR_OPCODE_CASE(SHL, SHL);
505
506 NV50_IR_OPCODE_CASE(AND, AND);
507 NV50_IR_OPCODE_CASE(OR, OR);
508 NV50_IR_OPCODE_CASE(MOD, MOD);
509 NV50_IR_OPCODE_CASE(XOR, XOR);
510 NV50_IR_OPCODE_CASE(SAD, SAD);
511 NV50_IR_OPCODE_CASE(TXF, TXF);
512 NV50_IR_OPCODE_CASE(TXQ, TXQ);
513
514 NV50_IR_OPCODE_CASE(EMIT, EMIT);
515 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
516
517 NV50_IR_OPCODE_CASE(KIL, DISCARD);
518
519 NV50_IR_OPCODE_CASE(F2I, CVT);
520 NV50_IR_OPCODE_CASE(IDIV, DIV);
521 NV50_IR_OPCODE_CASE(IMAX, MAX);
522 NV50_IR_OPCODE_CASE(IMIN, MIN);
523 NV50_IR_OPCODE_CASE(IABS, ABS);
524 NV50_IR_OPCODE_CASE(INEG, NEG);
525 NV50_IR_OPCODE_CASE(ISGE, SET);
526 NV50_IR_OPCODE_CASE(ISHR, SHR);
527 NV50_IR_OPCODE_CASE(ISLT, SET);
528 NV50_IR_OPCODE_CASE(F2U, CVT);
529 NV50_IR_OPCODE_CASE(U2F, CVT);
530 NV50_IR_OPCODE_CASE(UADD, ADD);
531 NV50_IR_OPCODE_CASE(UDIV, DIV);
532 NV50_IR_OPCODE_CASE(UMAD, MAD);
533 NV50_IR_OPCODE_CASE(UMAX, MAX);
534 NV50_IR_OPCODE_CASE(UMIN, MIN);
535 NV50_IR_OPCODE_CASE(UMOD, MOD);
536 NV50_IR_OPCODE_CASE(UMUL, MUL);
537 NV50_IR_OPCODE_CASE(USEQ, SET);
538 NV50_IR_OPCODE_CASE(USGE, SET);
539 NV50_IR_OPCODE_CASE(USHR, SHR);
540 NV50_IR_OPCODE_CASE(USLT, SET);
541 NV50_IR_OPCODE_CASE(USNE, SET);
542
543 NV50_IR_OPCODE_CASE(LOAD, TXF);
544 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
545 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
546 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
547 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
548 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
549 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
550 NV50_IR_OPCODE_CASE(GATHER4, TXG);
551 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
552
553 NV50_IR_OPCODE_CASE(END, EXIT);
554
555 default:
556 return nv50_ir::OP_NOP;
557 }
558 }
559
560 bool Instruction::checkDstSrcAliasing() const
561 {
562 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
563 return false;
564
565 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
566 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
567 break;
568 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
569 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
570 return true;
571 }
572 return false;
573 }
574
575 class Source
576 {
577 public:
578 Source(struct nv50_ir_prog_info *);
579 ~Source();
580
581 struct Subroutine
582 {
583 unsigned pc;
584 };
585
586 public:
587 bool scanSource();
588 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
589
590 public:
591 struct tgsi_shader_info scan;
592 struct tgsi_full_instruction *insns;
593 const struct tgsi_token *tokens;
594 struct nv50_ir_prog_info *info;
595
596 nv50_ir::DynArray tempArrays;
597 nv50_ir::DynArray immdArrays;
598 int tempArrayCount;
599 int immdArrayCount;
600
601 bool mainTempsInLMem;
602
603 int clipVertexOutput;
604
605 uint8_t *resourceTargets; // TGSI_TEXTURE_*
606 unsigned resourceCount;
607
608 Subroutine *subroutines;
609 unsigned subroutineCount;
610
611 private:
612 int inferSysValDirection(unsigned sn) const;
613 bool scanDeclaration(const struct tgsi_full_declaration *);
614 bool scanInstruction(const struct tgsi_full_instruction *);
615 void scanProperty(const struct tgsi_full_property *);
616 void scanImmediate(const struct tgsi_full_immediate *);
617
618 inline bool isEdgeFlagPassthrough(const Instruction&) const;
619 };
620
621 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
622 {
623 tokens = (const struct tgsi_token *)info->bin.source;
624
625 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
626 tgsi_dump(tokens, 0);
627
628 resourceTargets = NULL;
629 subroutines = NULL;
630
631 mainTempsInLMem = FALSE;
632 }
633
634 Source::~Source()
635 {
636 if (insns)
637 FREE(insns);
638
639 if (info->immd.data)
640 FREE(info->immd.data);
641 if (info->immd.type)
642 FREE(info->immd.type);
643
644 if (resourceTargets)
645 delete[] resourceTargets;
646 if (subroutines)
647 delete[] subroutines;
648 }
649
650 bool Source::scanSource()
651 {
652 unsigned insnCount = 0;
653 unsigned subrCount = 0;
654 struct tgsi_parse_context parse;
655
656 tgsi_scan_shader(tokens, &scan);
657
658 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
659 sizeof(insns[0]));
660 if (!insns)
661 return false;
662
663 clipVertexOutput = -1;
664
665 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
666 resourceTargets = new uint8_t[resourceCount];
667
668 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
669 subroutines = new Subroutine[subroutineCount];
670
671 info->immd.bufSize = 0;
672 tempArrayCount = 0;
673 immdArrayCount = 0;
674
675 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
676 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
677 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
678
679 if (info->type == PIPE_SHADER_FRAGMENT) {
680 info->prop.fp.writesDepth = scan.writes_z;
681 info->prop.fp.usesDiscard = scan.uses_kill;
682 } else
683 if (info->type == PIPE_SHADER_GEOMETRY) {
684 info->prop.gp.instanceCount = 1; // default value
685 }
686
687 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
688 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
689
690 tgsi_parse_init(&parse, tokens);
691 while (!tgsi_parse_end_of_tokens(&parse)) {
692 tgsi_parse_token(&parse);
693
694 switch (parse.FullToken.Token.Type) {
695 case TGSI_TOKEN_TYPE_IMMEDIATE:
696 scanImmediate(&parse.FullToken.FullImmediate);
697 break;
698 case TGSI_TOKEN_TYPE_DECLARATION:
699 scanDeclaration(&parse.FullToken.FullDeclaration);
700 break;
701 case TGSI_TOKEN_TYPE_INSTRUCTION:
702 insns[insnCount++] = parse.FullToken.FullInstruction;
703 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
704 subroutines[++subrCount].pc = insnCount - 1;
705 else
706 scanInstruction(&parse.FullToken.FullInstruction);
707 break;
708 case TGSI_TOKEN_TYPE_PROPERTY:
709 scanProperty(&parse.FullToken.FullProperty);
710 break;
711 default:
712 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
713 break;
714 }
715 }
716 tgsi_parse_free(&parse);
717
718 if (mainTempsInLMem)
719 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
720
721 if (info->io.genUserClip > 0)
722 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
723
724 return info->assignSlots(info) == 0;
725 }
726
727 void Source::scanProperty(const struct tgsi_full_property *prop)
728 {
729 switch (prop->Property.PropertyName) {
730 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
731 info->prop.gp.outputPrim = prop->u[0].Data;
732 break;
733 case TGSI_PROPERTY_GS_INPUT_PRIM:
734 info->prop.gp.inputPrim = prop->u[0].Data;
735 break;
736 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
737 info->prop.gp.maxVertices = prop->u[0].Data;
738 break;
739 #if 0
740 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
741 info->prop.gp.instanceCount = prop->u[0].Data;
742 break;
743 #endif
744 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
745 info->prop.fp.separateFragData = TRUE;
746 break;
747 case TGSI_PROPERTY_FS_COORD_ORIGIN:
748 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
749 // we don't care
750 break;
751 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
752 info->io.genUserClip = -1;
753 break;
754 default:
755 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
756 break;
757 }
758 }
759
760 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
761 {
762 const unsigned n = info->immd.count++;
763
764 assert(n < scan.immediate_count);
765
766 for (int c = 0; c < 4; ++c)
767 info->immd.data[n * 4 + c] = imm->u[c].Uint;
768
769 info->immd.type[n] = imm->Immediate.DataType;
770 }
771
772 int Source::inferSysValDirection(unsigned sn) const
773 {
774 switch (sn) {
775 case TGSI_SEMANTIC_INSTANCEID:
776 case TGSI_SEMANTIC_VERTEXID:
777 return 1;
778 #if 0
779 case TGSI_SEMANTIC_LAYER:
780 case TGSI_SEMANTIC_VIEWPORTINDEX:
781 return 0;
782 #endif
783 case TGSI_SEMANTIC_PRIMID:
784 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
785 default:
786 return 0;
787 }
788 }
789
790 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
791 {
792 unsigned i;
793 unsigned sn = TGSI_SEMANTIC_GENERIC;
794 unsigned si = 0;
795 const unsigned first = decl->Range.First, last = decl->Range.Last;
796
797 if (decl->Declaration.Semantic) {
798 sn = decl->Semantic.Name;
799 si = decl->Semantic.Index;
800 }
801
802 switch (decl->Declaration.File) {
803 case TGSI_FILE_INPUT:
804 if (info->type == PIPE_SHADER_VERTEX) {
805 // all vertex attributes are equal
806 for (i = first; i <= last; ++i) {
807 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
808 info->in[i].si = i;
809 }
810 } else {
811 for (i = first; i <= last; ++i, ++si) {
812 info->in[i].id = i;
813 info->in[i].sn = sn;
814 info->in[i].si = si;
815 if (info->type == PIPE_SHADER_FRAGMENT) {
816 // translate interpolation mode
817 switch (decl->Declaration.Interpolate) {
818 case TGSI_INTERPOLATE_CONSTANT:
819 info->in[i].flat = 1;
820 break;
821 case TGSI_INTERPOLATE_COLOR:
822 info->in[i].sc = 1;
823 break;
824 case TGSI_INTERPOLATE_LINEAR:
825 info->in[i].linear = 1;
826 break;
827 default:
828 break;
829 }
830 if (decl->Declaration.Centroid)
831 info->in[i].centroid = 1;
832 }
833 }
834 }
835 break;
836 case TGSI_FILE_OUTPUT:
837 for (i = first; i <= last; ++i, ++si) {
838 switch (sn) {
839 case TGSI_SEMANTIC_POSITION:
840 if (info->type == PIPE_SHADER_FRAGMENT)
841 info->io.fragDepth = i;
842 else
843 if (clipVertexOutput < 0)
844 clipVertexOutput = i;
845 break;
846 case TGSI_SEMANTIC_COLOR:
847 if (info->type == PIPE_SHADER_FRAGMENT)
848 info->prop.fp.numColourResults++;
849 break;
850 case TGSI_SEMANTIC_EDGEFLAG:
851 info->io.edgeFlagOut = i;
852 break;
853 case TGSI_SEMANTIC_CLIPVERTEX:
854 clipVertexOutput = i;
855 break;
856 case TGSI_SEMANTIC_CLIPDIST:
857 info->io.clipDistanceMask |=
858 decl->Declaration.UsageMask << (si * 4);
859 info->io.genUserClip = -1;
860 break;
861 default:
862 break;
863 }
864 info->out[i].id = i;
865 info->out[i].sn = sn;
866 info->out[i].si = si;
867 }
868 break;
869 case TGSI_FILE_SYSTEM_VALUE:
870 switch (sn) {
871 case TGSI_SEMANTIC_VERTEXID:
872 info->io.vertexId = first;
873 break;
874 default:
875 break;
876 }
877 for (i = first; i <= last; ++i, ++si) {
878 info->sv[i].sn = sn;
879 info->sv[i].si = si;
880 info->sv[i].input = inferSysValDirection(sn);
881 }
882 break;
883 case TGSI_FILE_RESOURCE:
884 for (i = first; i <= last; ++i)
885 resourceTargets[i] = decl->Resource.Resource;
886 break;
887 case TGSI_FILE_IMMEDIATE_ARRAY:
888 {
889 if (decl->Dim.Index2D >= immdArrayCount)
890 immdArrayCount = decl->Dim.Index2D + 1;
891 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
892 int c;
893 uint32_t base, count;
894 switch (decl->Declaration.UsageMask) {
895 case 0x1: c = 1; break;
896 case 0x3: c = 2; break;
897 default:
898 c = 4;
899 break;
900 }
901 immdArrays[decl->Dim.Index2D].u32 |= c;
902 count = (last + 1) * c;
903 base = info->immd.bufSize / 4;
904 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
905 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
906 info->immd.bufSize);
907 // NOTE: this assumes array declarations are ordered by Dim.Index2D
908 for (i = 0; i < count; ++i)
909 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
910 }
911 break;
912 case TGSI_FILE_TEMPORARY_ARRAY:
913 {
914 if (decl->Dim.Index2D >= tempArrayCount)
915 tempArrayCount = decl->Dim.Index2D + 1;
916 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
917 int c;
918 uint32_t count;
919 switch (decl->Declaration.UsageMask) {
920 case 0x1: c = 1; break;
921 case 0x3: c = 2; break;
922 default:
923 c = 4;
924 break;
925 }
926 tempArrays[decl->Dim.Index2D].u32 |= c;
927 count = (last + 1) * c;
928 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
929 }
930 break;
931 case TGSI_FILE_NULL:
932 case TGSI_FILE_TEMPORARY:
933 case TGSI_FILE_ADDRESS:
934 case TGSI_FILE_CONSTANT:
935 case TGSI_FILE_IMMEDIATE:
936 case TGSI_FILE_PREDICATE:
937 case TGSI_FILE_SAMPLER:
938 break;
939 default:
940 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
941 return false;
942 }
943 return true;
944 }
945
946 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
947 {
948 return insn.getOpcode() == TGSI_OPCODE_MOV &&
949 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
950 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
951 }
952
953 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
954 {
955 Instruction insn(inst);
956
957 if (insn.dstCount()) {
958 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
959 Instruction::DstRegister dst = insn.getDst(0);
960
961 if (dst.isIndirect(0))
962 for (unsigned i = 0; i < info->numOutputs; ++i)
963 info->out[i].mask = 0xf;
964 else
965 info->out[dst.getIndex(0)].mask |= dst.getMask();
966
967 if (isEdgeFlagPassthrough(insn))
968 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
969 } else
970 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
971 if (insn.getDst(0).isIndirect(0))
972 mainTempsInLMem = TRUE;
973 }
974 }
975
976 for (unsigned s = 0; s < insn.srcCount(); ++s) {
977 Instruction::SrcRegister src = insn.getSrc(s);
978 if (src.getFile() == TGSI_FILE_TEMPORARY)
979 if (src.isIndirect(0))
980 mainTempsInLMem = TRUE;
981 if (src.getFile() != TGSI_FILE_INPUT)
982 continue;
983 unsigned mask = insn.srcMask(s);
984
985 if (src.isIndirect(0)) {
986 for (unsigned i = 0; i < info->numInputs; ++i)
987 info->in[i].mask = 0xf;
988 } else {
989 for (unsigned c = 0; c < 4; ++c) {
990 if (!(mask & (1 << c)))
991 continue;
992 int k = src.getSwizzle(c);
993 int i = src.getIndex(0);
994 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
995 if (k <= TGSI_SWIZZLE_W)
996 info->in[i].mask |= 1 << k;
997 }
998 }
999 }
1000 return true;
1001 }
1002
1003 nv50_ir::TexInstruction::Target
1004 Instruction::getTexture(const tgsi::Source *code, int s) const
1005 {
1006 if (insn->Instruction.Texture) {
1007 return translateTexture(insn->Texture.Texture);
1008 } else {
1009 // XXX: indirect access
1010 unsigned int r = getSrc(s).getIndex(0);
1011 assert(r < code->resourceCount);
1012 return translateTexture(code->resourceTargets[r]);
1013 }
1014 }
1015
1016 } // namespace tgsi
1017
1018 namespace {
1019
1020 using namespace nv50_ir;
1021
1022 class Converter : public BuildUtil
1023 {
1024 public:
1025 Converter(Program *, const tgsi::Source *);
1026 ~Converter();
1027
1028 bool run();
1029
1030 private:
1031 Value *getVertexBase(int s);
1032 Value *fetchSrc(int s, int c);
1033 Value *acquireDst(int d, int c);
1034 void storeDst(int d, int c, Value *);
1035
1036 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1037 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1038 Value *val, Value *ptr);
1039
1040 Value *applySrcMod(Value *, int s, int c);
1041
1042 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1043 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1044 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1045
1046 bool handleInstruction(const struct tgsi_full_instruction *);
1047 void exportOutputs();
1048 inline bool isEndOfSubroutine(uint ip);
1049
1050 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1051
1052 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1053 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1054 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1055 void handleTXF(Value *dst0[4], int R);
1056 void handleTXQ(Value *dst0[4], enum TexQuery);
1057 void handleLIT(Value *dst0[4]);
1058 void handleUserClipPlanes();
1059
1060 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1061
1062 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1063
1064 Value *buildDot(int dim);
1065
1066 private:
1067 const struct tgsi::Source *code;
1068 const struct nv50_ir_prog_info *info;
1069
1070 uint ip; // instruction pointer
1071
1072 tgsi::Instruction tgsi;
1073
1074 DataType dstTy;
1075 DataType srcTy;
1076
1077 DataArray tData; // TGSI_FILE_TEMPORARY
1078 DataArray aData; // TGSI_FILE_ADDRESS
1079 DataArray pData; // TGSI_FILE_PREDICATE
1080 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1081 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1082 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1083
1084 Value *zero;
1085 Value *fragCoord[4];
1086 Value *clipVtx[4];
1087
1088 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1089 uint8_t vtxBaseValid;
1090
1091 Stack condBBs; // fork BB, then else clause BB
1092 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1093 Stack loopBBs; // loop headers
1094 Stack breakBBs; // end of / after loop
1095 Stack entryBBs; // start of current (inlined) subroutine
1096 Stack leaveBBs; // end of current (inlined) subroutine
1097 Stack retIPs; // return instruction pointer
1098 };
1099
1100 Symbol *
1101 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1102 {
1103 const int swz = src.getSwizzle(c);
1104
1105 return makeSym(src.getFile(),
1106 src.is2D() ? src.getIndex(1) : 0,
1107 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1108 src.getIndex(0) * 16 + swz * 4);
1109 }
1110
1111 Symbol *
1112 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1113 {
1114 return makeSym(dst.getFile(),
1115 dst.is2D() ? dst.getIndex(1) : 0,
1116 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1117 dst.getIndex(0) * 16 + c * 4);
1118 }
1119
1120 Symbol *
1121 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1122 {
1123 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1124
1125 sym->reg.fileIndex = fileIdx;
1126
1127 if (idx >= 0) {
1128 if (sym->reg.file == FILE_SHADER_INPUT)
1129 sym->setOffset(info->in[idx].slot[c] * 4);
1130 else
1131 if (sym->reg.file == FILE_SHADER_OUTPUT)
1132 sym->setOffset(info->out[idx].slot[c] * 4);
1133 else
1134 if (sym->reg.file == FILE_SYSTEM_VALUE)
1135 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1136 else
1137 sym->setOffset(address);
1138 } else {
1139 sym->setOffset(address);
1140 }
1141 return sym;
1142 }
1143
1144 static inline uint8_t
1145 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1146 {
1147 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1148
1149 if (var->flat)
1150 mode = NV50_IR_INTERP_FLAT;
1151 else
1152 if (var->linear)
1153 mode = NV50_IR_INTERP_LINEAR;
1154 else
1155 if (var->sc)
1156 mode = NV50_IR_INTERP_SC;
1157
1158 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1159 ? OP_PINTERP : OP_LINTERP;
1160
1161 if (var->centroid)
1162 mode |= NV50_IR_INTERP_CENTROID;
1163
1164 return mode;
1165 }
1166
1167 Value *
1168 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1169 {
1170 operation op;
1171
1172 // XXX: no way to know interpolation mode if we don't know what's accessed
1173 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1174 src.getIndex(0)], op);
1175
1176 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1177
1178 insn->setDef(0, getScratch());
1179 insn->setSrc(0, srcToSym(src, c));
1180 if (op == OP_PINTERP)
1181 insn->setSrc(1, fragCoord[3]);
1182 if (ptr)
1183 insn->setIndirect(0, 0, ptr);
1184
1185 insn->setInterpolate(mode);
1186
1187 bb->insertTail(insn);
1188 return insn->getDef(0);
1189 }
1190
1191 Value *
1192 Converter::applySrcMod(Value *val, int s, int c)
1193 {
1194 Modifier m = tgsi.getSrc(s).getMod(c);
1195 DataType ty = tgsi.inferSrcType();
1196
1197 if (m & Modifier(NV50_IR_MOD_ABS))
1198 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1199
1200 if (m & Modifier(NV50_IR_MOD_NEG))
1201 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1202
1203 return val;
1204 }
1205
1206 Value *
1207 Converter::getVertexBase(int s)
1208 {
1209 assert(s < 5);
1210 if (!(vtxBaseValid & (1 << s))) {
1211 const int index = tgsi.getSrc(s).getIndex(1);
1212 Value *rel = NULL;
1213 if (tgsi.getSrc(s).isIndirect(1))
1214 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1215 vtxBaseValid |= 1 << s;
1216 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1217 }
1218 return vtxBase[s];
1219 }
1220
1221 Value *
1222 Converter::fetchSrc(int s, int c)
1223 {
1224 Value *res;
1225 Value *ptr = NULL, *dimRel = NULL;
1226
1227 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1228
1229 if (src.isIndirect(0))
1230 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1231
1232 if (src.is2D()) {
1233 switch (src.getFile()) {
1234 case TGSI_FILE_INPUT:
1235 dimRel = getVertexBase(s);
1236 break;
1237 case TGSI_FILE_CONSTANT:
1238 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1239 if (src.isIndirect(1))
1240 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1241 break;
1242 default:
1243 break;
1244 }
1245 }
1246
1247 res = fetchSrc(src, c, ptr);
1248
1249 if (dimRel)
1250 res->getInsn()->setIndirect(0, 1, dimRel);
1251
1252 return applySrcMod(res, s, c);
1253 }
1254
1255 Value *
1256 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1257 {
1258 const int idx = src.getIndex(0);
1259 const int swz = src.getSwizzle(c);
1260
1261 switch (src.getFile()) {
1262 case TGSI_FILE_TEMPORARY:
1263 return tData.load(idx, swz, ptr);
1264 case TGSI_FILE_PREDICATE:
1265 return pData.load(idx, swz, ptr);
1266 case TGSI_FILE_ADDRESS:
1267 return aData.load(idx, swz, ptr);
1268
1269 case TGSI_FILE_TEMPORARY_ARRAY:
1270 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1271 return lData[src.getIndex(1)].load(idx, swz, ptr);
1272 case TGSI_FILE_IMMEDIATE_ARRAY:
1273 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1274 return iData[src.getIndex(1)].load(idx, swz, ptr);
1275
1276 case TGSI_FILE_IMMEDIATE:
1277 assert(!ptr);
1278 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1279
1280 case TGSI_FILE_CONSTANT:
1281 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1282
1283 case TGSI_FILE_INPUT:
1284 if (prog->getType() == Program::TYPE_FRAGMENT) {
1285 // don't load masked inputs, won't be assigned a slot
1286 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1287 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1288 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1289 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1290 return interpolate(src, c, ptr);
1291 }
1292 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1293
1294 case TGSI_FILE_SYSTEM_VALUE:
1295 assert(!ptr);
1296 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1297
1298 case TGSI_FILE_OUTPUT:
1299 case TGSI_FILE_RESOURCE:
1300 case TGSI_FILE_SAMPLER:
1301 case TGSI_FILE_NULL:
1302 default:
1303 assert(!"invalid/unhandled TGSI source file");
1304 return NULL;
1305 }
1306 }
1307
1308 Value *
1309 Converter::acquireDst(int d, int c)
1310 {
1311 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1312
1313 if (dst.isMasked(c))
1314 return NULL;
1315 if (dst.isIndirect(0))
1316 return getScratch();
1317
1318 const int idx = dst.getIndex(0);
1319
1320 switch (dst.getFile()) {
1321 case TGSI_FILE_TEMPORARY:
1322 return tData.acquire(idx, c);
1323 case TGSI_FILE_TEMPORARY_ARRAY:
1324 return getScratch();
1325 case TGSI_FILE_PREDICATE:
1326 return pData.acquire(idx, c);
1327 case TGSI_FILE_ADDRESS:
1328 return aData.acquire(idx, c);
1329
1330 case TGSI_FILE_OUTPUT:
1331 if (prog->getType() == Program::TYPE_FRAGMENT)
1332 return oData.acquire(idx, c);
1333 // fall through
1334 case TGSI_FILE_SYSTEM_VALUE:
1335 return getScratch();
1336
1337 default:
1338 assert(!"invalid dst file");
1339 return NULL;
1340 }
1341 }
1342
1343 void
1344 Converter::storeDst(int d, int c, Value *val)
1345 {
1346 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1347
1348 switch (tgsi.getSaturate()) {
1349 case TGSI_SAT_NONE:
1350 break;
1351 case TGSI_SAT_ZERO_ONE:
1352 mkOp1(OP_SAT, dstTy, val, val);
1353 break;
1354 case TGSI_SAT_MINUS_PLUS_ONE:
1355 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1356 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1357 break;
1358 default:
1359 assert(!"invalid saturation mode");
1360 break;
1361 }
1362
1363 Value *ptr = dst.isIndirect(0) ?
1364 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1365
1366 if (info->io.genUserClip > 0 &&
1367 dst.getFile() == TGSI_FILE_OUTPUT &&
1368 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1369 mkMov(clipVtx[c], val);
1370 val = clipVtx[c];
1371 }
1372
1373 storeDst(dst, c, val, ptr);
1374 }
1375
1376 void
1377 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1378 Value *val, Value *ptr)
1379 {
1380 const int idx = dst.getIndex(0);
1381
1382 switch (dst.getFile()) {
1383 case TGSI_FILE_TEMPORARY:
1384 tData.store(idx, c, ptr, val);
1385 break;
1386 case TGSI_FILE_TEMPORARY_ARRAY:
1387 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1388 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1389 break;
1390 case TGSI_FILE_PREDICATE:
1391 pData.store(idx, c, ptr, val);
1392 break;
1393 case TGSI_FILE_ADDRESS:
1394 aData.store(idx, c, ptr, val);
1395 break;
1396
1397 case TGSI_FILE_OUTPUT:
1398 if (prog->getType() == Program::TYPE_FRAGMENT)
1399 oData.store(idx, c, ptr, val);
1400 else
1401 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1402 break;
1403
1404 case TGSI_FILE_SYSTEM_VALUE:
1405 assert(!ptr);
1406 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1407 break;
1408
1409 default:
1410 assert(!"invalid dst file");
1411 break;
1412 }
1413 }
1414
1415 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1416 for (chan = 0; chan < 4; ++chan) \
1417 if (!inst.getDst(d).isMasked(chan))
1418
1419 Value *
1420 Converter::buildDot(int dim)
1421 {
1422 assert(dim > 0);
1423
1424 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1425 Value *dotp = getScratch();
1426
1427 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1428
1429 for (int c = 1; c < dim; ++c) {
1430 src0 = fetchSrc(0, c);
1431 src1 = fetchSrc(1, c);
1432 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1433 }
1434 return dotp;
1435 }
1436
1437 void
1438 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1439 {
1440 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1441 join->fixed = 1;
1442 conv->insertHead(join);
1443
1444 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1445 fork->insertBefore(fork->getExit(), fork->joinAt);
1446 }
1447
1448 void
1449 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1450 {
1451 unsigned rIdx = 0, sIdx = 0;
1452
1453 if (R >= 0)
1454 rIdx = tgsi.getSrc(R).getIndex(0);
1455 if (S >= 0)
1456 sIdx = tgsi.getSrc(S).getIndex(0);
1457
1458 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1459
1460 if (tgsi.getSrc(R).isIndirect(0)) {
1461 tex->tex.rIndirectSrc = s;
1462 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1463 }
1464 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1465 tex->tex.sIndirectSrc = s;
1466 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1467 }
1468 }
1469
1470 void
1471 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1472 {
1473 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1474 tex->tex.query = query;
1475 unsigned int c, d;
1476
1477 for (d = 0, c = 0; c < 4; ++c) {
1478 if (!dst0[c])
1479 continue;
1480 tex->tex.mask |= 1 << c;
1481 tex->setDef(d++, dst0[c]);
1482 }
1483 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1484
1485 setTexRS(tex, c, 1, -1);
1486
1487 bb->insertTail(tex);
1488 }
1489
1490 void
1491 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1492 {
1493 Value *proj = fetchSrc(0, 3);
1494 Instruction *insn = proj->getUniqueInsn();
1495 int c;
1496
1497 if (insn->op == OP_PINTERP) {
1498 bb->insertTail(insn = insn->clone(true));
1499 insn->op = OP_LINTERP;
1500 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1501 insn->setSrc(1, NULL);
1502 proj = insn->getDef(0);
1503 }
1504 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1505
1506 for (c = 0; c < 4; ++c) {
1507 if (!(mask & (1 << c)))
1508 continue;
1509 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1510 continue;
1511 mask &= ~(1 << c);
1512
1513 bb->insertTail(insn = insn->clone(true));
1514 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1515 insn->setSrc(1, proj);
1516 dst[c] = insn->getDef(0);
1517 }
1518 if (!mask)
1519 return;
1520
1521 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1522
1523 for (c = 0; c < 4; ++c)
1524 if (mask & (1 << c))
1525 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1526 }
1527
1528 // order of nv50 ir sources: x y z layer lod/bias shadow
1529 // order of TGSI TEX sources: x y z layer shadow lod/bias
1530 // lowering will finally set the hw specific order (like array first on nvc0)
1531 void
1532 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1533 {
1534 Value *val;
1535 Value *arg[4], *src[8];
1536 Value *lod = NULL, *shd = NULL;
1537 unsigned int s, c, d;
1538 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1539
1540 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1541
1542 for (s = 0; s < tgt.getArgCount(); ++s)
1543 arg[s] = src[s] = fetchSrc(0, s);
1544
1545 if (texi->op == OP_TXL || texi->op == OP_TXB)
1546 lod = fetchSrc(L >> 4, L & 3);
1547
1548 if (C == 0x0f)
1549 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1550
1551 if (tgt.isShadow())
1552 shd = fetchSrc(C >> 4, C & 3);
1553
1554 if (texi->op == OP_TXD) {
1555 for (c = 0; c < tgt.getDim(); ++c) {
1556 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1557 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1558 }
1559 }
1560
1561 // cube textures don't care about projection value, it's divided out
1562 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1563 unsigned int n = tgt.getDim();
1564 if (shd) {
1565 arg[n] = shd;
1566 ++n;
1567 assert(tgt.getDim() == tgt.getArgCount());
1568 }
1569 loadProjTexCoords(src, arg, (1 << n) - 1);
1570 if (shd)
1571 shd = src[n - 1];
1572 }
1573
1574 if (tgt.isCube()) {
1575 for (c = 0; c < 3; ++c)
1576 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1577 val = getScratch();
1578 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1579 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1580 mkOp1(OP_RCP, TYPE_F32, val, val);
1581 for (c = 0; c < 3; ++c)
1582 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1583 }
1584
1585 for (c = 0, d = 0; c < 4; ++c) {
1586 if (dst[c]) {
1587 texi->setDef(d++, dst[c]);
1588 texi->tex.mask |= 1 << c;
1589 } else {
1590 // NOTE: maybe hook up def too, for CSE
1591 }
1592 }
1593 for (s = 0; s < tgt.getArgCount(); ++s)
1594 texi->setSrc(s, src[s]);
1595 if (lod)
1596 texi->setSrc(s++, lod);
1597 if (shd)
1598 texi->setSrc(s++, shd);
1599
1600 setTexRS(texi, s, R, S);
1601
1602 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1603 texi->tex.levelZero = true;
1604
1605 bb->insertTail(texi);
1606 }
1607
1608 // 1st source: xyz = coordinates, w = lod
1609 // 2nd source: offset
1610 void
1611 Converter::handleTXF(Value *dst[4], int R)
1612 {
1613 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1614 unsigned int c, d, s;
1615
1616 texi->tex.target = tgsi.getTexture(code, R);
1617
1618 for (c = 0, d = 0; c < 4; ++c) {
1619 if (dst[c]) {
1620 texi->setDef(d++, dst[c]);
1621 texi->tex.mask |= 1 << c;
1622 }
1623 }
1624 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1625 texi->setSrc(c, fetchSrc(0, c));
1626 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1627
1628 setTexRS(texi, c, R, -1);
1629
1630 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1631 for (c = 0; c < 3; ++c) {
1632 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1633 if (texi->tex.offset[s][c])
1634 texi->tex.useOffsets = s + 1;
1635 }
1636 }
1637
1638 bb->insertTail(texi);
1639 }
1640
1641 void
1642 Converter::handleLIT(Value *dst0[4])
1643 {
1644 Value *val0 = NULL;
1645 unsigned int mask = tgsi.getDst(0).getMask();
1646
1647 if (mask & (1 << 0))
1648 loadImm(dst0[0], 1.0f);
1649
1650 if (mask & (1 << 3))
1651 loadImm(dst0[3], 1.0f);
1652
1653 if (mask & (3 << 1)) {
1654 val0 = getScratch();
1655 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1656 if (mask & (1 << 1))
1657 mkMov(dst0[1], val0);
1658 }
1659
1660 if (mask & (1 << 2)) {
1661 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1662 Value *val1 = getScratch(), *val3 = getScratch();
1663
1664 Value *pos128 = loadImm(NULL, +127.999999f);
1665 Value *neg128 = loadImm(NULL, -127.999999f);
1666
1667 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1668 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1669 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1670 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1671
1672 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1673 }
1674 }
1675
1676 bool
1677 Converter::isEndOfSubroutine(uint ip)
1678 {
1679 assert(ip < code->scan.num_instructions);
1680 tgsi::Instruction insn(&code->insns[ip]);
1681 return (insn.getOpcode() == TGSI_OPCODE_END ||
1682 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1683 // does END occur at end of main or the very end ?
1684 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1685 }
1686
1687 bool
1688 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1689 {
1690 Value *dst0[4], *rDst0[4];
1691 Value *src0, *src1, *src2;
1692 Value *val0, *val1;
1693 int c;
1694
1695 tgsi = tgsi::Instruction(insn);
1696
1697 bool useScratchDst = tgsi.checkDstSrcAliasing();
1698
1699 operation op = tgsi.getOP();
1700 dstTy = tgsi.inferDstType();
1701 srcTy = tgsi.inferSrcType();
1702
1703 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1704
1705 if (tgsi.dstCount()) {
1706 for (c = 0; c < 4; ++c) {
1707 rDst0[c] = acquireDst(0, c);
1708 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1709 }
1710 }
1711
1712 switch (tgsi.getOpcode()) {
1713 case TGSI_OPCODE_ADD:
1714 case TGSI_OPCODE_UADD:
1715 case TGSI_OPCODE_AND:
1716 case TGSI_OPCODE_DIV:
1717 case TGSI_OPCODE_IDIV:
1718 case TGSI_OPCODE_UDIV:
1719 case TGSI_OPCODE_MAX:
1720 case TGSI_OPCODE_MIN:
1721 case TGSI_OPCODE_IMAX:
1722 case TGSI_OPCODE_IMIN:
1723 case TGSI_OPCODE_UMAX:
1724 case TGSI_OPCODE_UMIN:
1725 case TGSI_OPCODE_MOD:
1726 case TGSI_OPCODE_UMOD:
1727 case TGSI_OPCODE_MUL:
1728 case TGSI_OPCODE_UMUL:
1729 case TGSI_OPCODE_OR:
1730 case TGSI_OPCODE_POW:
1731 case TGSI_OPCODE_SHL:
1732 case TGSI_OPCODE_ISHR:
1733 case TGSI_OPCODE_USHR:
1734 case TGSI_OPCODE_SUB:
1735 case TGSI_OPCODE_XOR:
1736 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1737 src0 = fetchSrc(0, c);
1738 src1 = fetchSrc(1, c);
1739 mkOp2(op, dstTy, dst0[c], src0, src1);
1740 }
1741 break;
1742 case TGSI_OPCODE_MAD:
1743 case TGSI_OPCODE_UMAD:
1744 case TGSI_OPCODE_SAD:
1745 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1746 src0 = fetchSrc(0, c);
1747 src1 = fetchSrc(1, c);
1748 src2 = fetchSrc(2, c);
1749 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1750 }
1751 break;
1752 case TGSI_OPCODE_MOV:
1753 case TGSI_OPCODE_ABS:
1754 case TGSI_OPCODE_CEIL:
1755 case TGSI_OPCODE_FLR:
1756 case TGSI_OPCODE_TRUNC:
1757 case TGSI_OPCODE_RCP:
1758 case TGSI_OPCODE_IABS:
1759 case TGSI_OPCODE_INEG:
1760 case TGSI_OPCODE_NOT:
1761 case TGSI_OPCODE_DDX:
1762 case TGSI_OPCODE_DDY:
1763 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1764 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1765 break;
1766 case TGSI_OPCODE_RSQ:
1767 src0 = fetchSrc(0, 0);
1768 val0 = getScratch();
1769 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1770 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1771 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1772 mkMov(dst0[c], val0);
1773 break;
1774 case TGSI_OPCODE_ARL:
1775 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1776 src0 = fetchSrc(0, c);
1777 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1778 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1779 }
1780 break;
1781 case TGSI_OPCODE_UARL:
1782 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1783 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1784 break;
1785 case TGSI_OPCODE_EX2:
1786 case TGSI_OPCODE_LG2:
1787 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1788 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1789 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1790 break;
1791 case TGSI_OPCODE_COS:
1792 case TGSI_OPCODE_SIN:
1793 val0 = getScratch();
1794 if (mask & 7) {
1795 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1796 mkOp1(op, TYPE_F32, val0, val0);
1797 for (c = 0; c < 3; ++c)
1798 if (dst0[c])
1799 mkMov(dst0[c], val0);
1800 }
1801 if (dst0[3]) {
1802 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1803 mkOp1(op, TYPE_F32, dst0[3], val0);
1804 }
1805 break;
1806 case TGSI_OPCODE_SCS:
1807 if (mask & 3) {
1808 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1809 if (dst0[0])
1810 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1811 if (dst0[1])
1812 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1813 }
1814 if (dst0[2])
1815 loadImm(dst0[2], 0.0f);
1816 if (dst0[3])
1817 loadImm(dst0[3], 1.0f);
1818 break;
1819 case TGSI_OPCODE_EXP:
1820 src0 = fetchSrc(0, 0);
1821 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1822 if (dst0[1])
1823 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1824 if (dst0[0])
1825 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1826 if (dst0[2])
1827 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1828 if (dst0[3])
1829 loadImm(dst0[3], 1.0f);
1830 break;
1831 case TGSI_OPCODE_LOG:
1832 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1833 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1834 if (dst0[0] || dst0[1])
1835 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1836 if (dst0[1]) {
1837 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1838 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1839 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1840 }
1841 if (dst0[3])
1842 loadImm(dst0[3], 1.0f);
1843 break;
1844 case TGSI_OPCODE_DP2:
1845 val0 = buildDot(2);
1846 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1847 mkMov(dst0[c], val0);
1848 break;
1849 case TGSI_OPCODE_DP3:
1850 val0 = buildDot(3);
1851 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1852 mkMov(dst0[c], val0);
1853 break;
1854 case TGSI_OPCODE_DP4:
1855 val0 = buildDot(4);
1856 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1857 mkMov(dst0[c], val0);
1858 break;
1859 case TGSI_OPCODE_DPH:
1860 val0 = buildDot(3);
1861 src1 = fetchSrc(1, 3);
1862 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1863 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1864 mkMov(dst0[c], val0);
1865 break;
1866 case TGSI_OPCODE_DST:
1867 if (dst0[0])
1868 loadImm(dst0[0], 1.0f);
1869 if (dst0[1]) {
1870 src0 = fetchSrc(0, 1);
1871 src1 = fetchSrc(1, 1);
1872 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1873 }
1874 if (dst0[2])
1875 mkMov(dst0[2], fetchSrc(0, 2));
1876 if (dst0[3])
1877 mkMov(dst0[3], fetchSrc(1, 3));
1878 break;
1879 case TGSI_OPCODE_LRP:
1880 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1881 src0 = fetchSrc(0, c);
1882 src1 = fetchSrc(1, c);
1883 src2 = fetchSrc(2, c);
1884 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1885 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1886 }
1887 break;
1888 case TGSI_OPCODE_LIT:
1889 handleLIT(dst0);
1890 break;
1891 case TGSI_OPCODE_XPD:
1892 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1893 if (c < 3) {
1894 val0 = getSSA();
1895 src0 = fetchSrc(1, (c + 1) % 3);
1896 src1 = fetchSrc(0, (c + 2) % 3);
1897 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1898 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1899
1900 src0 = fetchSrc(0, (c + 1) % 3);
1901 src1 = fetchSrc(1, (c + 2) % 3);
1902 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1903 } else {
1904 loadImm(dst0[c], 1.0f);
1905 }
1906 }
1907 break;
1908 case TGSI_OPCODE_ISSG:
1909 case TGSI_OPCODE_SSG:
1910 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1911 src0 = fetchSrc(0, c);
1912 val0 = getScratch();
1913 val1 = getScratch();
1914 mkCmp(OP_SET, CC_GT, srcTy, val0, src0, zero);
1915 mkCmp(OP_SET, CC_LT, srcTy, val1, src0, zero);
1916 if (srcTy == TYPE_F32)
1917 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1918 else
1919 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
1920 }
1921 break;
1922 case TGSI_OPCODE_UCMP:
1923 case TGSI_OPCODE_CMP:
1924 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1925 src0 = fetchSrc(0, c);
1926 src1 = fetchSrc(1, c);
1927 src2 = fetchSrc(2, c);
1928 if (src1 == src2)
1929 mkMov(dst0[c], src1);
1930 else
1931 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1932 srcTy, dst0[c], src1, src2, src0);
1933 }
1934 break;
1935 case TGSI_OPCODE_FRC:
1936 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1937 src0 = fetchSrc(0, c);
1938 val0 = getScratch();
1939 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1940 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1941 }
1942 break;
1943 case TGSI_OPCODE_ROUND:
1944 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1945 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1946 ->rnd = ROUND_NI;
1947 break;
1948 case TGSI_OPCODE_CLAMP:
1949 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1950 src0 = fetchSrc(0, c);
1951 src1 = fetchSrc(1, c);
1952 src2 = fetchSrc(2, c);
1953 val0 = getScratch();
1954 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1955 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1956 }
1957 break;
1958 case TGSI_OPCODE_SLT:
1959 case TGSI_OPCODE_SGE:
1960 case TGSI_OPCODE_SEQ:
1961 case TGSI_OPCODE_SFL:
1962 case TGSI_OPCODE_SGT:
1963 case TGSI_OPCODE_SLE:
1964 case TGSI_OPCODE_SNE:
1965 case TGSI_OPCODE_STR:
1966 case TGSI_OPCODE_ISGE:
1967 case TGSI_OPCODE_ISLT:
1968 case TGSI_OPCODE_USEQ:
1969 case TGSI_OPCODE_USGE:
1970 case TGSI_OPCODE_USLT:
1971 case TGSI_OPCODE_USNE:
1972 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1973 src0 = fetchSrc(0, c);
1974 src1 = fetchSrc(1, c);
1975 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1976 }
1977 break;
1978 case TGSI_OPCODE_KIL:
1979 val0 = new_LValue(func, FILE_PREDICATE);
1980 for (c = 0; c < 4; ++c) {
1981 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1982 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1983 }
1984 break;
1985 case TGSI_OPCODE_KILP:
1986 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1987 break;
1988 case TGSI_OPCODE_TEX:
1989 case TGSI_OPCODE_TXB:
1990 case TGSI_OPCODE_TXL:
1991 case TGSI_OPCODE_TXP:
1992 // R S L C Dx Dy
1993 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1994 break;
1995 case TGSI_OPCODE_TXD:
1996 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1997 break;
1998 case TGSI_OPCODE_SAMPLE:
1999 case TGSI_OPCODE_SAMPLE_B:
2000 case TGSI_OPCODE_SAMPLE_D:
2001 case TGSI_OPCODE_SAMPLE_L:
2002 case TGSI_OPCODE_SAMPLE_C:
2003 case TGSI_OPCODE_SAMPLE_C_LZ:
2004 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
2005 break;
2006 case TGSI_OPCODE_TXF:
2007 case TGSI_OPCODE_LOAD:
2008 handleTXF(dst0, 1);
2009 break;
2010 case TGSI_OPCODE_TXQ:
2011 case TGSI_OPCODE_RESINFO:
2012 handleTXQ(dst0, TXQ_DIMS);
2013 break;
2014 case TGSI_OPCODE_F2I:
2015 case TGSI_OPCODE_F2U:
2016 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2017 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2018 break;
2019 case TGSI_OPCODE_I2F:
2020 case TGSI_OPCODE_U2F:
2021 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2022 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2023 break;
2024 case TGSI_OPCODE_EMIT:
2025 case TGSI_OPCODE_ENDPRIM:
2026 // get vertex stream if specified (must be immediate)
2027 src0 = tgsi.srcCount() ?
2028 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2029 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2030 break;
2031 case TGSI_OPCODE_IF:
2032 {
2033 BasicBlock *ifBB = new BasicBlock(func);
2034
2035 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2036 condBBs.push(bb);
2037 joinBBs.push(bb);
2038
2039 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2040
2041 setPosition(ifBB, true);
2042 }
2043 break;
2044 case TGSI_OPCODE_ELSE:
2045 {
2046 BasicBlock *elseBB = new BasicBlock(func);
2047 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2048
2049 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2050 condBBs.push(bb);
2051
2052 forkBB->getExit()->asFlow()->target.bb = elseBB;
2053 if (!bb->isTerminated())
2054 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2055
2056 setPosition(elseBB, true);
2057 }
2058 break;
2059 case TGSI_OPCODE_ENDIF:
2060 {
2061 BasicBlock *convBB = new BasicBlock(func);
2062 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2063 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2064
2065 if (!bb->isTerminated()) {
2066 // we only want join if none of the clauses ended with CONT/BREAK/RET
2067 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2068 insertConvergenceOps(convBB, forkBB);
2069 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2070 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2071 }
2072
2073 if (prevBB->getExit()->op == OP_BRA) {
2074 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2075 prevBB->getExit()->asFlow()->target.bb = convBB;
2076 }
2077 setPosition(convBB, true);
2078 }
2079 break;
2080 case TGSI_OPCODE_BGNLOOP:
2081 {
2082 BasicBlock *lbgnBB = new BasicBlock(func);
2083 BasicBlock *lbrkBB = new BasicBlock(func);
2084
2085 loopBBs.push(lbgnBB);
2086 breakBBs.push(lbrkBB);
2087 if (loopBBs.getSize() > func->loopNestingBound)
2088 func->loopNestingBound++;
2089
2090 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2091
2092 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2093 setPosition(lbgnBB, true);
2094 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2095 }
2096 break;
2097 case TGSI_OPCODE_ENDLOOP:
2098 {
2099 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2100
2101 if (!bb->isTerminated()) {
2102 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2103 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2104 }
2105 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2106 }
2107 break;
2108 case TGSI_OPCODE_BRK:
2109 {
2110 if (bb->isTerminated())
2111 break;
2112 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2113 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2114 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2115 }
2116 break;
2117 case TGSI_OPCODE_CONT:
2118 {
2119 if (bb->isTerminated())
2120 break;
2121 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2122 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2123 contBB->explicitCont = true;
2124 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2125 }
2126 break;
2127 case TGSI_OPCODE_BGNSUB:
2128 {
2129 if (!retIPs.getSize()) {
2130 // end of main function
2131 ip = code->scan.num_instructions - 2; // goto END
2132 return true;
2133 }
2134 BasicBlock *entry = new BasicBlock(func);
2135 BasicBlock *leave = new BasicBlock(func);
2136 entryBBs.push(entry);
2137 leaveBBs.push(leave);
2138 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2139 setPosition(entry, true);
2140 }
2141 return true;
2142 case TGSI_OPCODE_ENDSUB:
2143 {
2144 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2145 entryBBs.pop();
2146 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2147 setPosition(leave, true);
2148 ip = retIPs.pop().u.u;
2149 }
2150 return true;
2151 case TGSI_OPCODE_CAL:
2152 // we don't have function declarations, so inline everything
2153 retIPs.push(ip);
2154 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2155 return true;
2156 case TGSI_OPCODE_RET:
2157 {
2158 if (bb->isTerminated())
2159 return true;
2160 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2161 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2162 if (!isEndOfSubroutine(ip + 1)) {
2163 // insert a PRERET at the entry if this is an early return
2164 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2165 preRet->fixed = 1;
2166 entry->insertHead(preRet);
2167 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2168 }
2169 // everything inlined so RET serves only to wrap up the stack
2170 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2171 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2172 }
2173 break;
2174 case TGSI_OPCODE_END:
2175 {
2176 // attach and generate epilogue code
2177 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2178 entryBBs.pop();
2179 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2180 setPosition(epilogue, true);
2181 if (prog->getType() == Program::TYPE_FRAGMENT)
2182 exportOutputs();
2183 if (info->io.genUserClip > 0)
2184 handleUserClipPlanes();
2185 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2186 }
2187 break;
2188 case TGSI_OPCODE_SWITCH:
2189 case TGSI_OPCODE_CASE:
2190 ERROR("switch/case opcode encountered, should have been lowered\n");
2191 abort();
2192 break;
2193 default:
2194 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2195 assert(0);
2196 break;
2197 }
2198
2199 if (tgsi.dstCount()) {
2200 for (c = 0; c < 4; ++c) {
2201 if (!dst0[c])
2202 continue;
2203 if (dst0[c] != rDst0[c])
2204 mkMov(rDst0[c], dst0[c]);
2205 storeDst(0, c, rDst0[c]);
2206 }
2207 }
2208 vtxBaseValid = 0;
2209
2210 return true;
2211 }
2212
2213 void
2214 Converter::handleUserClipPlanes()
2215 {
2216 Value *res[8];
2217 int i, c;
2218
2219 for (c = 0; c < 4; ++c) {
2220 for (i = 0; i < info->io.genUserClip; ++i) {
2221 Value *ucp;
2222 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2223 i * 16 + c * 4), NULL);
2224 if (c == 0)
2225 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2226 else
2227 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2228 }
2229 }
2230
2231 for (i = 0; i < info->io.genUserClip; ++i)
2232 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2233 }
2234
2235 void
2236 Converter::exportOutputs()
2237 {
2238 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2239 for (unsigned int c = 0; c < 4; ++c) {
2240 if (!oData.exists(i, c))
2241 continue;
2242 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2243 info->out[i].slot[c] * 4);
2244 Value *val = oData.load(i, c, NULL);
2245 if (val)
2246 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2247 }
2248 }
2249 }
2250
2251 Converter::Converter(Program *ir, const tgsi::Source *src)
2252 : code(src),
2253 tgsi(NULL),
2254 tData(this), aData(this), pData(this), oData(this)
2255 {
2256 prog = ir;
2257 info = code->info;
2258
2259 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2260
2261 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2262 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2263 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2264 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2265
2266 lData = NULL;
2267 iData = NULL;
2268
2269 zero = mkImm((uint32_t)0);
2270
2271 vtxBaseValid = 0;
2272 }
2273
2274 Converter::~Converter()
2275 {
2276 if (lData)
2277 delete[] lData;
2278 if (iData)
2279 delete[] iData;
2280 }
2281
2282 bool
2283 Converter::run()
2284 {
2285 BasicBlock *entry = new BasicBlock(prog->main);
2286 BasicBlock *leave = new BasicBlock(prog->main);
2287
2288 if (code->tempArrayCount && !lData) {
2289 uint32_t volume = 0;
2290 lData = new DataArray[code->tempArrayCount];
2291 if (!lData)
2292 return false;
2293 for (int i = 0; i < code->tempArrayCount; ++i) {
2294 int len = code->tempArrays[i].u32 >> 2;
2295 int dim = code->tempArrays[i].u32 & 3;
2296 lData[i].setParent(this);
2297 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2298 volume += (len * dim * 4 + 0xf) & ~0xf;
2299 }
2300 }
2301 if (code->immdArrayCount && !iData) {
2302 uint32_t volume = 0;
2303 iData = new DataArray[code->immdArrayCount];
2304 if (!iData)
2305 return false;
2306 for (int i = 0; i < code->immdArrayCount; ++i) {
2307 int len = code->immdArrays[i].u32 >> 2;
2308 int dim = code->immdArrays[i].u32 & 3;
2309 iData[i].setParent(this);
2310 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2311 volume += (len * dim * 4 + 0xf) & ~0xf;
2312 }
2313 }
2314
2315 prog->main->setEntry(entry);
2316 prog->main->setExit(leave);
2317
2318 setPosition(entry, true);
2319 entryBBs.push(entry);
2320 leaveBBs.push(leave);
2321
2322 if (info->io.genUserClip > 0) {
2323 for (int c = 0; c < 4; ++c)
2324 clipVtx[c] = getScratch();
2325 }
2326
2327 if (prog->getType() == Program::TYPE_FRAGMENT) {
2328 Symbol *sv = mkSysVal(SV_POSITION, 3);
2329 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2330 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2331 }
2332
2333 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2334 if (!handleInstruction(&code->insns[ip]))
2335 return false;
2336 }
2337 return true;
2338 }
2339
2340 } // unnamed namespace
2341
2342 namespace nv50_ir {
2343
2344 bool
2345 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2346 {
2347 tgsi::Source src(info);
2348 if (!src.scanSource())
2349 return false;
2350
2351 Converter builder(this, &src);
2352 return builder.run();
2353 }
2354
2355 } // namespace nv50_ir