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nv50/ir: handle TGSI_SEMANTIC_VERTEXID
[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP3:
218 return 0x7;
219 case TGSI_OPCODE_DP4:
220 case TGSI_OPCODE_DPH:
221 case TGSI_OPCODE_KIL: /* WriteMask ignored */
222 return 0xf;
223 case TGSI_OPCODE_DST:
224 return mask & (s ? 0xa : 0x6);
225 case TGSI_OPCODE_EX2:
226 case TGSI_OPCODE_EXP:
227 case TGSI_OPCODE_LG2:
228 case TGSI_OPCODE_LOG:
229 case TGSI_OPCODE_POW:
230 case TGSI_OPCODE_RCP:
231 case TGSI_OPCODE_RSQ:
232 case TGSI_OPCODE_SCS:
233 return 0x1;
234 case TGSI_OPCODE_IF:
235 return 0x1;
236 case TGSI_OPCODE_LIT:
237 return 0xb;
238 case TGSI_OPCODE_TEX:
239 case TGSI_OPCODE_TXB:
240 case TGSI_OPCODE_TXD:
241 case TGSI_OPCODE_TXL:
242 case TGSI_OPCODE_TXP:
243 {
244 const struct tgsi_instruction_texture *tex = &insn->Texture;
245
246 assert(insn->Instruction.Texture);
247
248 mask = 0x7;
249 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
250 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
251 mask |= 0x8; /* bias, lod or proj */
252
253 switch (tex->Texture) {
254 case TGSI_TEXTURE_1D:
255 mask &= 0x9;
256 break;
257 case TGSI_TEXTURE_SHADOW1D:
258 mask &= 0x5;
259 break;
260 case TGSI_TEXTURE_1D_ARRAY:
261 case TGSI_TEXTURE_2D:
262 case TGSI_TEXTURE_RECT:
263 mask &= 0xb;
264 break;
265 default:
266 break;
267 }
268 }
269 return mask;
270 case TGSI_OPCODE_XPD:
271 {
272 unsigned int x = 0;
273 if (mask & 1) x |= 0x6;
274 if (mask & 2) x |= 0x5;
275 if (mask & 4) x |= 0x3;
276 return x;
277 }
278 default:
279 break;
280 }
281
282 return mask;
283 }
284
285 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
286 {
287 nv50_ir::Modifier m(0);
288
289 if (reg.Absolute)
290 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
291 if (reg.Negate)
292 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
293 return m;
294 }
295
296 static nv50_ir::DataFile translateFile(uint file)
297 {
298 switch (file) {
299 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
300 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
301 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
302 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
303 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
304 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
305 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
306 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
307 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
308 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
309 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
310 case TGSI_FILE_SAMPLER:
311 case TGSI_FILE_NULL:
312 default:
313 return nv50_ir::FILE_NULL;
314 }
315 }
316
317 static nv50_ir::SVSemantic translateSysVal(uint sysval)
318 {
319 switch (sysval) {
320 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
321 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
322 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
323 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
324 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
325 default:
326 assert(0);
327 return nv50_ir::SV_CLOCK;
328 }
329 }
330
331 #define NV50_IR_TEX_TARG_CASE(a, b) \
332 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
333
334 static nv50_ir::TexTarget translateTexture(uint tex)
335 {
336 switch (tex) {
337 NV50_IR_TEX_TARG_CASE(1D, 1D);
338 NV50_IR_TEX_TARG_CASE(2D, 2D);
339 NV50_IR_TEX_TARG_CASE(3D, 3D);
340 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
341 NV50_IR_TEX_TARG_CASE(RECT, RECT);
342 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
343 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
344 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
345 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
346 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
347 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
348 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
349
350 case TGSI_TEXTURE_UNKNOWN:
351 default:
352 assert(!"invalid texture target");
353 return nv50_ir::TEX_TARGET_2D;
354 }
355 }
356
357 nv50_ir::DataType Instruction::inferSrcType() const
358 {
359 switch (getOpcode()) {
360 case TGSI_OPCODE_AND:
361 case TGSI_OPCODE_OR:
362 case TGSI_OPCODE_XOR:
363 case TGSI_OPCODE_U2F:
364 case TGSI_OPCODE_UADD:
365 case TGSI_OPCODE_UDIV:
366 case TGSI_OPCODE_UMOD:
367 case TGSI_OPCODE_UMAD:
368 case TGSI_OPCODE_UMUL:
369 case TGSI_OPCODE_UMAX:
370 case TGSI_OPCODE_UMIN:
371 case TGSI_OPCODE_USEQ:
372 case TGSI_OPCODE_USGE:
373 case TGSI_OPCODE_USLT:
374 case TGSI_OPCODE_USNE:
375 case TGSI_OPCODE_USHR:
376 case TGSI_OPCODE_UCMP:
377 return nv50_ir::TYPE_U32;
378 case TGSI_OPCODE_I2F:
379 case TGSI_OPCODE_IDIV:
380 case TGSI_OPCODE_IMAX:
381 case TGSI_OPCODE_IMIN:
382 case TGSI_OPCODE_IABS:
383 case TGSI_OPCODE_INEG:
384 case TGSI_OPCODE_ISGE:
385 case TGSI_OPCODE_ISHR:
386 case TGSI_OPCODE_ISLT:
387 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
388 case TGSI_OPCODE_MOD:
389 case TGSI_OPCODE_UARL:
390 return nv50_ir::TYPE_S32;
391 default:
392 return nv50_ir::TYPE_F32;
393 }
394 }
395
396 nv50_ir::DataType Instruction::inferDstType() const
397 {
398 switch (getOpcode()) {
399 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
400 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
401 case TGSI_OPCODE_I2F:
402 case TGSI_OPCODE_U2F:
403 return nv50_ir::TYPE_F32;
404 default:
405 return inferSrcType();
406 }
407 }
408
409 nv50_ir::CondCode Instruction::getSetCond() const
410 {
411 using namespace nv50_ir;
412
413 switch (getOpcode()) {
414 case TGSI_OPCODE_SLT:
415 case TGSI_OPCODE_ISLT:
416 case TGSI_OPCODE_USLT:
417 return CC_LT;
418 case TGSI_OPCODE_SLE:
419 return CC_LE;
420 case TGSI_OPCODE_SGE:
421 case TGSI_OPCODE_ISGE:
422 case TGSI_OPCODE_USGE:
423 return CC_GE;
424 case TGSI_OPCODE_SGT:
425 return CC_GT;
426 case TGSI_OPCODE_SEQ:
427 case TGSI_OPCODE_USEQ:
428 return CC_EQ;
429 case TGSI_OPCODE_SNE:
430 return CC_NEU;
431 case TGSI_OPCODE_USNE:
432 return CC_NE;
433 case TGSI_OPCODE_SFL:
434 return CC_NEVER;
435 case TGSI_OPCODE_STR:
436 default:
437 return CC_ALWAYS;
438 }
439 }
440
441 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
442
443 static nv50_ir::operation translateOpcode(uint opcode)
444 {
445 switch (opcode) {
446 NV50_IR_OPCODE_CASE(ARL, SHL);
447 NV50_IR_OPCODE_CASE(MOV, MOV);
448
449 NV50_IR_OPCODE_CASE(RCP, RCP);
450 NV50_IR_OPCODE_CASE(RSQ, RSQ);
451
452 NV50_IR_OPCODE_CASE(MUL, MUL);
453 NV50_IR_OPCODE_CASE(ADD, ADD);
454
455 NV50_IR_OPCODE_CASE(MIN, MIN);
456 NV50_IR_OPCODE_CASE(MAX, MAX);
457 NV50_IR_OPCODE_CASE(SLT, SET);
458 NV50_IR_OPCODE_CASE(SGE, SET);
459 NV50_IR_OPCODE_CASE(MAD, MAD);
460 NV50_IR_OPCODE_CASE(SUB, SUB);
461
462 NV50_IR_OPCODE_CASE(FLR, FLOOR);
463 NV50_IR_OPCODE_CASE(ROUND, CVT);
464 NV50_IR_OPCODE_CASE(EX2, EX2);
465 NV50_IR_OPCODE_CASE(LG2, LG2);
466 NV50_IR_OPCODE_CASE(POW, POW);
467
468 NV50_IR_OPCODE_CASE(ABS, ABS);
469
470 NV50_IR_OPCODE_CASE(COS, COS);
471 NV50_IR_OPCODE_CASE(DDX, DFDX);
472 NV50_IR_OPCODE_CASE(DDY, DFDY);
473 NV50_IR_OPCODE_CASE(KILP, DISCARD);
474
475 NV50_IR_OPCODE_CASE(SEQ, SET);
476 NV50_IR_OPCODE_CASE(SFL, SET);
477 NV50_IR_OPCODE_CASE(SGT, SET);
478 NV50_IR_OPCODE_CASE(SIN, SIN);
479 NV50_IR_OPCODE_CASE(SLE, SET);
480 NV50_IR_OPCODE_CASE(SNE, SET);
481 NV50_IR_OPCODE_CASE(STR, SET);
482 NV50_IR_OPCODE_CASE(TEX, TEX);
483 NV50_IR_OPCODE_CASE(TXD, TXD);
484 NV50_IR_OPCODE_CASE(TXP, TEX);
485
486 NV50_IR_OPCODE_CASE(BRA, BRA);
487 NV50_IR_OPCODE_CASE(CAL, CALL);
488 NV50_IR_OPCODE_CASE(RET, RET);
489 NV50_IR_OPCODE_CASE(CMP, SLCT);
490
491 NV50_IR_OPCODE_CASE(TXB, TXB);
492
493 NV50_IR_OPCODE_CASE(DIV, DIV);
494
495 NV50_IR_OPCODE_CASE(TXL, TXL);
496
497 NV50_IR_OPCODE_CASE(CEIL, CEIL);
498 NV50_IR_OPCODE_CASE(I2F, CVT);
499 NV50_IR_OPCODE_CASE(NOT, NOT);
500 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
501 NV50_IR_OPCODE_CASE(SHL, SHL);
502
503 NV50_IR_OPCODE_CASE(AND, AND);
504 NV50_IR_OPCODE_CASE(OR, OR);
505 NV50_IR_OPCODE_CASE(MOD, MOD);
506 NV50_IR_OPCODE_CASE(XOR, XOR);
507 NV50_IR_OPCODE_CASE(SAD, SAD);
508 NV50_IR_OPCODE_CASE(TXF, TXF);
509 NV50_IR_OPCODE_CASE(TXQ, TXQ);
510
511 NV50_IR_OPCODE_CASE(EMIT, EMIT);
512 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
513
514 NV50_IR_OPCODE_CASE(KIL, DISCARD);
515
516 NV50_IR_OPCODE_CASE(F2I, CVT);
517 NV50_IR_OPCODE_CASE(IDIV, DIV);
518 NV50_IR_OPCODE_CASE(IMAX, MAX);
519 NV50_IR_OPCODE_CASE(IMIN, MIN);
520 NV50_IR_OPCODE_CASE(IABS, ABS);
521 NV50_IR_OPCODE_CASE(INEG, NEG);
522 NV50_IR_OPCODE_CASE(ISGE, SET);
523 NV50_IR_OPCODE_CASE(ISHR, SHR);
524 NV50_IR_OPCODE_CASE(ISLT, SET);
525 NV50_IR_OPCODE_CASE(F2U, CVT);
526 NV50_IR_OPCODE_CASE(U2F, CVT);
527 NV50_IR_OPCODE_CASE(UADD, ADD);
528 NV50_IR_OPCODE_CASE(UDIV, DIV);
529 NV50_IR_OPCODE_CASE(UMAD, MAD);
530 NV50_IR_OPCODE_CASE(UMAX, MAX);
531 NV50_IR_OPCODE_CASE(UMIN, MIN);
532 NV50_IR_OPCODE_CASE(UMOD, MOD);
533 NV50_IR_OPCODE_CASE(UMUL, MUL);
534 NV50_IR_OPCODE_CASE(USEQ, SET);
535 NV50_IR_OPCODE_CASE(USGE, SET);
536 NV50_IR_OPCODE_CASE(USHR, SHR);
537 NV50_IR_OPCODE_CASE(USLT, SET);
538 NV50_IR_OPCODE_CASE(USNE, SET);
539
540 NV50_IR_OPCODE_CASE(LOAD, TXF);
541 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
542 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
543 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
544 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
545 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
546 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
547 NV50_IR_OPCODE_CASE(GATHER4, TXG);
548 NV50_IR_OPCODE_CASE(RESINFO, TXQ);
549
550 NV50_IR_OPCODE_CASE(END, EXIT);
551
552 default:
553 return nv50_ir::OP_NOP;
554 }
555 }
556
557 bool Instruction::checkDstSrcAliasing() const
558 {
559 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
560 return false;
561
562 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
563 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
564 break;
565 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
566 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
567 return true;
568 }
569 return false;
570 }
571
572 class Source
573 {
574 public:
575 Source(struct nv50_ir_prog_info *);
576 ~Source();
577
578 struct Subroutine
579 {
580 unsigned pc;
581 };
582
583 public:
584 bool scanSource();
585 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
586
587 public:
588 struct tgsi_shader_info scan;
589 struct tgsi_full_instruction *insns;
590 const struct tgsi_token *tokens;
591 struct nv50_ir_prog_info *info;
592
593 nv50_ir::DynArray tempArrays;
594 nv50_ir::DynArray immdArrays;
595 int tempArrayCount;
596 int immdArrayCount;
597
598 bool mainTempsInLMem;
599
600 int clipVertexOutput;
601
602 uint8_t *resourceTargets; // TGSI_TEXTURE_*
603 unsigned resourceCount;
604
605 Subroutine *subroutines;
606 unsigned subroutineCount;
607
608 private:
609 int inferSysValDirection(unsigned sn) const;
610 bool scanDeclaration(const struct tgsi_full_declaration *);
611 bool scanInstruction(const struct tgsi_full_instruction *);
612 void scanProperty(const struct tgsi_full_property *);
613 void scanImmediate(const struct tgsi_full_immediate *);
614
615 inline bool isEdgeFlagPassthrough(const Instruction&) const;
616 };
617
618 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
619 {
620 tokens = (const struct tgsi_token *)info->bin.source;
621
622 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
623 tgsi_dump(tokens, 0);
624
625 resourceTargets = NULL;
626 subroutines = NULL;
627
628 mainTempsInLMem = FALSE;
629 }
630
631 Source::~Source()
632 {
633 if (insns)
634 FREE(insns);
635
636 if (info->immd.data)
637 FREE(info->immd.data);
638 if (info->immd.type)
639 FREE(info->immd.type);
640
641 if (resourceTargets)
642 delete[] resourceTargets;
643 if (subroutines)
644 delete[] subroutines;
645 }
646
647 bool Source::scanSource()
648 {
649 unsigned insnCount = 0;
650 unsigned subrCount = 0;
651 struct tgsi_parse_context parse;
652
653 tgsi_scan_shader(tokens, &scan);
654
655 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
656 sizeof(insns[0]));
657 if (!insns)
658 return false;
659
660 clipVertexOutput = -1;
661
662 resourceCount = scan.file_max[TGSI_FILE_RESOURCE] + 1;
663 resourceTargets = new uint8_t[resourceCount];
664
665 subroutineCount = scan.opcode_count[TGSI_OPCODE_BGNSUB] + 1;
666 subroutines = new Subroutine[subroutineCount];
667
668 info->immd.bufSize = 0;
669 tempArrayCount = 0;
670 immdArrayCount = 0;
671
672 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
673 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
674 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
675
676 if (info->type == PIPE_SHADER_FRAGMENT) {
677 info->prop.fp.writesDepth = scan.writes_z;
678 info->prop.fp.usesDiscard = scan.uses_kill;
679 } else
680 if (info->type == PIPE_SHADER_GEOMETRY) {
681 info->prop.gp.instanceCount = 1; // default value
682 }
683
684 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
685 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
686
687 tgsi_parse_init(&parse, tokens);
688 while (!tgsi_parse_end_of_tokens(&parse)) {
689 tgsi_parse_token(&parse);
690
691 switch (parse.FullToken.Token.Type) {
692 case TGSI_TOKEN_TYPE_IMMEDIATE:
693 scanImmediate(&parse.FullToken.FullImmediate);
694 break;
695 case TGSI_TOKEN_TYPE_DECLARATION:
696 scanDeclaration(&parse.FullToken.FullDeclaration);
697 break;
698 case TGSI_TOKEN_TYPE_INSTRUCTION:
699 insns[insnCount++] = parse.FullToken.FullInstruction;
700 if (insns[insnCount - 1].Instruction.Opcode == TGSI_OPCODE_BGNSUB)
701 subroutines[++subrCount].pc = insnCount - 1;
702 else
703 scanInstruction(&parse.FullToken.FullInstruction);
704 break;
705 case TGSI_TOKEN_TYPE_PROPERTY:
706 scanProperty(&parse.FullToken.FullProperty);
707 break;
708 default:
709 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
710 break;
711 }
712 }
713 tgsi_parse_free(&parse);
714
715 if (mainTempsInLMem)
716 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
717
718 if (info->io.genUserClip > 0)
719 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
720
721 return info->assignSlots(info) == 0;
722 }
723
724 void Source::scanProperty(const struct tgsi_full_property *prop)
725 {
726 switch (prop->Property.PropertyName) {
727 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
728 info->prop.gp.outputPrim = prop->u[0].Data;
729 break;
730 case TGSI_PROPERTY_GS_INPUT_PRIM:
731 info->prop.gp.inputPrim = prop->u[0].Data;
732 break;
733 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
734 info->prop.gp.maxVertices = prop->u[0].Data;
735 break;
736 #if 0
737 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
738 info->prop.gp.instanceCount = prop->u[0].Data;
739 break;
740 #endif
741 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
742 info->prop.fp.separateFragData = TRUE;
743 break;
744 case TGSI_PROPERTY_FS_COORD_ORIGIN:
745 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
746 // we don't care
747 break;
748 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
749 info->io.genUserClip = -1;
750 break;
751 default:
752 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
753 break;
754 }
755 }
756
757 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
758 {
759 const unsigned n = info->immd.count++;
760
761 assert(n < scan.immediate_count);
762
763 for (int c = 0; c < 4; ++c)
764 info->immd.data[n * 4 + c] = imm->u[c].Uint;
765
766 info->immd.type[n] = imm->Immediate.DataType;
767 }
768
769 int Source::inferSysValDirection(unsigned sn) const
770 {
771 switch (sn) {
772 case TGSI_SEMANTIC_INSTANCEID:
773 case TGSI_SEMANTIC_VERTEXID:
774 return 1;
775 #if 0
776 case TGSI_SEMANTIC_LAYER:
777 case TGSI_SEMANTIC_VIEWPORTINDEX:
778 return 0;
779 #endif
780 case TGSI_SEMANTIC_PRIMID:
781 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
782 default:
783 return 0;
784 }
785 }
786
787 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
788 {
789 unsigned i;
790 unsigned sn = TGSI_SEMANTIC_GENERIC;
791 unsigned si = 0;
792 const unsigned first = decl->Range.First, last = decl->Range.Last;
793
794 if (decl->Declaration.Semantic) {
795 sn = decl->Semantic.Name;
796 si = decl->Semantic.Index;
797 }
798
799 switch (decl->Declaration.File) {
800 case TGSI_FILE_INPUT:
801 if (info->type == PIPE_SHADER_VERTEX) {
802 // all vertex attributes are equal
803 for (i = first; i <= last; ++i) {
804 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
805 info->in[i].si = i;
806 }
807 } else {
808 for (i = first; i <= last; ++i, ++si) {
809 info->in[i].id = i;
810 info->in[i].sn = sn;
811 info->in[i].si = si;
812 if (info->type == PIPE_SHADER_FRAGMENT) {
813 // translate interpolation mode
814 switch (decl->Declaration.Interpolate) {
815 case TGSI_INTERPOLATE_CONSTANT:
816 info->in[i].flat = 1;
817 break;
818 case TGSI_INTERPOLATE_LINEAR:
819 if (sn != TGSI_SEMANTIC_COLOR) // GL_NICEST
820 info->in[i].linear = 1;
821 break;
822 default:
823 break;
824 }
825 if (decl->Declaration.Centroid)
826 info->in[i].centroid = 1;
827 }
828 }
829 }
830 break;
831 case TGSI_FILE_OUTPUT:
832 for (i = first; i <= last; ++i, ++si) {
833 switch (sn) {
834 case TGSI_SEMANTIC_POSITION:
835 if (info->type == PIPE_SHADER_FRAGMENT)
836 info->io.fragDepth = i;
837 else
838 if (clipVertexOutput < 0)
839 clipVertexOutput = i;
840 break;
841 case TGSI_SEMANTIC_COLOR:
842 if (info->type == PIPE_SHADER_FRAGMENT)
843 info->prop.fp.numColourResults++;
844 break;
845 case TGSI_SEMANTIC_EDGEFLAG:
846 info->io.edgeFlagOut = i;
847 break;
848 case TGSI_SEMANTIC_CLIPVERTEX:
849 clipVertexOutput = i;
850 break;
851 case TGSI_SEMANTIC_CLIPDIST:
852 info->io.clipDistanceMask |=
853 decl->Declaration.UsageMask << (si * 4);
854 info->io.genUserClip = -1;
855 break;
856 default:
857 break;
858 }
859 info->out[i].id = i;
860 info->out[i].sn = sn;
861 info->out[i].si = si;
862 }
863 break;
864 case TGSI_FILE_SYSTEM_VALUE:
865 for (i = first; i <= last; ++i, ++si) {
866 info->sv[i].sn = sn;
867 info->sv[i].si = si;
868 info->sv[i].input = inferSysValDirection(sn);
869 }
870 break;
871 case TGSI_FILE_RESOURCE:
872 for (i = first; i <= last; ++i)
873 resourceTargets[i] = decl->Resource.Resource;
874 break;
875 case TGSI_FILE_IMMEDIATE_ARRAY:
876 {
877 if (decl->Dim.Index2D >= immdArrayCount)
878 immdArrayCount = decl->Dim.Index2D + 1;
879 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
880 int c;
881 uint32_t base, count;
882 switch (decl->Declaration.UsageMask) {
883 case 0x1: c = 1; break;
884 case 0x3: c = 2; break;
885 default:
886 c = 4;
887 break;
888 }
889 immdArrays[decl->Dim.Index2D].u32 |= c;
890 count = (last + 1) * c;
891 base = info->immd.bufSize / 4;
892 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
893 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
894 info->immd.bufSize);
895 // NOTE: this assumes array declarations are ordered by Dim.Index2D
896 for (i = 0; i < count; ++i)
897 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
898 }
899 break;
900 case TGSI_FILE_TEMPORARY_ARRAY:
901 {
902 if (decl->Dim.Index2D >= tempArrayCount)
903 tempArrayCount = decl->Dim.Index2D + 1;
904 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
905 int c;
906 uint32_t count;
907 switch (decl->Declaration.UsageMask) {
908 case 0x1: c = 1; break;
909 case 0x3: c = 2; break;
910 default:
911 c = 4;
912 break;
913 }
914 tempArrays[decl->Dim.Index2D].u32 |= c;
915 count = (last + 1) * c;
916 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
917 }
918 break;
919 case TGSI_FILE_NULL:
920 case TGSI_FILE_TEMPORARY:
921 case TGSI_FILE_ADDRESS:
922 case TGSI_FILE_CONSTANT:
923 case TGSI_FILE_IMMEDIATE:
924 case TGSI_FILE_PREDICATE:
925 case TGSI_FILE_SAMPLER:
926 break;
927 default:
928 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
929 return false;
930 }
931 return true;
932 }
933
934 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
935 {
936 return insn.getOpcode() == TGSI_OPCODE_MOV &&
937 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
938 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
939 }
940
941 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
942 {
943 Instruction insn(inst);
944
945 if (insn.dstCount()) {
946 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
947 Instruction::DstRegister dst = insn.getDst(0);
948
949 if (dst.isIndirect(0))
950 for (unsigned i = 0; i < info->numOutputs; ++i)
951 info->out[i].mask = 0xf;
952 else
953 info->out[dst.getIndex(0)].mask |= dst.getMask();
954
955 if (isEdgeFlagPassthrough(insn))
956 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
957 } else
958 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
959 if (insn.getDst(0).isIndirect(0))
960 mainTempsInLMem = TRUE;
961 }
962 }
963
964 for (unsigned s = 0; s < insn.srcCount(); ++s) {
965 Instruction::SrcRegister src = insn.getSrc(s);
966 if (src.getFile() == TGSI_FILE_TEMPORARY)
967 if (src.isIndirect(0))
968 mainTempsInLMem = TRUE;
969 if (src.getFile() != TGSI_FILE_INPUT)
970 continue;
971 unsigned mask = insn.srcMask(s);
972
973 if (src.isIndirect(0)) {
974 for (unsigned i = 0; i < info->numInputs; ++i)
975 info->in[i].mask = 0xf;
976 } else {
977 for (unsigned c = 0; c < 4; ++c) {
978 if (!(mask & (1 << c)))
979 continue;
980 int k = src.getSwizzle(c);
981 int i = src.getIndex(0);
982 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
983 if (k <= TGSI_SWIZZLE_W)
984 info->in[i].mask |= 1 << k;
985 }
986 }
987 }
988 return true;
989 }
990
991 nv50_ir::TexInstruction::Target
992 Instruction::getTexture(const tgsi::Source *code, int s) const
993 {
994 if (insn->Instruction.Texture) {
995 return translateTexture(insn->Texture.Texture);
996 } else {
997 // XXX: indirect access
998 unsigned int r = getSrc(s).getIndex(0);
999 assert(r < code->resourceCount);
1000 return translateTexture(code->resourceTargets[r]);
1001 }
1002 }
1003
1004 } // namespace tgsi
1005
1006 namespace {
1007
1008 using namespace nv50_ir;
1009
1010 class Converter : public BuildUtil
1011 {
1012 public:
1013 Converter(Program *, const tgsi::Source *);
1014 ~Converter();
1015
1016 bool run();
1017
1018 private:
1019 Value *getVertexBase(int s);
1020 Value *fetchSrc(int s, int c);
1021 Value *acquireDst(int d, int c);
1022 void storeDst(int d, int c, Value *);
1023
1024 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1025 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1026 Value *val, Value *ptr);
1027
1028 Value *applySrcMod(Value *, int s, int c);
1029
1030 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1031 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1032 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1033
1034 bool handleInstruction(const struct tgsi_full_instruction *);
1035 void exportOutputs();
1036 inline bool isEndOfSubroutine(uint ip);
1037
1038 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1039
1040 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1041 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1042 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1043 void handleTXF(Value *dst0[4], int R);
1044 void handleTXQ(Value *dst0[4], enum TexQuery);
1045 void handleLIT(Value *dst0[4]);
1046 void handleUserClipPlanes();
1047
1048 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1049
1050 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1051
1052 Value *buildDot(int dim);
1053
1054 private:
1055 const struct tgsi::Source *code;
1056 const struct nv50_ir_prog_info *info;
1057
1058 uint ip; // instruction pointer
1059
1060 tgsi::Instruction tgsi;
1061
1062 DataType dstTy;
1063 DataType srcTy;
1064
1065 DataArray tData; // TGSI_FILE_TEMPORARY
1066 DataArray aData; // TGSI_FILE_ADDRESS
1067 DataArray pData; // TGSI_FILE_PREDICATE
1068 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1069 DataArray *lData; // TGSI_FILE_TEMPORARY_ARRAY
1070 DataArray *iData; // TGSI_FILE_IMMEDIATE_ARRAY
1071
1072 Value *zero;
1073 Value *fragCoord[4];
1074 Value *clipVtx[4];
1075
1076 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1077 uint8_t vtxBaseValid;
1078
1079 Stack condBBs; // fork BB, then else clause BB
1080 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1081 Stack loopBBs; // loop headers
1082 Stack breakBBs; // end of / after loop
1083 Stack entryBBs; // start of current (inlined) subroutine
1084 Stack leaveBBs; // end of current (inlined) subroutine
1085 Stack retIPs; // return instruction pointer
1086 };
1087
1088 Symbol *
1089 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1090 {
1091 const int swz = src.getSwizzle(c);
1092
1093 return makeSym(src.getFile(),
1094 src.is2D() ? src.getIndex(1) : 0,
1095 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1096 src.getIndex(0) * 16 + swz * 4);
1097 }
1098
1099 Symbol *
1100 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1101 {
1102 return makeSym(dst.getFile(),
1103 dst.is2D() ? dst.getIndex(1) : 0,
1104 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1105 dst.getIndex(0) * 16 + c * 4);
1106 }
1107
1108 Symbol *
1109 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1110 {
1111 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1112
1113 sym->reg.fileIndex = fileIdx;
1114
1115 if (idx >= 0) {
1116 if (sym->reg.file == FILE_SHADER_INPUT)
1117 sym->setOffset(info->in[idx].slot[c] * 4);
1118 else
1119 if (sym->reg.file == FILE_SHADER_OUTPUT)
1120 sym->setOffset(info->out[idx].slot[c] * 4);
1121 else
1122 if (sym->reg.file == FILE_SYSTEM_VALUE)
1123 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1124 else
1125 sym->setOffset(address);
1126 } else {
1127 sym->setOffset(address);
1128 }
1129 return sym;
1130 }
1131
1132 static inline uint8_t
1133 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1134 {
1135 uint8_t mode;
1136
1137 if (var->flat)
1138 mode = NV50_IR_INTERP_FLAT;
1139 else
1140 if (var->linear)
1141 mode = NV50_IR_INTERP_LINEAR;
1142 else
1143 mode = NV50_IR_INTERP_PERSPECTIVE;
1144
1145 op = (mode == NV50_IR_INTERP_PERSPECTIVE) ? OP_PINTERP : OP_LINTERP;
1146
1147 if (var->centroid)
1148 mode |= NV50_IR_INTERP_CENTROID;
1149
1150 return mode;
1151 }
1152
1153 Value *
1154 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1155 {
1156 operation op;
1157
1158 // XXX: no way to know interpolation mode if we don't know what's accessed
1159 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1160 src.getIndex(0)], op);
1161
1162 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1163
1164 insn->setDef(0, getScratch());
1165 insn->setSrc(0, srcToSym(src, c));
1166 if (op == OP_PINTERP)
1167 insn->setSrc(1, fragCoord[3]);
1168 if (ptr)
1169 insn->setIndirect(0, 0, ptr);
1170
1171 insn->setInterpolate(mode);
1172
1173 bb->insertTail(insn);
1174 return insn->getDef(0);
1175 }
1176
1177 Value *
1178 Converter::applySrcMod(Value *val, int s, int c)
1179 {
1180 Modifier m = tgsi.getSrc(s).getMod(c);
1181 DataType ty = tgsi.inferSrcType();
1182
1183 if (m & Modifier(NV50_IR_MOD_ABS))
1184 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1185
1186 if (m & Modifier(NV50_IR_MOD_NEG))
1187 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1188
1189 return val;
1190 }
1191
1192 Value *
1193 Converter::getVertexBase(int s)
1194 {
1195 assert(s < 5);
1196 if (!(vtxBaseValid & (1 << s))) {
1197 const int index = tgsi.getSrc(s).getIndex(1);
1198 Value *rel = NULL;
1199 if (tgsi.getSrc(s).isIndirect(1))
1200 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1201 vtxBaseValid |= 1 << s;
1202 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1203 }
1204 return vtxBase[s];
1205 }
1206
1207 Value *
1208 Converter::fetchSrc(int s, int c)
1209 {
1210 Value *res;
1211 Value *ptr = NULL, *dimRel = NULL;
1212
1213 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1214
1215 if (src.isIndirect(0))
1216 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1217
1218 if (src.is2D()) {
1219 switch (src.getFile()) {
1220 case TGSI_FILE_INPUT:
1221 dimRel = getVertexBase(s);
1222 break;
1223 case TGSI_FILE_CONSTANT:
1224 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1225 if (src.isIndirect(1))
1226 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1227 break;
1228 default:
1229 break;
1230 }
1231 }
1232
1233 res = fetchSrc(src, c, ptr);
1234
1235 if (dimRel)
1236 res->getInsn()->setIndirect(0, 1, dimRel);
1237
1238 return applySrcMod(res, s, c);
1239 }
1240
1241 Value *
1242 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1243 {
1244 const int idx = src.getIndex(0);
1245 const int swz = src.getSwizzle(c);
1246
1247 switch (src.getFile()) {
1248 case TGSI_FILE_TEMPORARY:
1249 return tData.load(idx, swz, ptr);
1250 case TGSI_FILE_PREDICATE:
1251 return pData.load(idx, swz, ptr);
1252 case TGSI_FILE_ADDRESS:
1253 return aData.load(idx, swz, ptr);
1254
1255 case TGSI_FILE_TEMPORARY_ARRAY:
1256 assert(src.is2D() && src.getIndex(1) < code->tempArrayCount);
1257 return lData[src.getIndex(1)].load(idx, swz, ptr);
1258 case TGSI_FILE_IMMEDIATE_ARRAY:
1259 assert(src.is2D() && src.getIndex(1) < code->immdArrayCount);
1260 return iData[src.getIndex(1)].load(idx, swz, ptr);
1261
1262 case TGSI_FILE_IMMEDIATE:
1263 assert(!ptr);
1264 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1265
1266 case TGSI_FILE_CONSTANT:
1267 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1268
1269 case TGSI_FILE_INPUT:
1270 if (prog->getType() == Program::TYPE_FRAGMENT) {
1271 // don't load masked inputs, won't be assigned a slot
1272 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1273 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1274 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1275 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1276 return interpolate(src, c, ptr);
1277 }
1278 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1279
1280 case TGSI_FILE_SYSTEM_VALUE:
1281 assert(!ptr);
1282 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1283
1284 case TGSI_FILE_OUTPUT:
1285 case TGSI_FILE_RESOURCE:
1286 case TGSI_FILE_SAMPLER:
1287 case TGSI_FILE_NULL:
1288 default:
1289 assert(!"invalid/unhandled TGSI source file");
1290 return NULL;
1291 }
1292 }
1293
1294 Value *
1295 Converter::acquireDst(int d, int c)
1296 {
1297 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1298
1299 if (dst.isMasked(c))
1300 return NULL;
1301 if (dst.isIndirect(0))
1302 return getScratch();
1303
1304 const int idx = dst.getIndex(0);
1305
1306 switch (dst.getFile()) {
1307 case TGSI_FILE_TEMPORARY:
1308 return tData.acquire(idx, c);
1309 case TGSI_FILE_TEMPORARY_ARRAY:
1310 return getScratch();
1311 case TGSI_FILE_PREDICATE:
1312 return pData.acquire(idx, c);
1313 case TGSI_FILE_ADDRESS:
1314 return aData.acquire(idx, c);
1315
1316 case TGSI_FILE_OUTPUT:
1317 if (prog->getType() == Program::TYPE_FRAGMENT)
1318 return oData.acquire(idx, c);
1319 // fall through
1320 case TGSI_FILE_SYSTEM_VALUE:
1321 return getScratch();
1322
1323 default:
1324 assert(!"invalid dst file");
1325 return NULL;
1326 }
1327 }
1328
1329 void
1330 Converter::storeDst(int d, int c, Value *val)
1331 {
1332 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1333
1334 switch (tgsi.getSaturate()) {
1335 case TGSI_SAT_NONE:
1336 break;
1337 case TGSI_SAT_ZERO_ONE:
1338 mkOp1(OP_SAT, dstTy, val, val);
1339 break;
1340 case TGSI_SAT_MINUS_PLUS_ONE:
1341 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1342 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1343 break;
1344 default:
1345 assert(!"invalid saturation mode");
1346 break;
1347 }
1348
1349 Value *ptr = dst.isIndirect(0) ?
1350 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1351
1352 if (info->io.genUserClip > 0 &&
1353 dst.getFile() == TGSI_FILE_OUTPUT &&
1354 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1355 mkMov(clipVtx[c], val);
1356 val = clipVtx[c];
1357 }
1358
1359 storeDst(dst, c, val, ptr);
1360 }
1361
1362 void
1363 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1364 Value *val, Value *ptr)
1365 {
1366 const int idx = dst.getIndex(0);
1367
1368 switch (dst.getFile()) {
1369 case TGSI_FILE_TEMPORARY:
1370 tData.store(idx, c, ptr, val);
1371 break;
1372 case TGSI_FILE_TEMPORARY_ARRAY:
1373 assert(dst.is2D() && dst.getIndex(1) < code->tempArrayCount);
1374 lData[dst.getIndex(1)].store(idx, c, ptr, val);
1375 break;
1376 case TGSI_FILE_PREDICATE:
1377 pData.store(idx, c, ptr, val);
1378 break;
1379 case TGSI_FILE_ADDRESS:
1380 aData.store(idx, c, ptr, val);
1381 break;
1382
1383 case TGSI_FILE_OUTPUT:
1384 if (prog->getType() == Program::TYPE_FRAGMENT)
1385 oData.store(idx, c, ptr, val);
1386 else
1387 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1388 break;
1389
1390 case TGSI_FILE_SYSTEM_VALUE:
1391 assert(!ptr);
1392 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1393 break;
1394
1395 default:
1396 assert(!"invalid dst file");
1397 break;
1398 }
1399 }
1400
1401 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1402 for (chan = 0; chan < 4; ++chan) \
1403 if (!inst.getDst(d).isMasked(chan))
1404
1405 Value *
1406 Converter::buildDot(int dim)
1407 {
1408 assert(dim > 0);
1409
1410 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1411 Value *dotp = getScratch();
1412
1413 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1414
1415 for (int c = 1; c < dim; ++c) {
1416 src0 = fetchSrc(0, c);
1417 src1 = fetchSrc(1, c);
1418 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1419 }
1420 return dotp;
1421 }
1422
1423 void
1424 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1425 {
1426 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1427 join->fixed = 1;
1428 conv->insertHead(join);
1429
1430 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1431 fork->insertBefore(fork->getExit(), fork->joinAt);
1432 }
1433
1434 void
1435 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1436 {
1437 unsigned rIdx = 0, sIdx = 0;
1438
1439 if (R >= 0)
1440 rIdx = tgsi.getSrc(R).getIndex(0);
1441 if (S >= 0)
1442 sIdx = tgsi.getSrc(S).getIndex(0);
1443
1444 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1445
1446 if (tgsi.getSrc(R).isIndirect(0)) {
1447 tex->tex.rIndirectSrc = s;
1448 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1449 }
1450 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1451 tex->tex.sIndirectSrc = s;
1452 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1453 }
1454 }
1455
1456 void
1457 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1458 {
1459 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1460 tex->tex.query = query;
1461 unsigned int c, d;
1462
1463 for (d = 0, c = 0; c < 4; ++c) {
1464 if (!dst0[c])
1465 continue;
1466 tex->tex.mask |= 1 << c;
1467 tex->setDef(d++, dst0[c]);
1468 }
1469 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1470
1471 setTexRS(tex, c, 1, -1);
1472
1473 bb->insertTail(tex);
1474 }
1475
1476 void
1477 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1478 {
1479 Value *proj = fetchSrc(0, 3);
1480 Instruction *insn = proj->getUniqueInsn();
1481 int c;
1482
1483 if (insn->op == OP_PINTERP) {
1484 bb->insertTail(insn = insn->clone(true));
1485 insn->op = OP_LINTERP;
1486 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1487 insn->setSrc(1, NULL);
1488 proj = insn->getDef(0);
1489 }
1490 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1491
1492 for (c = 0; c < 4; ++c) {
1493 if (!(mask & (1 << c)))
1494 continue;
1495 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1496 continue;
1497 mask &= ~(1 << c);
1498
1499 bb->insertTail(insn = insn->clone(true));
1500 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1501 insn->setSrc(1, proj);
1502 dst[c] = insn->getDef(0);
1503 }
1504 if (!mask)
1505 return;
1506
1507 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1508
1509 for (c = 0; c < 4; ++c)
1510 if (mask & (1 << c))
1511 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1512 }
1513
1514 // order of nv50 ir sources: x y z layer lod/bias shadow
1515 // order of TGSI TEX sources: x y z layer shadow lod/bias
1516 // lowering will finally set the hw specific order (like array first on nvc0)
1517 void
1518 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1519 {
1520 Value *val;
1521 Value *arg[4], *src[8];
1522 Value *lod = NULL, *shd = NULL;
1523 unsigned int s, c, d;
1524 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1525
1526 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1527
1528 for (s = 0; s < tgt.getArgCount(); ++s)
1529 arg[s] = src[s] = fetchSrc(0, s);
1530
1531 if (texi->op == OP_TXL || texi->op == OP_TXB)
1532 lod = fetchSrc(L >> 4, L & 3);
1533
1534 if (C == 0x0f)
1535 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1536
1537 if (tgt.isShadow())
1538 shd = fetchSrc(C >> 4, C & 3);
1539
1540 if (texi->op == OP_TXD) {
1541 for (c = 0; c < tgt.getDim(); ++c) {
1542 texi->dPdx[c] = fetchSrc(Dx >> 4, (Dx & 3) + c);
1543 texi->dPdy[c] = fetchSrc(Dy >> 4, (Dy & 3) + c);
1544 }
1545 }
1546
1547 // cube textures don't care about projection value, it's divided out
1548 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1549 unsigned int n = tgt.getDim();
1550 if (shd) {
1551 arg[n] = shd;
1552 ++n;
1553 assert(tgt.getDim() == tgt.getArgCount());
1554 }
1555 loadProjTexCoords(src, arg, (1 << n) - 1);
1556 if (shd)
1557 shd = src[n - 1];
1558 }
1559
1560 if (tgt.isCube()) {
1561 for (c = 0; c < 3; ++c)
1562 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1563 val = getScratch();
1564 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1565 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1566 mkOp1(OP_RCP, TYPE_F32, val, val);
1567 for (c = 0; c < 3; ++c)
1568 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1569 }
1570
1571 for (c = 0, d = 0; c < 4; ++c) {
1572 if (dst[c]) {
1573 texi->setDef(d++, dst[c]);
1574 texi->tex.mask |= 1 << c;
1575 } else {
1576 // NOTE: maybe hook up def too, for CSE
1577 }
1578 }
1579 for (s = 0; s < tgt.getArgCount(); ++s)
1580 texi->setSrc(s, src[s]);
1581 if (lod)
1582 texi->setSrc(s++, lod);
1583 if (shd)
1584 texi->setSrc(s++, shd);
1585
1586 setTexRS(texi, s, R, S);
1587
1588 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1589 texi->tex.levelZero = true;
1590
1591 bb->insertTail(texi);
1592 }
1593
1594 // 1st source: xyz = coordinates, w = lod
1595 // 2nd source: offset
1596 void
1597 Converter::handleTXF(Value *dst[4], int R)
1598 {
1599 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1600 unsigned int c, d, s;
1601
1602 texi->tex.target = tgsi.getTexture(code, R);
1603
1604 for (c = 0, d = 0; c < 4; ++c) {
1605 if (dst[c]) {
1606 texi->setDef(d++, dst[c]);
1607 texi->tex.mask |= 1 << c;
1608 }
1609 }
1610 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1611 texi->setSrc(c, fetchSrc(0, c));
1612 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1613
1614 setTexRS(texi, c, R, -1);
1615
1616 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1617 for (c = 0; c < 3; ++c) {
1618 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1619 if (texi->tex.offset[s][c])
1620 texi->tex.useOffsets = s + 1;
1621 }
1622 }
1623
1624 bb->insertTail(texi);
1625 }
1626
1627 void
1628 Converter::handleLIT(Value *dst0[4])
1629 {
1630 Value *val0 = NULL;
1631 unsigned int mask = tgsi.getDst(0).getMask();
1632
1633 if (mask & (1 << 0))
1634 loadImm(dst0[0], 1.0f);
1635
1636 if (mask & (1 << 3))
1637 loadImm(dst0[3], 1.0f);
1638
1639 if (mask & (3 << 1)) {
1640 val0 = getScratch();
1641 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1642 if (mask & (1 << 1))
1643 mkMov(dst0[1], val0);
1644 }
1645
1646 if (mask & (1 << 2)) {
1647 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1648 Value *val1 = getScratch(), *val3 = getScratch();
1649
1650 Value *pos128 = loadImm(NULL, +127.999999f);
1651 Value *neg128 = loadImm(NULL, -127.999999f);
1652
1653 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1654 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1655 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1656 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1657
1658 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1659 }
1660 }
1661
1662 bool
1663 Converter::isEndOfSubroutine(uint ip)
1664 {
1665 assert(ip < code->scan.num_instructions);
1666 tgsi::Instruction insn(&code->insns[ip]);
1667 return (insn.getOpcode() == TGSI_OPCODE_END ||
1668 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1669 // does END occur at end of main or the very end ?
1670 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1671 }
1672
1673 bool
1674 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1675 {
1676 Value *dst0[4], *rDst0[4];
1677 Value *src0, *src1, *src2;
1678 Value *val0, *val1;
1679 int c;
1680
1681 tgsi = tgsi::Instruction(insn);
1682
1683 bool useScratchDst = tgsi.checkDstSrcAliasing();
1684
1685 operation op = tgsi.getOP();
1686 dstTy = tgsi.inferDstType();
1687 srcTy = tgsi.inferSrcType();
1688
1689 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1690
1691 if (tgsi.dstCount()) {
1692 for (c = 0; c < 4; ++c) {
1693 rDst0[c] = acquireDst(0, c);
1694 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1695 }
1696 }
1697
1698 switch (tgsi.getOpcode()) {
1699 case TGSI_OPCODE_ADD:
1700 case TGSI_OPCODE_UADD:
1701 case TGSI_OPCODE_AND:
1702 case TGSI_OPCODE_DIV:
1703 case TGSI_OPCODE_IDIV:
1704 case TGSI_OPCODE_UDIV:
1705 case TGSI_OPCODE_MAX:
1706 case TGSI_OPCODE_MIN:
1707 case TGSI_OPCODE_IMAX:
1708 case TGSI_OPCODE_IMIN:
1709 case TGSI_OPCODE_UMAX:
1710 case TGSI_OPCODE_UMIN:
1711 case TGSI_OPCODE_MOD:
1712 case TGSI_OPCODE_UMOD:
1713 case TGSI_OPCODE_MUL:
1714 case TGSI_OPCODE_UMUL:
1715 case TGSI_OPCODE_OR:
1716 case TGSI_OPCODE_POW:
1717 case TGSI_OPCODE_SHL:
1718 case TGSI_OPCODE_ISHR:
1719 case TGSI_OPCODE_USHR:
1720 case TGSI_OPCODE_SUB:
1721 case TGSI_OPCODE_XOR:
1722 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1723 src0 = fetchSrc(0, c);
1724 src1 = fetchSrc(1, c);
1725 mkOp2(op, dstTy, dst0[c], src0, src1);
1726 }
1727 break;
1728 case TGSI_OPCODE_MAD:
1729 case TGSI_OPCODE_UMAD:
1730 case TGSI_OPCODE_SAD:
1731 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1732 src0 = fetchSrc(0, c);
1733 src1 = fetchSrc(1, c);
1734 src2 = fetchSrc(2, c);
1735 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1736 }
1737 break;
1738 case TGSI_OPCODE_MOV:
1739 case TGSI_OPCODE_ABS:
1740 case TGSI_OPCODE_CEIL:
1741 case TGSI_OPCODE_FLR:
1742 case TGSI_OPCODE_TRUNC:
1743 case TGSI_OPCODE_RCP:
1744 case TGSI_OPCODE_IABS:
1745 case TGSI_OPCODE_INEG:
1746 case TGSI_OPCODE_NOT:
1747 case TGSI_OPCODE_DDX:
1748 case TGSI_OPCODE_DDY:
1749 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1750 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1751 break;
1752 case TGSI_OPCODE_RSQ:
1753 src0 = fetchSrc(0, 0);
1754 val0 = getScratch();
1755 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1756 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1757 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1758 mkMov(dst0[c], val0);
1759 break;
1760 case TGSI_OPCODE_ARL:
1761 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1762 src0 = fetchSrc(0, c);
1763 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1764 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1765 }
1766 break;
1767 case TGSI_OPCODE_UARL:
1768 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1769 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1770 break;
1771 case TGSI_OPCODE_EX2:
1772 case TGSI_OPCODE_LG2:
1773 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1774 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1775 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1776 break;
1777 case TGSI_OPCODE_COS:
1778 case TGSI_OPCODE_SIN:
1779 val0 = getScratch();
1780 if (mask & 7) {
1781 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1782 mkOp1(op, TYPE_F32, val0, val0);
1783 for (c = 0; c < 3; ++c)
1784 if (dst0[c])
1785 mkMov(dst0[c], val0);
1786 }
1787 if (dst0[3]) {
1788 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1789 mkOp1(op, TYPE_F32, dst0[3], val0);
1790 }
1791 break;
1792 case TGSI_OPCODE_SCS:
1793 if (mask & 3) {
1794 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1795 if (dst0[0])
1796 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1797 if (dst0[1])
1798 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1799 }
1800 if (dst0[2])
1801 loadImm(dst0[2], 0.0f);
1802 if (dst0[3])
1803 loadImm(dst0[3], 1.0f);
1804 break;
1805 case TGSI_OPCODE_EXP:
1806 src0 = fetchSrc(0, 0);
1807 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1808 if (dst0[1])
1809 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1810 if (dst0[0])
1811 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1812 if (dst0[2])
1813 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1814 if (dst0[3])
1815 loadImm(dst0[3], 1.0f);
1816 break;
1817 case TGSI_OPCODE_LOG:
1818 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1819 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1820 if (dst0[0] || dst0[1])
1821 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1822 if (dst0[1]) {
1823 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1824 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1825 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1826 }
1827 if (dst0[3])
1828 loadImm(dst0[3], 1.0f);
1829 break;
1830 case TGSI_OPCODE_DP2:
1831 val0 = buildDot(2);
1832 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1833 mkMov(dst0[c], val0);
1834 break;
1835 case TGSI_OPCODE_DP3:
1836 val0 = buildDot(3);
1837 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1838 mkMov(dst0[c], val0);
1839 break;
1840 case TGSI_OPCODE_DP4:
1841 val0 = buildDot(4);
1842 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1843 mkMov(dst0[c], val0);
1844 break;
1845 case TGSI_OPCODE_DPH:
1846 val0 = buildDot(3);
1847 src1 = fetchSrc(1, 3);
1848 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1849 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1850 mkMov(dst0[c], val0);
1851 break;
1852 case TGSI_OPCODE_DST:
1853 if (dst0[0])
1854 loadImm(dst0[0], 1.0f);
1855 if (dst0[1]) {
1856 src0 = fetchSrc(0, 1);
1857 src1 = fetchSrc(1, 1);
1858 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1859 }
1860 if (dst0[2])
1861 mkMov(dst0[2], fetchSrc(0, 2));
1862 if (dst0[3])
1863 mkMov(dst0[3], fetchSrc(1, 3));
1864 break;
1865 case TGSI_OPCODE_LRP:
1866 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1867 src0 = fetchSrc(0, c);
1868 src1 = fetchSrc(1, c);
1869 src2 = fetchSrc(2, c);
1870 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1871 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1872 }
1873 break;
1874 case TGSI_OPCODE_LIT:
1875 handleLIT(dst0);
1876 break;
1877 case TGSI_OPCODE_XPD:
1878 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1879 if (c < 3) {
1880 val0 = getSSA();
1881 src0 = fetchSrc(1, (c + 1) % 3);
1882 src1 = fetchSrc(0, (c + 2) % 3);
1883 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1884 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1885
1886 src0 = fetchSrc(0, (c + 1) % 3);
1887 src1 = fetchSrc(1, (c + 2) % 3);
1888 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1889 } else {
1890 loadImm(dst0[c], 1.0f);
1891 }
1892 }
1893 break;
1894 case TGSI_OPCODE_SSG:
1895 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1896 src0 = fetchSrc(0, c);
1897 val0 = getScratch();
1898 val1 = getScratch();
1899 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, src0, zero);
1900 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, src0, zero);
1901 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1902 }
1903 break;
1904 case TGSI_OPCODE_UCMP:
1905 case TGSI_OPCODE_CMP:
1906 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1907 src0 = fetchSrc(0, c);
1908 src1 = fetchSrc(1, c);
1909 src2 = fetchSrc(2, c);
1910 if (src1 == src2)
1911 mkMov(dst0[c], src1);
1912 else
1913 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1914 srcTy, dst0[c], src1, src2, src0);
1915 }
1916 break;
1917 case TGSI_OPCODE_FRC:
1918 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1919 src0 = fetchSrc(0, c);
1920 val0 = getScratch();
1921 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1922 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1923 }
1924 break;
1925 case TGSI_OPCODE_ROUND:
1926 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1927 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
1928 ->rnd = ROUND_NI;
1929 break;
1930 case TGSI_OPCODE_CLAMP:
1931 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1932 src0 = fetchSrc(0, c);
1933 src1 = fetchSrc(1, c);
1934 src2 = fetchSrc(2, c);
1935 val0 = getScratch();
1936 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
1937 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
1938 }
1939 break;
1940 case TGSI_OPCODE_SLT:
1941 case TGSI_OPCODE_SGE:
1942 case TGSI_OPCODE_SEQ:
1943 case TGSI_OPCODE_SFL:
1944 case TGSI_OPCODE_SGT:
1945 case TGSI_OPCODE_SLE:
1946 case TGSI_OPCODE_SNE:
1947 case TGSI_OPCODE_STR:
1948 case TGSI_OPCODE_ISGE:
1949 case TGSI_OPCODE_ISLT:
1950 case TGSI_OPCODE_USEQ:
1951 case TGSI_OPCODE_USGE:
1952 case TGSI_OPCODE_USLT:
1953 case TGSI_OPCODE_USNE:
1954 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1955 src0 = fetchSrc(0, c);
1956 src1 = fetchSrc(1, c);
1957 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
1958 }
1959 break;
1960 case TGSI_OPCODE_KIL:
1961 val0 = new_LValue(func, FILE_PREDICATE);
1962 for (c = 0; c < 4; ++c) {
1963 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
1964 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
1965 }
1966 break;
1967 case TGSI_OPCODE_KILP:
1968 mkOp(OP_DISCARD, TYPE_NONE, NULL);
1969 break;
1970 case TGSI_OPCODE_TEX:
1971 case TGSI_OPCODE_TXB:
1972 case TGSI_OPCODE_TXL:
1973 case TGSI_OPCODE_TXP:
1974 // R S L C Dx Dy
1975 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
1976 break;
1977 case TGSI_OPCODE_TXD:
1978 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
1979 break;
1980 case TGSI_OPCODE_SAMPLE:
1981 case TGSI_OPCODE_SAMPLE_B:
1982 case TGSI_OPCODE_SAMPLE_D:
1983 case TGSI_OPCODE_SAMPLE_L:
1984 case TGSI_OPCODE_SAMPLE_C:
1985 case TGSI_OPCODE_SAMPLE_C_LZ:
1986 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
1987 break;
1988 case TGSI_OPCODE_TXF:
1989 case TGSI_OPCODE_LOAD:
1990 handleTXF(dst0, 1);
1991 break;
1992 case TGSI_OPCODE_TXQ:
1993 case TGSI_OPCODE_RESINFO:
1994 handleTXQ(dst0, TXQ_DIMS);
1995 break;
1996 case TGSI_OPCODE_F2I:
1997 case TGSI_OPCODE_F2U:
1998 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1999 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2000 break;
2001 case TGSI_OPCODE_I2F:
2002 case TGSI_OPCODE_U2F:
2003 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2004 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2005 break;
2006 case TGSI_OPCODE_EMIT:
2007 case TGSI_OPCODE_ENDPRIM:
2008 // get vertex stream if specified (must be immediate)
2009 src0 = tgsi.srcCount() ?
2010 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2011 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2012 break;
2013 case TGSI_OPCODE_IF:
2014 {
2015 BasicBlock *ifBB = new BasicBlock(func);
2016
2017 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2018 condBBs.push(bb);
2019 joinBBs.push(bb);
2020
2021 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2022
2023 setPosition(ifBB, true);
2024 }
2025 break;
2026 case TGSI_OPCODE_ELSE:
2027 {
2028 BasicBlock *elseBB = new BasicBlock(func);
2029 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2030
2031 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2032 condBBs.push(bb);
2033
2034 forkBB->getExit()->asFlow()->target.bb = elseBB;
2035 if (!bb->isTerminated())
2036 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2037
2038 setPosition(elseBB, true);
2039 }
2040 break;
2041 case TGSI_OPCODE_ENDIF:
2042 {
2043 BasicBlock *convBB = new BasicBlock(func);
2044 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2045 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2046
2047 if (!bb->isTerminated()) {
2048 // we only want join if none of the clauses ended with CONT/BREAK/RET
2049 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2050 insertConvergenceOps(convBB, forkBB);
2051 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2052 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2053 }
2054
2055 if (prevBB->getExit()->op == OP_BRA) {
2056 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2057 prevBB->getExit()->asFlow()->target.bb = convBB;
2058 }
2059 setPosition(convBB, true);
2060 }
2061 break;
2062 case TGSI_OPCODE_BGNLOOP:
2063 {
2064 BasicBlock *lbgnBB = new BasicBlock(func);
2065 BasicBlock *lbrkBB = new BasicBlock(func);
2066
2067 loopBBs.push(lbgnBB);
2068 breakBBs.push(lbrkBB);
2069 if (loopBBs.getSize() > func->loopNestingBound)
2070 func->loopNestingBound++;
2071
2072 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2073
2074 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2075 setPosition(lbgnBB, true);
2076 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2077 }
2078 break;
2079 case TGSI_OPCODE_ENDLOOP:
2080 {
2081 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2082
2083 if (!bb->isTerminated()) {
2084 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2085 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2086 }
2087 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2088 }
2089 break;
2090 case TGSI_OPCODE_BRK:
2091 {
2092 if (bb->isTerminated())
2093 break;
2094 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2095 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2096 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2097 }
2098 break;
2099 case TGSI_OPCODE_CONT:
2100 {
2101 if (bb->isTerminated())
2102 break;
2103 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2104 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2105 contBB->explicitCont = true;
2106 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2107 }
2108 break;
2109 case TGSI_OPCODE_BGNSUB:
2110 {
2111 if (!retIPs.getSize()) {
2112 // end of main function
2113 ip = code->scan.num_instructions - 2; // goto END
2114 return true;
2115 }
2116 BasicBlock *entry = new BasicBlock(func);
2117 BasicBlock *leave = new BasicBlock(func);
2118 entryBBs.push(entry);
2119 leaveBBs.push(leave);
2120 bb->cfg.attach(&entry->cfg, Graph::Edge::TREE);
2121 setPosition(entry, true);
2122 }
2123 return true;
2124 case TGSI_OPCODE_ENDSUB:
2125 {
2126 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2127 entryBBs.pop();
2128 bb->cfg.attach(&leave->cfg, Graph::Edge::TREE);
2129 setPosition(leave, true);
2130 ip = retIPs.pop().u.u;
2131 }
2132 return true;
2133 case TGSI_OPCODE_CAL:
2134 // we don't have function declarations, so inline everything
2135 retIPs.push(ip);
2136 ip = code->subroutines[tgsi.getLabel()].pc - 1; // +1 after return
2137 return true;
2138 case TGSI_OPCODE_RET:
2139 {
2140 if (bb->isTerminated())
2141 return true;
2142 BasicBlock *entry = reinterpret_cast<BasicBlock *>(entryBBs.peek().u.p);
2143 BasicBlock *leave = reinterpret_cast<BasicBlock *>(leaveBBs.peek().u.p);
2144 if (!isEndOfSubroutine(ip + 1)) {
2145 // insert a PRERET at the entry if this is an early return
2146 FlowInstruction *preRet = new_FlowInstruction(func, OP_PRERET, leave);
2147 preRet->fixed = 1;
2148 entry->insertHead(preRet);
2149 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2150 }
2151 // everything inlined so RET serves only to wrap up the stack
2152 if (entry->getEntry() && entry->getEntry()->op == OP_PRERET)
2153 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2154 }
2155 break;
2156 case TGSI_OPCODE_END:
2157 {
2158 // attach and generate epilogue code
2159 BasicBlock *epilogue = reinterpret_cast<BasicBlock *>(leaveBBs.pop().u.p);
2160 entryBBs.pop();
2161 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2162 setPosition(epilogue, true);
2163 if (prog->getType() == Program::TYPE_FRAGMENT)
2164 exportOutputs();
2165 if (info->io.genUserClip > 0)
2166 handleUserClipPlanes();
2167 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2168 }
2169 break;
2170 case TGSI_OPCODE_SWITCH:
2171 case TGSI_OPCODE_CASE:
2172 ERROR("switch/case opcode encountered, should have been lowered\n");
2173 abort();
2174 break;
2175 default:
2176 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2177 assert(0);
2178 break;
2179 }
2180
2181 if (tgsi.dstCount()) {
2182 for (c = 0; c < 4; ++c) {
2183 if (!dst0[c])
2184 continue;
2185 if (dst0[c] != rDst0[c])
2186 mkMov(rDst0[c], dst0[c]);
2187 storeDst(0, c, rDst0[c]);
2188 }
2189 }
2190 vtxBaseValid = 0;
2191
2192 return true;
2193 }
2194
2195 void
2196 Converter::handleUserClipPlanes()
2197 {
2198 Value *res[8];
2199 int i, c;
2200
2201 for (c = 0; c < 4; ++c) {
2202 for (i = 0; i < info->io.genUserClip; ++i) {
2203 Value *ucp;
2204 ucp = mkLoad(TYPE_F32, mkSymbol(FILE_MEMORY_CONST, 15, TYPE_F32,
2205 i * 16 + c * 4), NULL);
2206 if (c == 0)
2207 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2208 else
2209 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2210 }
2211 }
2212
2213 for (i = 0; i < info->io.genUserClip; ++i)
2214 mkOp2(OP_WRSV, TYPE_F32, NULL, mkSysVal(SV_CLIP_DISTANCE, i), res[i]);
2215 }
2216
2217 void
2218 Converter::exportOutputs()
2219 {
2220 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2221 for (unsigned int c = 0; c < 4; ++c) {
2222 if (!oData.exists(i, c))
2223 continue;
2224 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2225 info->out[i].slot[c] * 4);
2226 Value *val = oData.load(i, c, NULL);
2227 if (val)
2228 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2229 }
2230 }
2231 }
2232
2233 Converter::Converter(Program *ir, const tgsi::Source *src)
2234 : code(src),
2235 tgsi(NULL),
2236 tData(this), aData(this), pData(this), oData(this)
2237 {
2238 prog = ir;
2239 info = code->info;
2240
2241 DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2242
2243 tData.setup(0, code->fileSize(TGSI_FILE_TEMPORARY), 4, 4, tFile);
2244 pData.setup(0, code->fileSize(TGSI_FILE_PREDICATE), 4, 4, FILE_PREDICATE);
2245 aData.setup(0, code->fileSize(TGSI_FILE_ADDRESS), 4, 4, FILE_ADDRESS);
2246 oData.setup(0, code->fileSize(TGSI_FILE_OUTPUT), 4, 4, FILE_GPR);
2247
2248 lData = NULL;
2249 iData = NULL;
2250
2251 zero = mkImm((uint32_t)0);
2252
2253 vtxBaseValid = 0;
2254 }
2255
2256 Converter::~Converter()
2257 {
2258 if (lData)
2259 delete[] lData;
2260 if (iData)
2261 delete[] iData;
2262 }
2263
2264 bool
2265 Converter::run()
2266 {
2267 BasicBlock *entry = new BasicBlock(prog->main);
2268 BasicBlock *leave = new BasicBlock(prog->main);
2269
2270 if (code->tempArrayCount && !lData) {
2271 uint32_t volume = 0;
2272 lData = new DataArray[code->tempArrayCount];
2273 if (!lData)
2274 return false;
2275 for (int i = 0; i < code->tempArrayCount; ++i) {
2276 int len = code->tempArrays[i].u32 >> 2;
2277 int dim = code->tempArrays[i].u32 & 3;
2278 lData[i].setParent(this);
2279 lData[i].setup(volume, len, dim, 4, FILE_MEMORY_LOCAL);
2280 volume += (len * dim * 4 + 0xf) & ~0xf;
2281 }
2282 }
2283 if (code->immdArrayCount && !iData) {
2284 uint32_t volume = 0;
2285 iData = new DataArray[code->immdArrayCount];
2286 if (!iData)
2287 return false;
2288 for (int i = 0; i < code->immdArrayCount; ++i) {
2289 int len = code->immdArrays[i].u32 >> 2;
2290 int dim = code->immdArrays[i].u32 & 3;
2291 iData[i].setParent(this);
2292 iData[i].setup(volume, len, dim, 4, FILE_MEMORY_CONST, 14);
2293 volume += (len * dim * 4 + 0xf) & ~0xf;
2294 }
2295 }
2296
2297 prog->main->setEntry(entry);
2298 prog->main->setExit(leave);
2299
2300 setPosition(entry, true);
2301 entryBBs.push(entry);
2302 leaveBBs.push(leave);
2303
2304 if (info->io.genUserClip > 0) {
2305 for (int c = 0; c < 4; ++c)
2306 clipVtx[c] = getScratch();
2307 }
2308
2309 if (prog->getType() == Program::TYPE_FRAGMENT) {
2310 Symbol *sv = mkSysVal(SV_POSITION, 3);
2311 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2312 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2313 }
2314
2315 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2316 if (!handleInstruction(&code->insns[ip]))
2317 return false;
2318 }
2319 return true;
2320 }
2321
2322 } // unnamed namespace
2323
2324 namespace nv50_ir {
2325
2326 bool
2327 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2328 {
2329 tgsi::Source src(info);
2330 if (!src.scanSource())
2331 return false;
2332
2333 Converter builder(this, &src);
2334 return builder.run();
2335 }
2336
2337 } // namespace nv50_ir