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[mesa.git] / src / gallium / drivers / nv50 / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 extern "C" {
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 }
27
28 #include "nv50_ir.h"
29 #include "nv50_ir_util.h"
30 #include "nv50_ir_build_util.h"
31
32 namespace tgsi {
33
34 class Source;
35
36 static nv50_ir::operation translateOpcode(uint opcode);
37 static nv50_ir::DataFile translateFile(uint file);
38 static nv50_ir::TexTarget translateTexture(uint texTarg);
39 static nv50_ir::SVSemantic translateSysVal(uint sysval);
40
41 class Instruction
42 {
43 public:
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
45
46 class SrcRegister
47 {
48 public:
49 SrcRegister(const struct tgsi_full_src_register *src)
50 : reg(src->Register),
51 fsr(src)
52 { }
53
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
55
56 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
57 {
58 struct tgsi_src_register reg;
59 memset(&reg, 0, sizeof(reg));
60 reg.Index = off.Index;
61 reg.File = off.File;
62 reg.SwizzleX = off.SwizzleX;
63 reg.SwizzleY = off.SwizzleY;
64 reg.SwizzleZ = off.SwizzleZ;
65 return reg;
66 }
67
68 SrcRegister(const struct tgsi_texture_offset& off) :
69 reg(offsetToSrc(off)),
70 fsr(NULL)
71 { }
72
73 uint getFile() const { return reg.File; }
74
75 bool is2D() const { return reg.Dimension; }
76
77 bool isIndirect(int dim) const
78 {
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
80 }
81
82 int getIndex(int dim) const
83 {
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
85 }
86
87 int getSwizzle(int chan) const
88 {
89 return tgsi_util_get_src_register_swizzle(&reg, chan);
90 }
91
92 nv50_ir::Modifier getMod(int chan) const;
93
94 SrcRegister getIndirect(int dim) const
95 {
96 assert(fsr && isIndirect(dim));
97 if (dim)
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect);
100 }
101
102 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
103 {
104 assert(reg.File == TGSI_FILE_IMMEDIATE);
105 assert(!reg.Absolute);
106 assert(!reg.Negate);
107 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
108 }
109
110 private:
111 const struct tgsi_src_register reg;
112 const struct tgsi_full_src_register *fsr;
113 };
114
115 class DstRegister
116 {
117 public:
118 DstRegister(const struct tgsi_full_dst_register *dst)
119 : reg(dst->Register),
120 fdr(dst)
121 { }
122
123 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
124
125 uint getFile() const { return reg.File; }
126
127 bool is2D() const { return reg.Dimension; }
128
129 bool isIndirect(int dim) const
130 {
131 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
132 }
133
134 int getIndex(int dim) const
135 {
136 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
137 }
138
139 unsigned int getMask() const { return reg.WriteMask; }
140
141 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
142
143 SrcRegister getIndirect(int dim) const
144 {
145 assert(fdr && isIndirect(dim));
146 if (dim)
147 return SrcRegister(fdr->DimIndirect);
148 return SrcRegister(fdr->Indirect);
149 }
150
151 private:
152 const struct tgsi_dst_register reg;
153 const struct tgsi_full_dst_register *fdr;
154 };
155
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
157
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
160
161 // mask of used components of source s
162 unsigned int srcMask(unsigned int s) const;
163
164 SrcRegister getSrc(unsigned int s) const
165 {
166 assert(s < srcCount());
167 return SrcRegister(&insn->Src[s]);
168 }
169
170 DstRegister getDst(unsigned int d) const
171 {
172 assert(d < dstCount());
173 return DstRegister(&insn->Dst[d]);
174 }
175
176 SrcRegister getTexOffset(unsigned int i) const
177 {
178 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
179 return SrcRegister(insn->TexOffsets[i]);
180 }
181
182 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
183
184 bool checkDstSrcAliasing() const;
185
186 inline nv50_ir::operation getOP() const {
187 return translateOpcode(getOpcode()); }
188
189 nv50_ir::DataType inferSrcType() const;
190 nv50_ir::DataType inferDstType() const;
191
192 nv50_ir::CondCode getSetCond() const;
193
194 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
195
196 inline uint getLabel() { return insn->Label.Label; }
197
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
199
200 void print() const
201 {
202 tgsi_dump_instruction(insn, 1);
203 }
204
205 private:
206 const struct tgsi_full_instruction *insn;
207 };
208
209 unsigned int Instruction::srcMask(unsigned int s) const
210 {
211 unsigned int mask = insn->Dst[0].Register.WriteMask;
212
213 switch (insn->Instruction.Opcode) {
214 case TGSI_OPCODE_COS:
215 case TGSI_OPCODE_SIN:
216 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
217 case TGSI_OPCODE_DP2:
218 return 0x3;
219 case TGSI_OPCODE_DP3:
220 return 0x7;
221 case TGSI_OPCODE_DP4:
222 case TGSI_OPCODE_DPH:
223 case TGSI_OPCODE_KIL: /* WriteMask ignored */
224 return 0xf;
225 case TGSI_OPCODE_DST:
226 return mask & (s ? 0xa : 0x6);
227 case TGSI_OPCODE_EX2:
228 case TGSI_OPCODE_EXP:
229 case TGSI_OPCODE_LG2:
230 case TGSI_OPCODE_LOG:
231 case TGSI_OPCODE_POW:
232 case TGSI_OPCODE_RCP:
233 case TGSI_OPCODE_RSQ:
234 case TGSI_OPCODE_SCS:
235 return 0x1;
236 case TGSI_OPCODE_IF:
237 return 0x1;
238 case TGSI_OPCODE_LIT:
239 return 0xb;
240 case TGSI_OPCODE_TEX2:
241 case TGSI_OPCODE_TXB2:
242 case TGSI_OPCODE_TXL2:
243 return (s == 0) ? 0xf : 0x3;
244 case TGSI_OPCODE_TEX:
245 case TGSI_OPCODE_TXB:
246 case TGSI_OPCODE_TXD:
247 case TGSI_OPCODE_TXL:
248 case TGSI_OPCODE_TXP:
249 {
250 const struct tgsi_instruction_texture *tex = &insn->Texture;
251
252 assert(insn->Instruction.Texture);
253
254 mask = 0x7;
255 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
256 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
257 mask |= 0x8; /* bias, lod or proj */
258
259 switch (tex->Texture) {
260 case TGSI_TEXTURE_1D:
261 mask &= 0x9;
262 break;
263 case TGSI_TEXTURE_SHADOW1D:
264 mask &= 0xd;
265 break;
266 case TGSI_TEXTURE_1D_ARRAY:
267 case TGSI_TEXTURE_2D:
268 case TGSI_TEXTURE_RECT:
269 mask &= 0xb;
270 break;
271 case TGSI_TEXTURE_CUBE_ARRAY:
272 case TGSI_TEXTURE_SHADOW2D_ARRAY:
273 case TGSI_TEXTURE_SHADOWCUBE:
274 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
275 mask |= 0x8;
276 break;
277 default:
278 break;
279 }
280 }
281 return mask;
282 case TGSI_OPCODE_XPD:
283 {
284 unsigned int x = 0;
285 if (mask & 1) x |= 0x6;
286 if (mask & 2) x |= 0x5;
287 if (mask & 4) x |= 0x3;
288 return x;
289 }
290 default:
291 break;
292 }
293
294 return mask;
295 }
296
297 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
298 {
299 nv50_ir::Modifier m(0);
300
301 if (reg.Absolute)
302 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
303 if (reg.Negate)
304 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
305 return m;
306 }
307
308 static nv50_ir::DataFile translateFile(uint file)
309 {
310 switch (file) {
311 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
312 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
313 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
314 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
315 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
316 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
317 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
318 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
319 case TGSI_FILE_IMMEDIATE_ARRAY: return nv50_ir::FILE_IMMEDIATE;
320 case TGSI_FILE_TEMPORARY_ARRAY: return nv50_ir::FILE_MEMORY_LOCAL;
321 case TGSI_FILE_RESOURCE: return nv50_ir::FILE_MEMORY_GLOBAL;
322 case TGSI_FILE_SAMPLER:
323 case TGSI_FILE_NULL:
324 default:
325 return nv50_ir::FILE_NULL;
326 }
327 }
328
329 static nv50_ir::SVSemantic translateSysVal(uint sysval)
330 {
331 switch (sysval) {
332 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
333 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
334 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
335 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
336 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
337 default:
338 assert(0);
339 return nv50_ir::SV_CLOCK;
340 }
341 }
342
343 #define NV50_IR_TEX_TARG_CASE(a, b) \
344 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
345
346 static nv50_ir::TexTarget translateTexture(uint tex)
347 {
348 switch (tex) {
349 NV50_IR_TEX_TARG_CASE(1D, 1D);
350 NV50_IR_TEX_TARG_CASE(2D, 2D);
351 NV50_IR_TEX_TARG_CASE(3D, 3D);
352 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
353 NV50_IR_TEX_TARG_CASE(RECT, RECT);
354 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
355 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
356 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
357 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
358 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
359 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
360 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
361 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
362 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
363 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
364 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
365
366 case TGSI_TEXTURE_UNKNOWN:
367 default:
368 assert(!"invalid texture target");
369 return nv50_ir::TEX_TARGET_2D;
370 }
371 }
372
373 nv50_ir::DataType Instruction::inferSrcType() const
374 {
375 switch (getOpcode()) {
376 case TGSI_OPCODE_AND:
377 case TGSI_OPCODE_OR:
378 case TGSI_OPCODE_XOR:
379 case TGSI_OPCODE_NOT:
380 case TGSI_OPCODE_U2F:
381 case TGSI_OPCODE_UADD:
382 case TGSI_OPCODE_UDIV:
383 case TGSI_OPCODE_UMOD:
384 case TGSI_OPCODE_UMAD:
385 case TGSI_OPCODE_UMUL:
386 case TGSI_OPCODE_UMAX:
387 case TGSI_OPCODE_UMIN:
388 case TGSI_OPCODE_USEQ:
389 case TGSI_OPCODE_USGE:
390 case TGSI_OPCODE_USLT:
391 case TGSI_OPCODE_USNE:
392 case TGSI_OPCODE_USHR:
393 case TGSI_OPCODE_UCMP:
394 return nv50_ir::TYPE_U32;
395 case TGSI_OPCODE_I2F:
396 case TGSI_OPCODE_IDIV:
397 case TGSI_OPCODE_IMAX:
398 case TGSI_OPCODE_IMIN:
399 case TGSI_OPCODE_IABS:
400 case TGSI_OPCODE_INEG:
401 case TGSI_OPCODE_ISGE:
402 case TGSI_OPCODE_ISHR:
403 case TGSI_OPCODE_ISLT:
404 case TGSI_OPCODE_ISSG:
405 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
406 case TGSI_OPCODE_MOD:
407 case TGSI_OPCODE_UARL:
408 return nv50_ir::TYPE_S32;
409 default:
410 return nv50_ir::TYPE_F32;
411 }
412 }
413
414 nv50_ir::DataType Instruction::inferDstType() const
415 {
416 switch (getOpcode()) {
417 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
418 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
419 case TGSI_OPCODE_I2F:
420 case TGSI_OPCODE_U2F:
421 return nv50_ir::TYPE_F32;
422 default:
423 return inferSrcType();
424 }
425 }
426
427 nv50_ir::CondCode Instruction::getSetCond() const
428 {
429 using namespace nv50_ir;
430
431 switch (getOpcode()) {
432 case TGSI_OPCODE_SLT:
433 case TGSI_OPCODE_ISLT:
434 case TGSI_OPCODE_USLT:
435 return CC_LT;
436 case TGSI_OPCODE_SLE:
437 return CC_LE;
438 case TGSI_OPCODE_SGE:
439 case TGSI_OPCODE_ISGE:
440 case TGSI_OPCODE_USGE:
441 return CC_GE;
442 case TGSI_OPCODE_SGT:
443 return CC_GT;
444 case TGSI_OPCODE_SEQ:
445 case TGSI_OPCODE_USEQ:
446 return CC_EQ;
447 case TGSI_OPCODE_SNE:
448 return CC_NEU;
449 case TGSI_OPCODE_USNE:
450 return CC_NE;
451 case TGSI_OPCODE_SFL:
452 return CC_NEVER;
453 case TGSI_OPCODE_STR:
454 default:
455 return CC_ALWAYS;
456 }
457 }
458
459 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
460
461 static nv50_ir::operation translateOpcode(uint opcode)
462 {
463 switch (opcode) {
464 NV50_IR_OPCODE_CASE(ARL, SHL);
465 NV50_IR_OPCODE_CASE(MOV, MOV);
466
467 NV50_IR_OPCODE_CASE(RCP, RCP);
468 NV50_IR_OPCODE_CASE(RSQ, RSQ);
469
470 NV50_IR_OPCODE_CASE(MUL, MUL);
471 NV50_IR_OPCODE_CASE(ADD, ADD);
472
473 NV50_IR_OPCODE_CASE(MIN, MIN);
474 NV50_IR_OPCODE_CASE(MAX, MAX);
475 NV50_IR_OPCODE_CASE(SLT, SET);
476 NV50_IR_OPCODE_CASE(SGE, SET);
477 NV50_IR_OPCODE_CASE(MAD, MAD);
478 NV50_IR_OPCODE_CASE(SUB, SUB);
479
480 NV50_IR_OPCODE_CASE(FLR, FLOOR);
481 NV50_IR_OPCODE_CASE(ROUND, CVT);
482 NV50_IR_OPCODE_CASE(EX2, EX2);
483 NV50_IR_OPCODE_CASE(LG2, LG2);
484 NV50_IR_OPCODE_CASE(POW, POW);
485
486 NV50_IR_OPCODE_CASE(ABS, ABS);
487
488 NV50_IR_OPCODE_CASE(COS, COS);
489 NV50_IR_OPCODE_CASE(DDX, DFDX);
490 NV50_IR_OPCODE_CASE(DDY, DFDY);
491 NV50_IR_OPCODE_CASE(KILP, DISCARD);
492
493 NV50_IR_OPCODE_CASE(SEQ, SET);
494 NV50_IR_OPCODE_CASE(SFL, SET);
495 NV50_IR_OPCODE_CASE(SGT, SET);
496 NV50_IR_OPCODE_CASE(SIN, SIN);
497 NV50_IR_OPCODE_CASE(SLE, SET);
498 NV50_IR_OPCODE_CASE(SNE, SET);
499 NV50_IR_OPCODE_CASE(STR, SET);
500 NV50_IR_OPCODE_CASE(TEX, TEX);
501 NV50_IR_OPCODE_CASE(TXD, TXD);
502 NV50_IR_OPCODE_CASE(TXP, TEX);
503
504 NV50_IR_OPCODE_CASE(BRA, BRA);
505 NV50_IR_OPCODE_CASE(CAL, CALL);
506 NV50_IR_OPCODE_CASE(RET, RET);
507 NV50_IR_OPCODE_CASE(CMP, SLCT);
508
509 NV50_IR_OPCODE_CASE(TXB, TXB);
510
511 NV50_IR_OPCODE_CASE(DIV, DIV);
512
513 NV50_IR_OPCODE_CASE(TXL, TXL);
514
515 NV50_IR_OPCODE_CASE(CEIL, CEIL);
516 NV50_IR_OPCODE_CASE(I2F, CVT);
517 NV50_IR_OPCODE_CASE(NOT, NOT);
518 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
519 NV50_IR_OPCODE_CASE(SHL, SHL);
520
521 NV50_IR_OPCODE_CASE(AND, AND);
522 NV50_IR_OPCODE_CASE(OR, OR);
523 NV50_IR_OPCODE_CASE(MOD, MOD);
524 NV50_IR_OPCODE_CASE(XOR, XOR);
525 NV50_IR_OPCODE_CASE(SAD, SAD);
526 NV50_IR_OPCODE_CASE(TXF, TXF);
527 NV50_IR_OPCODE_CASE(TXQ, TXQ);
528
529 NV50_IR_OPCODE_CASE(EMIT, EMIT);
530 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
531
532 NV50_IR_OPCODE_CASE(KIL, DISCARD);
533
534 NV50_IR_OPCODE_CASE(F2I, CVT);
535 NV50_IR_OPCODE_CASE(IDIV, DIV);
536 NV50_IR_OPCODE_CASE(IMAX, MAX);
537 NV50_IR_OPCODE_CASE(IMIN, MIN);
538 NV50_IR_OPCODE_CASE(IABS, ABS);
539 NV50_IR_OPCODE_CASE(INEG, NEG);
540 NV50_IR_OPCODE_CASE(ISGE, SET);
541 NV50_IR_OPCODE_CASE(ISHR, SHR);
542 NV50_IR_OPCODE_CASE(ISLT, SET);
543 NV50_IR_OPCODE_CASE(F2U, CVT);
544 NV50_IR_OPCODE_CASE(U2F, CVT);
545 NV50_IR_OPCODE_CASE(UADD, ADD);
546 NV50_IR_OPCODE_CASE(UDIV, DIV);
547 NV50_IR_OPCODE_CASE(UMAD, MAD);
548 NV50_IR_OPCODE_CASE(UMAX, MAX);
549 NV50_IR_OPCODE_CASE(UMIN, MIN);
550 NV50_IR_OPCODE_CASE(UMOD, MOD);
551 NV50_IR_OPCODE_CASE(UMUL, MUL);
552 NV50_IR_OPCODE_CASE(USEQ, SET);
553 NV50_IR_OPCODE_CASE(USGE, SET);
554 NV50_IR_OPCODE_CASE(USHR, SHR);
555 NV50_IR_OPCODE_CASE(USLT, SET);
556 NV50_IR_OPCODE_CASE(USNE, SET);
557
558 NV50_IR_OPCODE_CASE(LOAD, TXF);
559 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
560 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
561 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
562 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
563 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
564 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
565 NV50_IR_OPCODE_CASE(GATHER4, TXG);
566 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
567
568 NV50_IR_OPCODE_CASE(TEX2, TEX);
569 NV50_IR_OPCODE_CASE(TXB2, TXB);
570 NV50_IR_OPCODE_CASE(TXL2, TXL);
571
572 NV50_IR_OPCODE_CASE(END, EXIT);
573
574 default:
575 return nv50_ir::OP_NOP;
576 }
577 }
578
579 bool Instruction::checkDstSrcAliasing() const
580 {
581 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
582 return false;
583
584 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
585 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
586 break;
587 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
588 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
589 return true;
590 }
591 return false;
592 }
593
594 class Source
595 {
596 public:
597 Source(struct nv50_ir_prog_info *);
598 ~Source();
599
600 public:
601 bool scanSource();
602 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
603
604 public:
605 struct tgsi_shader_info scan;
606 struct tgsi_full_instruction *insns;
607 const struct tgsi_token *tokens;
608 struct nv50_ir_prog_info *info;
609
610 nv50_ir::DynArray tempArrays;
611 nv50_ir::DynArray immdArrays;
612 int tempArrayCount;
613 int immdArrayCount;
614
615 bool mainTempsInLMem;
616
617 int clipVertexOutput;
618
619 uint8_t *samplerViewTargets; // TGSI_TEXTURE_*
620 unsigned samplerViewCount;
621
622 private:
623 int inferSysValDirection(unsigned sn) const;
624 bool scanDeclaration(const struct tgsi_full_declaration *);
625 bool scanInstruction(const struct tgsi_full_instruction *);
626 void scanProperty(const struct tgsi_full_property *);
627 void scanImmediate(const struct tgsi_full_immediate *);
628
629 inline bool isEdgeFlagPassthrough(const Instruction&) const;
630 };
631
632 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
633 {
634 tokens = (const struct tgsi_token *)info->bin.source;
635
636 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
637 tgsi_dump(tokens, 0);
638
639 samplerViewTargets = NULL;
640
641 mainTempsInLMem = FALSE;
642 }
643
644 Source::~Source()
645 {
646 if (insns)
647 FREE(insns);
648
649 if (info->immd.data)
650 FREE(info->immd.data);
651 if (info->immd.type)
652 FREE(info->immd.type);
653
654 if (samplerViewTargets)
655 delete[] samplerViewTargets;
656 }
657
658 bool Source::scanSource()
659 {
660 unsigned insnCount = 0;
661 struct tgsi_parse_context parse;
662
663 tgsi_scan_shader(tokens, &scan);
664
665 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
666 sizeof(insns[0]));
667 if (!insns)
668 return false;
669
670 clipVertexOutput = -1;
671
672 samplerViewCount = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
673 samplerViewTargets = new uint8_t[samplerViewCount];
674
675 info->immd.bufSize = 0;
676 tempArrayCount = 0;
677 immdArrayCount = 0;
678
679 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
680 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
681 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
682
683 if (info->type == PIPE_SHADER_FRAGMENT) {
684 info->prop.fp.writesDepth = scan.writes_z;
685 info->prop.fp.usesDiscard = scan.uses_kill;
686 } else
687 if (info->type == PIPE_SHADER_GEOMETRY) {
688 info->prop.gp.instanceCount = 1; // default value
689 }
690
691 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
692 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
693
694 tgsi_parse_init(&parse, tokens);
695 while (!tgsi_parse_end_of_tokens(&parse)) {
696 tgsi_parse_token(&parse);
697
698 switch (parse.FullToken.Token.Type) {
699 case TGSI_TOKEN_TYPE_IMMEDIATE:
700 scanImmediate(&parse.FullToken.FullImmediate);
701 break;
702 case TGSI_TOKEN_TYPE_DECLARATION:
703 scanDeclaration(&parse.FullToken.FullDeclaration);
704 break;
705 case TGSI_TOKEN_TYPE_INSTRUCTION:
706 insns[insnCount++] = parse.FullToken.FullInstruction;
707 scanInstruction(&parse.FullToken.FullInstruction);
708 break;
709 case TGSI_TOKEN_TYPE_PROPERTY:
710 scanProperty(&parse.FullToken.FullProperty);
711 break;
712 default:
713 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
714 break;
715 }
716 }
717 tgsi_parse_free(&parse);
718
719 if (mainTempsInLMem)
720 info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
721
722 if (info->io.genUserClip > 0) {
723 info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
724
725 for (unsigned int n = 0; n < ((info->io.genUserClip + 3) / 4); ++n) {
726 unsigned int i = info->numOutputs++;
727 info->out[i].id = i;
728 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
729 info->out[i].si = n;
730 info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
731 }
732 }
733
734 return info->assignSlots(info) == 0;
735 }
736
737 void Source::scanProperty(const struct tgsi_full_property *prop)
738 {
739 switch (prop->Property.PropertyName) {
740 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
741 info->prop.gp.outputPrim = prop->u[0].Data;
742 break;
743 case TGSI_PROPERTY_GS_INPUT_PRIM:
744 info->prop.gp.inputPrim = prop->u[0].Data;
745 break;
746 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
747 info->prop.gp.maxVertices = prop->u[0].Data;
748 break;
749 #if 0
750 case TGSI_PROPERTY_GS_INSTANCE_COUNT:
751 info->prop.gp.instanceCount = prop->u[0].Data;
752 break;
753 #endif
754 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
755 info->prop.fp.separateFragData = TRUE;
756 break;
757 case TGSI_PROPERTY_FS_COORD_ORIGIN:
758 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
759 // we don't care
760 break;
761 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
762 info->io.genUserClip = -1;
763 break;
764 default:
765 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
766 break;
767 }
768 }
769
770 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
771 {
772 const unsigned n = info->immd.count++;
773
774 assert(n < scan.immediate_count);
775
776 for (int c = 0; c < 4; ++c)
777 info->immd.data[n * 4 + c] = imm->u[c].Uint;
778
779 info->immd.type[n] = imm->Immediate.DataType;
780 }
781
782 int Source::inferSysValDirection(unsigned sn) const
783 {
784 switch (sn) {
785 case TGSI_SEMANTIC_INSTANCEID:
786 case TGSI_SEMANTIC_VERTEXID:
787 return 1;
788 #if 0
789 case TGSI_SEMANTIC_LAYER:
790 case TGSI_SEMANTIC_VIEWPORTINDEX:
791 return 0;
792 #endif
793 case TGSI_SEMANTIC_PRIMID:
794 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
795 default:
796 return 0;
797 }
798 }
799
800 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
801 {
802 unsigned i;
803 unsigned sn = TGSI_SEMANTIC_GENERIC;
804 unsigned si = 0;
805 const unsigned first = decl->Range.First, last = decl->Range.Last;
806
807 if (decl->Declaration.Semantic) {
808 sn = decl->Semantic.Name;
809 si = decl->Semantic.Index;
810 }
811
812 switch (decl->Declaration.File) {
813 case TGSI_FILE_INPUT:
814 if (info->type == PIPE_SHADER_VERTEX) {
815 // all vertex attributes are equal
816 for (i = first; i <= last; ++i) {
817 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
818 info->in[i].si = i;
819 }
820 } else {
821 for (i = first; i <= last; ++i, ++si) {
822 info->in[i].id = i;
823 info->in[i].sn = sn;
824 info->in[i].si = si;
825 if (info->type == PIPE_SHADER_FRAGMENT) {
826 // translate interpolation mode
827 switch (decl->Interp.Interpolate) {
828 case TGSI_INTERPOLATE_CONSTANT:
829 info->in[i].flat = 1;
830 break;
831 case TGSI_INTERPOLATE_COLOR:
832 info->in[i].sc = 1;
833 break;
834 case TGSI_INTERPOLATE_LINEAR:
835 info->in[i].linear = 1;
836 break;
837 default:
838 break;
839 }
840 if (decl->Interp.Centroid)
841 info->in[i].centroid = 1;
842 }
843 }
844 }
845 break;
846 case TGSI_FILE_OUTPUT:
847 for (i = first; i <= last; ++i, ++si) {
848 switch (sn) {
849 case TGSI_SEMANTIC_POSITION:
850 if (info->type == PIPE_SHADER_FRAGMENT)
851 info->io.fragDepth = i;
852 else
853 if (clipVertexOutput < 0)
854 clipVertexOutput = i;
855 break;
856 case TGSI_SEMANTIC_COLOR:
857 if (info->type == PIPE_SHADER_FRAGMENT)
858 info->prop.fp.numColourResults++;
859 break;
860 case TGSI_SEMANTIC_EDGEFLAG:
861 info->io.edgeFlagOut = i;
862 break;
863 case TGSI_SEMANTIC_CLIPVERTEX:
864 clipVertexOutput = i;
865 break;
866 case TGSI_SEMANTIC_CLIPDIST:
867 info->io.clipDistanceMask |=
868 decl->Declaration.UsageMask << (si * 4);
869 info->io.genUserClip = -1;
870 break;
871 default:
872 break;
873 }
874 info->out[i].id = i;
875 info->out[i].sn = sn;
876 info->out[i].si = si;
877 }
878 break;
879 case TGSI_FILE_SYSTEM_VALUE:
880 switch (sn) {
881 case TGSI_SEMANTIC_INSTANCEID:
882 info->io.instanceId = first;
883 break;
884 case TGSI_SEMANTIC_VERTEXID:
885 info->io.vertexId = first;
886 break;
887 default:
888 break;
889 }
890 for (i = first; i <= last; ++i, ++si) {
891 info->sv[i].sn = sn;
892 info->sv[i].si = si;
893 info->sv[i].input = inferSysValDirection(sn);
894 }
895 break;
896 case TGSI_FILE_SAMPLER_VIEW:
897 for (i = first; i <= last; ++i)
898 samplerViewTargets[i] = decl->SamplerView.Resource;
899 break;
900 case TGSI_FILE_IMMEDIATE_ARRAY:
901 {
902 if (decl->Dim.Index2D >= immdArrayCount)
903 immdArrayCount = decl->Dim.Index2D + 1;
904 immdArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
905 int c;
906 uint32_t base, count;
907 switch (decl->Declaration.UsageMask) {
908 case 0x1: c = 1; break;
909 case 0x3: c = 2; break;
910 default:
911 c = 4;
912 break;
913 }
914 immdArrays[decl->Dim.Index2D].u32 |= c;
915 count = (last + 1) * c;
916 base = info->immd.bufSize / 4;
917 info->immd.bufSize = (info->immd.bufSize + count * 4 + 0xf) & ~0xf;
918 info->immd.buf = (uint32_t *)REALLOC(info->immd.buf, base * 4,
919 info->immd.bufSize);
920 // NOTE: this assumes array declarations are ordered by Dim.Index2D
921 for (i = 0; i < count; ++i)
922 info->immd.buf[base + i] = decl->ImmediateData.u[i].Uint;
923 }
924 break;
925 case TGSI_FILE_TEMPORARY_ARRAY:
926 {
927 if (decl->Dim.Index2D >= tempArrayCount)
928 tempArrayCount = decl->Dim.Index2D + 1;
929 tempArrays[decl->Dim.Index2D].u32 = (last + 1) << 2;
930 int c;
931 uint32_t count;
932 switch (decl->Declaration.UsageMask) {
933 case 0x1: c = 1; break;
934 case 0x3: c = 2; break;
935 default:
936 c = 4;
937 break;
938 }
939 tempArrays[decl->Dim.Index2D].u32 |= c;
940 count = (last + 1) * c;
941 info->bin.tlsSpace += (info->bin.tlsSpace + count * 4 + 0xf) & ~0xf;
942 }
943 break;
944 case TGSI_FILE_NULL:
945 case TGSI_FILE_TEMPORARY:
946 case TGSI_FILE_ADDRESS:
947 case TGSI_FILE_CONSTANT:
948 case TGSI_FILE_IMMEDIATE:
949 case TGSI_FILE_PREDICATE:
950 case TGSI_FILE_SAMPLER:
951 break;
952 default:
953 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
954 return false;
955 }
956 return true;
957 }
958
959 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
960 {
961 return insn.getOpcode() == TGSI_OPCODE_MOV &&
962 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
963 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
964 }
965
966 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
967 {
968 Instruction insn(inst);
969
970 if (insn.dstCount()) {
971 if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
972 Instruction::DstRegister dst = insn.getDst(0);
973
974 if (dst.isIndirect(0))
975 for (unsigned i = 0; i < info->numOutputs; ++i)
976 info->out[i].mask = 0xf;
977 else
978 info->out[dst.getIndex(0)].mask |= dst.getMask();
979
980 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE)
981 info->out[dst.getIndex(0)].mask &= 1;
982
983 if (isEdgeFlagPassthrough(insn))
984 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
985 } else
986 if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
987 if (insn.getDst(0).isIndirect(0))
988 mainTempsInLMem = TRUE;
989 }
990 }
991
992 for (unsigned s = 0; s < insn.srcCount(); ++s) {
993 Instruction::SrcRegister src = insn.getSrc(s);
994 if (src.getFile() == TGSI_FILE_TEMPORARY)
995 if (src.isIndirect(0))
996 mainTempsInLMem = TRUE;
997 if (src.getFile() != TGSI_FILE_INPUT)
998 continue;
999 unsigned mask = insn.srcMask(s);
1000
1001 if (src.isIndirect(0)) {
1002 for (unsigned i = 0; i < info->numInputs; ++i)
1003 info->in[i].mask = 0xf;
1004 } else {
1005 for (unsigned c = 0; c < 4; ++c) {
1006 if (!(mask & (1 << c)))
1007 continue;
1008 int k = src.getSwizzle(c);
1009 int i = src.getIndex(0);
1010 if (info->in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
1011 if (k <= TGSI_SWIZZLE_W)
1012 info->in[i].mask |= 1 << k;
1013 }
1014 }
1015 }
1016 return true;
1017 }
1018
1019 nv50_ir::TexInstruction::Target
1020 Instruction::getTexture(const tgsi::Source *code, int s) const
1021 {
1022 switch (getSrc(s).getFile()) {
1023 case TGSI_FILE_SAMPLER_VIEW: {
1024 // XXX: indirect access
1025 unsigned int r = getSrc(s).getIndex(0);
1026 assert(r < code->samplerViewCount);
1027 return translateTexture(code->samplerViewTargets[r]);
1028 }
1029 default:
1030 return translateTexture(insn->Texture.Texture);
1031 }
1032 }
1033
1034 } // namespace tgsi
1035
1036 namespace {
1037
1038 using namespace nv50_ir;
1039
1040 class Converter : public BuildUtil
1041 {
1042 public:
1043 Converter(Program *, const tgsi::Source *);
1044 ~Converter();
1045
1046 bool run();
1047
1048 private:
1049 struct Subroutine
1050 {
1051 Subroutine(Function *f) : f(f) { }
1052 Function *f;
1053 ValueMap values;
1054 };
1055
1056 Value *getVertexBase(int s);
1057 DataArray *getArrayForFile(unsigned file, int idx);
1058 Value *fetchSrc(int s, int c);
1059 Value *acquireDst(int d, int c);
1060 void storeDst(int d, int c, Value *);
1061
1062 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1063 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1064 Value *val, Value *ptr);
1065
1066 Value *applySrcMod(Value *, int s, int c);
1067
1068 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1069 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1070 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1071
1072 bool handleInstruction(const struct tgsi_full_instruction *);
1073 void exportOutputs();
1074 inline Subroutine *getSubroutine(unsigned ip);
1075 inline Subroutine *getSubroutine(Function *);
1076 inline bool isEndOfSubroutine(uint ip);
1077
1078 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1079
1080 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1081 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1082 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1083 void handleTXF(Value *dst0[4], int R);
1084 void handleTXQ(Value *dst0[4], enum TexQuery);
1085 void handleLIT(Value *dst0[4]);
1086 void handleUserClipPlanes();
1087
1088 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1089
1090 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1091
1092 Value *buildDot(int dim);
1093
1094 class BindArgumentsPass : public Pass {
1095 public:
1096 BindArgumentsPass(Converter &conv) : conv(conv) { }
1097
1098 private:
1099 Converter &conv;
1100 Subroutine *sub;
1101
1102 template<typename T> inline void
1103 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1104 T (Function::*proto));
1105
1106 template<typename T> inline void
1107 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1108 T (Function::*proto));
1109
1110 protected:
1111 bool visit(Function *);
1112 bool visit(BasicBlock *bb) { return false; }
1113 };
1114
1115 private:
1116 const struct tgsi::Source *code;
1117 const struct nv50_ir_prog_info *info;
1118
1119 struct {
1120 std::map<unsigned, Subroutine> map;
1121 Subroutine *cur;
1122 } sub;
1123
1124 uint ip; // instruction pointer
1125
1126 tgsi::Instruction tgsi;
1127
1128 DataType dstTy;
1129 DataType srcTy;
1130
1131 DataArray tData; // TGSI_FILE_TEMPORARY
1132 DataArray aData; // TGSI_FILE_ADDRESS
1133 DataArray pData; // TGSI_FILE_PREDICATE
1134 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1135 std::vector<DataArray> lData; // TGSI_FILE_TEMPORARY_ARRAY
1136 std::vector<DataArray> iData; // TGSI_FILE_IMMEDIATE_ARRAY
1137
1138 Value *zero;
1139 Value *fragCoord[4];
1140 Value *clipVtx[4];
1141
1142 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1143 uint8_t vtxBaseValid;
1144
1145 Stack condBBs; // fork BB, then else clause BB
1146 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1147 Stack loopBBs; // loop headers
1148 Stack breakBBs; // end of / after loop
1149 };
1150
1151 Symbol *
1152 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1153 {
1154 const int swz = src.getSwizzle(c);
1155
1156 return makeSym(src.getFile(),
1157 src.is2D() ? src.getIndex(1) : 0,
1158 src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1159 src.getIndex(0) * 16 + swz * 4);
1160 }
1161
1162 Symbol *
1163 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1164 {
1165 return makeSym(dst.getFile(),
1166 dst.is2D() ? dst.getIndex(1) : 0,
1167 dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1168 dst.getIndex(0) * 16 + c * 4);
1169 }
1170
1171 Symbol *
1172 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1173 {
1174 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1175
1176 sym->reg.fileIndex = fileIdx;
1177
1178 if (idx >= 0) {
1179 if (sym->reg.file == FILE_SHADER_INPUT)
1180 sym->setOffset(info->in[idx].slot[c] * 4);
1181 else
1182 if (sym->reg.file == FILE_SHADER_OUTPUT)
1183 sym->setOffset(info->out[idx].slot[c] * 4);
1184 else
1185 if (sym->reg.file == FILE_SYSTEM_VALUE)
1186 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1187 else
1188 sym->setOffset(address);
1189 } else {
1190 sym->setOffset(address);
1191 }
1192 return sym;
1193 }
1194
1195 static inline uint8_t
1196 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1197 {
1198 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1199
1200 if (var->flat)
1201 mode = NV50_IR_INTERP_FLAT;
1202 else
1203 if (var->linear)
1204 mode = NV50_IR_INTERP_LINEAR;
1205 else
1206 if (var->sc)
1207 mode = NV50_IR_INTERP_SC;
1208
1209 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1210 ? OP_PINTERP : OP_LINTERP;
1211
1212 if (var->centroid)
1213 mode |= NV50_IR_INTERP_CENTROID;
1214
1215 return mode;
1216 }
1217
1218 Value *
1219 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1220 {
1221 operation op;
1222
1223 // XXX: no way to know interpolation mode if we don't know what's accessed
1224 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1225 src.getIndex(0)], op);
1226
1227 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1228
1229 insn->setDef(0, getScratch());
1230 insn->setSrc(0, srcToSym(src, c));
1231 if (op == OP_PINTERP)
1232 insn->setSrc(1, fragCoord[3]);
1233 if (ptr)
1234 insn->setIndirect(0, 0, ptr);
1235
1236 insn->setInterpolate(mode);
1237
1238 bb->insertTail(insn);
1239 return insn->getDef(0);
1240 }
1241
1242 Value *
1243 Converter::applySrcMod(Value *val, int s, int c)
1244 {
1245 Modifier m = tgsi.getSrc(s).getMod(c);
1246 DataType ty = tgsi.inferSrcType();
1247
1248 if (m & Modifier(NV50_IR_MOD_ABS))
1249 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1250
1251 if (m & Modifier(NV50_IR_MOD_NEG))
1252 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1253
1254 return val;
1255 }
1256
1257 Value *
1258 Converter::getVertexBase(int s)
1259 {
1260 assert(s < 5);
1261 if (!(vtxBaseValid & (1 << s))) {
1262 const int index = tgsi.getSrc(s).getIndex(1);
1263 Value *rel = NULL;
1264 if (tgsi.getSrc(s).isIndirect(1))
1265 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1266 vtxBaseValid |= 1 << s;
1267 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(), mkImm(index), rel);
1268 }
1269 return vtxBase[s];
1270 }
1271
1272 Value *
1273 Converter::fetchSrc(int s, int c)
1274 {
1275 Value *res;
1276 Value *ptr = NULL, *dimRel = NULL;
1277
1278 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1279
1280 if (src.isIndirect(0))
1281 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1282
1283 if (src.is2D()) {
1284 switch (src.getFile()) {
1285 case TGSI_FILE_INPUT:
1286 dimRel = getVertexBase(s);
1287 break;
1288 case TGSI_FILE_CONSTANT:
1289 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1290 if (src.isIndirect(1))
1291 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1292 break;
1293 default:
1294 break;
1295 }
1296 }
1297
1298 res = fetchSrc(src, c, ptr);
1299
1300 if (dimRel)
1301 res->getInsn()->setIndirect(0, 1, dimRel);
1302
1303 return applySrcMod(res, s, c);
1304 }
1305
1306 Converter::DataArray *
1307 Converter::getArrayForFile(unsigned file, int idx)
1308 {
1309 switch (file) {
1310 case TGSI_FILE_TEMPORARY:
1311 return &tData;
1312 case TGSI_FILE_PREDICATE:
1313 return &pData;
1314 case TGSI_FILE_ADDRESS:
1315 return &aData;
1316 case TGSI_FILE_TEMPORARY_ARRAY:
1317 assert(idx < code->tempArrayCount);
1318 return &lData[idx];
1319 case TGSI_FILE_IMMEDIATE_ARRAY:
1320 assert(idx < code->immdArrayCount);
1321 return &iData[idx];
1322 case TGSI_FILE_OUTPUT:
1323 assert(prog->getType() == Program::TYPE_FRAGMENT);
1324 return &oData;
1325 default:
1326 assert(!"invalid/unhandled TGSI source file");
1327 return NULL;
1328 }
1329 }
1330
1331 Value *
1332 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1333 {
1334 const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1335 const int idx = src.getIndex(0);
1336 const int swz = src.getSwizzle(c);
1337
1338 switch (src.getFile()) {
1339 case TGSI_FILE_IMMEDIATE:
1340 assert(!ptr);
1341 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1342 case TGSI_FILE_CONSTANT:
1343 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1344 case TGSI_FILE_INPUT:
1345 if (prog->getType() == Program::TYPE_FRAGMENT) {
1346 // don't load masked inputs, won't be assigned a slot
1347 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1348 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1349 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1350 return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1351 return interpolate(src, c, ptr);
1352 }
1353 return mkLoad(TYPE_U32, srcToSym(src, c), ptr);
1354 case TGSI_FILE_OUTPUT:
1355 assert(!"load from output file");
1356 return NULL;
1357 case TGSI_FILE_SYSTEM_VALUE:
1358 assert(!ptr);
1359 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1360 default:
1361 return getArrayForFile(src.getFile(), idx2d)->load(
1362 sub.cur->values, idx, swz, ptr);
1363 }
1364 }
1365
1366 Value *
1367 Converter::acquireDst(int d, int c)
1368 {
1369 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1370 const unsigned f = dst.getFile();
1371 const int idx = dst.getIndex(0);
1372 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1373
1374 if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1375 return NULL;
1376
1377 if (dst.isIndirect(0) ||
1378 f == TGSI_FILE_TEMPORARY_ARRAY ||
1379 f == TGSI_FILE_SYSTEM_VALUE ||
1380 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1381 return getScratch();
1382
1383 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1384 }
1385
1386 void
1387 Converter::storeDst(int d, int c, Value *val)
1388 {
1389 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1390
1391 switch (tgsi.getSaturate()) {
1392 case TGSI_SAT_NONE:
1393 break;
1394 case TGSI_SAT_ZERO_ONE:
1395 mkOp1(OP_SAT, dstTy, val, val);
1396 break;
1397 case TGSI_SAT_MINUS_PLUS_ONE:
1398 mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1399 mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1400 break;
1401 default:
1402 assert(!"invalid saturation mode");
1403 break;
1404 }
1405
1406 Value *ptr = dst.isIndirect(0) ?
1407 fetchSrc(dst.getIndirect(0), 0, NULL) : NULL;
1408
1409 if (info->io.genUserClip > 0 &&
1410 dst.getFile() == TGSI_FILE_OUTPUT &&
1411 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1412 mkMov(clipVtx[c], val);
1413 val = clipVtx[c];
1414 }
1415
1416 storeDst(dst, c, val, ptr);
1417 }
1418
1419 void
1420 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1421 Value *val, Value *ptr)
1422 {
1423 const unsigned f = dst.getFile();
1424 const int idx = dst.getIndex(0);
1425 const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1426
1427 if (f == TGSI_FILE_SYSTEM_VALUE) {
1428 assert(!ptr);
1429 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1430 } else
1431 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1432 if (ptr || (info->out[idx].mask & (1 << c)))
1433 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1434 } else
1435 if (f == TGSI_FILE_TEMPORARY ||
1436 f == TGSI_FILE_TEMPORARY_ARRAY ||
1437 f == TGSI_FILE_PREDICATE ||
1438 f == TGSI_FILE_ADDRESS ||
1439 f == TGSI_FILE_OUTPUT) {
1440 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1441 } else {
1442 assert(!"invalid dst file");
1443 }
1444 }
1445
1446 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1447 for (chan = 0; chan < 4; ++chan) \
1448 if (!inst.getDst(d).isMasked(chan))
1449
1450 Value *
1451 Converter::buildDot(int dim)
1452 {
1453 assert(dim > 0);
1454
1455 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1456 Value *dotp = getScratch();
1457
1458 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1459
1460 for (int c = 1; c < dim; ++c) {
1461 src0 = fetchSrc(0, c);
1462 src1 = fetchSrc(1, c);
1463 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1464 }
1465 return dotp;
1466 }
1467
1468 void
1469 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1470 {
1471 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1472 join->fixed = 1;
1473 conv->insertHead(join);
1474
1475 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1476 fork->insertBefore(fork->getExit(), fork->joinAt);
1477 }
1478
1479 void
1480 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1481 {
1482 unsigned rIdx = 0, sIdx = 0;
1483
1484 if (R >= 0)
1485 rIdx = tgsi.getSrc(R).getIndex(0);
1486 if (S >= 0)
1487 sIdx = tgsi.getSrc(S).getIndex(0);
1488
1489 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1490
1491 if (tgsi.getSrc(R).isIndirect(0)) {
1492 tex->tex.rIndirectSrc = s;
1493 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1494 }
1495 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1496 tex->tex.sIndirectSrc = s;
1497 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1498 }
1499 }
1500
1501 void
1502 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1503 {
1504 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1505 tex->tex.query = query;
1506 unsigned int c, d;
1507
1508 for (d = 0, c = 0; c < 4; ++c) {
1509 if (!dst0[c])
1510 continue;
1511 tex->tex.mask |= 1 << c;
1512 tex->setDef(d++, dst0[c]);
1513 }
1514 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1515
1516 setTexRS(tex, c, 1, -1);
1517
1518 bb->insertTail(tex);
1519 }
1520
1521 void
1522 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1523 {
1524 Value *proj = fetchSrc(0, 3);
1525 Instruction *insn = proj->getUniqueInsn();
1526 int c;
1527
1528 if (insn->op == OP_PINTERP) {
1529 bb->insertTail(insn = cloneForward(func, insn));
1530 insn->op = OP_LINTERP;
1531 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1532 insn->setSrc(1, NULL);
1533 proj = insn->getDef(0);
1534 }
1535 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1536
1537 for (c = 0; c < 4; ++c) {
1538 if (!(mask & (1 << c)))
1539 continue;
1540 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1541 continue;
1542 mask &= ~(1 << c);
1543
1544 bb->insertTail(insn = cloneForward(func, insn));
1545 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1546 insn->setSrc(1, proj);
1547 dst[c] = insn->getDef(0);
1548 }
1549 if (!mask)
1550 return;
1551
1552 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1553
1554 for (c = 0; c < 4; ++c)
1555 if (mask & (1 << c))
1556 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1557 }
1558
1559 // order of nv50 ir sources: x y z layer lod/bias shadow
1560 // order of TGSI TEX sources: x y z layer shadow lod/bias
1561 // lowering will finally set the hw specific order (like array first on nvc0)
1562 void
1563 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1564 {
1565 Value *val;
1566 Value *arg[4], *src[8];
1567 Value *lod = NULL, *shd = NULL;
1568 unsigned int s, c, d;
1569 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1570
1571 TexInstruction::Target tgt = tgsi.getTexture(code, R);
1572
1573 for (s = 0; s < tgt.getArgCount(); ++s)
1574 arg[s] = src[s] = fetchSrc(0, s);
1575
1576 if (texi->op == OP_TXL || texi->op == OP_TXB)
1577 lod = fetchSrc(L >> 4, L & 3);
1578
1579 if (C == 0x0f)
1580 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1581
1582 if (tgt.isShadow())
1583 shd = fetchSrc(C >> 4, C & 3);
1584
1585 if (texi->op == OP_TXD) {
1586 for (c = 0; c < tgt.getDim(); ++c) {
1587 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1588 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1589 }
1590 }
1591
1592 // cube textures don't care about projection value, it's divided out
1593 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1594 unsigned int n = tgt.getDim();
1595 if (shd) {
1596 arg[n] = shd;
1597 ++n;
1598 assert(tgt.getDim() == tgt.getArgCount());
1599 }
1600 loadProjTexCoords(src, arg, (1 << n) - 1);
1601 if (shd)
1602 shd = src[n - 1];
1603 }
1604
1605 if (tgt.isCube()) {
1606 for (c = 0; c < 3; ++c)
1607 src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1608 val = getScratch();
1609 mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1610 mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1611 mkOp1(OP_RCP, TYPE_F32, val, val);
1612 for (c = 0; c < 3; ++c)
1613 src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1614 }
1615
1616 for (c = 0, d = 0; c < 4; ++c) {
1617 if (dst[c]) {
1618 texi->setDef(d++, dst[c]);
1619 texi->tex.mask |= 1 << c;
1620 } else {
1621 // NOTE: maybe hook up def too, for CSE
1622 }
1623 }
1624 for (s = 0; s < tgt.getArgCount(); ++s)
1625 texi->setSrc(s, src[s]);
1626 if (lod)
1627 texi->setSrc(s++, lod);
1628 if (shd)
1629 texi->setSrc(s++, shd);
1630
1631 setTexRS(texi, s, R, S);
1632
1633 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1634 texi->tex.levelZero = true;
1635
1636 bb->insertTail(texi);
1637 }
1638
1639 // 1st source: xyz = coordinates, w = lod
1640 // 2nd source: offset
1641 void
1642 Converter::handleTXF(Value *dst[4], int R)
1643 {
1644 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1645 unsigned int c, d, s;
1646
1647 texi->tex.target = tgsi.getTexture(code, R);
1648
1649 for (c = 0, d = 0; c < 4; ++c) {
1650 if (dst[c]) {
1651 texi->setDef(d++, dst[c]);
1652 texi->tex.mask |= 1 << c;
1653 }
1654 }
1655 for (c = 0; c < texi->tex.target.getArgCount(); ++c)
1656 texi->setSrc(c, fetchSrc(0, c));
1657 texi->setSrc(c++, fetchSrc(0, 3)); // lod
1658
1659 setTexRS(texi, c, R, -1);
1660
1661 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1662 for (c = 0; c < 3; ++c) {
1663 texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
1664 if (texi->tex.offset[s][c])
1665 texi->tex.useOffsets = s + 1;
1666 }
1667 }
1668
1669 bb->insertTail(texi);
1670 }
1671
1672 void
1673 Converter::handleLIT(Value *dst0[4])
1674 {
1675 Value *val0 = NULL;
1676 unsigned int mask = tgsi.getDst(0).getMask();
1677
1678 if (mask & (1 << 0))
1679 loadImm(dst0[0], 1.0f);
1680
1681 if (mask & (1 << 3))
1682 loadImm(dst0[3], 1.0f);
1683
1684 if (mask & (3 << 1)) {
1685 val0 = getScratch();
1686 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1687 if (mask & (1 << 1))
1688 mkMov(dst0[1], val0);
1689 }
1690
1691 if (mask & (1 << 2)) {
1692 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1693 Value *val1 = getScratch(), *val3 = getScratch();
1694
1695 Value *pos128 = loadImm(NULL, +127.999999f);
1696 Value *neg128 = loadImm(NULL, -127.999999f);
1697
1698 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1699 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1700 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1701 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1702
1703 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], val3, zero, val0);
1704 }
1705 }
1706
1707 Converter::Subroutine *
1708 Converter::getSubroutine(unsigned ip)
1709 {
1710 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
1711
1712 if (it == sub.map.end())
1713 it = sub.map.insert(std::make_pair(
1714 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
1715
1716 return &it->second;
1717 }
1718
1719 Converter::Subroutine *
1720 Converter::getSubroutine(Function *f)
1721 {
1722 unsigned ip = f->getLabel();
1723 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
1724
1725 if (it == sub.map.end())
1726 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
1727
1728 return &it->second;
1729 }
1730
1731 bool
1732 Converter::isEndOfSubroutine(uint ip)
1733 {
1734 assert(ip < code->scan.num_instructions);
1735 tgsi::Instruction insn(&code->insns[ip]);
1736 return (insn.getOpcode() == TGSI_OPCODE_END ||
1737 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
1738 // does END occur at end of main or the very end ?
1739 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
1740 }
1741
1742 bool
1743 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
1744 {
1745 Value *dst0[4], *rDst0[4];
1746 Value *src0, *src1, *src2;
1747 Value *val0, *val1;
1748 int c;
1749
1750 tgsi = tgsi::Instruction(insn);
1751
1752 bool useScratchDst = tgsi.checkDstSrcAliasing();
1753
1754 operation op = tgsi.getOP();
1755 dstTy = tgsi.inferDstType();
1756 srcTy = tgsi.inferSrcType();
1757
1758 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
1759
1760 if (tgsi.dstCount()) {
1761 for (c = 0; c < 4; ++c) {
1762 rDst0[c] = acquireDst(0, c);
1763 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
1764 }
1765 }
1766
1767 switch (tgsi.getOpcode()) {
1768 case TGSI_OPCODE_ADD:
1769 case TGSI_OPCODE_UADD:
1770 case TGSI_OPCODE_AND:
1771 case TGSI_OPCODE_DIV:
1772 case TGSI_OPCODE_IDIV:
1773 case TGSI_OPCODE_UDIV:
1774 case TGSI_OPCODE_MAX:
1775 case TGSI_OPCODE_MIN:
1776 case TGSI_OPCODE_IMAX:
1777 case TGSI_OPCODE_IMIN:
1778 case TGSI_OPCODE_UMAX:
1779 case TGSI_OPCODE_UMIN:
1780 case TGSI_OPCODE_MOD:
1781 case TGSI_OPCODE_UMOD:
1782 case TGSI_OPCODE_MUL:
1783 case TGSI_OPCODE_UMUL:
1784 case TGSI_OPCODE_OR:
1785 case TGSI_OPCODE_POW:
1786 case TGSI_OPCODE_SHL:
1787 case TGSI_OPCODE_ISHR:
1788 case TGSI_OPCODE_USHR:
1789 case TGSI_OPCODE_SUB:
1790 case TGSI_OPCODE_XOR:
1791 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1792 src0 = fetchSrc(0, c);
1793 src1 = fetchSrc(1, c);
1794 mkOp2(op, dstTy, dst0[c], src0, src1);
1795 }
1796 break;
1797 case TGSI_OPCODE_MAD:
1798 case TGSI_OPCODE_UMAD:
1799 case TGSI_OPCODE_SAD:
1800 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1801 src0 = fetchSrc(0, c);
1802 src1 = fetchSrc(1, c);
1803 src2 = fetchSrc(2, c);
1804 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
1805 }
1806 break;
1807 case TGSI_OPCODE_MOV:
1808 case TGSI_OPCODE_ABS:
1809 case TGSI_OPCODE_CEIL:
1810 case TGSI_OPCODE_FLR:
1811 case TGSI_OPCODE_TRUNC:
1812 case TGSI_OPCODE_RCP:
1813 case TGSI_OPCODE_IABS:
1814 case TGSI_OPCODE_INEG:
1815 case TGSI_OPCODE_NOT:
1816 case TGSI_OPCODE_DDX:
1817 case TGSI_OPCODE_DDY:
1818 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1819 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
1820 break;
1821 case TGSI_OPCODE_RSQ:
1822 src0 = fetchSrc(0, 0);
1823 val0 = getScratch();
1824 mkOp1(OP_ABS, TYPE_F32, val0, src0);
1825 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
1826 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1827 mkMov(dst0[c], val0);
1828 break;
1829 case TGSI_OPCODE_ARL:
1830 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1831 src0 = fetchSrc(0, c);
1832 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = ROUND_M;
1833 mkOp2(OP_SHL, TYPE_U32, dst0[c], dst0[c], mkImm(4));
1834 }
1835 break;
1836 case TGSI_OPCODE_UARL:
1837 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1838 mkOp2(OP_SHL, TYPE_U32, dst0[c], fetchSrc(0, c), mkImm(4));
1839 break;
1840 case TGSI_OPCODE_EX2:
1841 case TGSI_OPCODE_LG2:
1842 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
1843 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1844 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
1845 break;
1846 case TGSI_OPCODE_COS:
1847 case TGSI_OPCODE_SIN:
1848 val0 = getScratch();
1849 if (mask & 7) {
1850 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
1851 mkOp1(op, TYPE_F32, val0, val0);
1852 for (c = 0; c < 3; ++c)
1853 if (dst0[c])
1854 mkMov(dst0[c], val0);
1855 }
1856 if (dst0[3]) {
1857 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
1858 mkOp1(op, TYPE_F32, dst0[3], val0);
1859 }
1860 break;
1861 case TGSI_OPCODE_SCS:
1862 if (mask & 3) {
1863 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
1864 if (dst0[0])
1865 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
1866 if (dst0[1])
1867 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
1868 }
1869 if (dst0[2])
1870 loadImm(dst0[2], 0.0f);
1871 if (dst0[3])
1872 loadImm(dst0[3], 1.0f);
1873 break;
1874 case TGSI_OPCODE_EXP:
1875 src0 = fetchSrc(0, 0);
1876 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
1877 if (dst0[1])
1878 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
1879 if (dst0[0])
1880 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
1881 if (dst0[2])
1882 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
1883 if (dst0[3])
1884 loadImm(dst0[3], 1.0f);
1885 break;
1886 case TGSI_OPCODE_LOG:
1887 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
1888 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
1889 if (dst0[0] || dst0[1])
1890 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
1891 if (dst0[1]) {
1892 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
1893 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
1894 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
1895 }
1896 if (dst0[3])
1897 loadImm(dst0[3], 1.0f);
1898 break;
1899 case TGSI_OPCODE_DP2:
1900 val0 = buildDot(2);
1901 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1902 mkMov(dst0[c], val0);
1903 break;
1904 case TGSI_OPCODE_DP3:
1905 val0 = buildDot(3);
1906 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1907 mkMov(dst0[c], val0);
1908 break;
1909 case TGSI_OPCODE_DP4:
1910 val0 = buildDot(4);
1911 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1912 mkMov(dst0[c], val0);
1913 break;
1914 case TGSI_OPCODE_DPH:
1915 val0 = buildDot(3);
1916 src1 = fetchSrc(1, 3);
1917 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
1918 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
1919 mkMov(dst0[c], val0);
1920 break;
1921 case TGSI_OPCODE_DST:
1922 if (dst0[0])
1923 loadImm(dst0[0], 1.0f);
1924 if (dst0[1]) {
1925 src0 = fetchSrc(0, 1);
1926 src1 = fetchSrc(1, 1);
1927 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
1928 }
1929 if (dst0[2])
1930 mkMov(dst0[2], fetchSrc(0, 2));
1931 if (dst0[3])
1932 mkMov(dst0[3], fetchSrc(1, 3));
1933 break;
1934 case TGSI_OPCODE_LRP:
1935 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1936 src0 = fetchSrc(0, c);
1937 src1 = fetchSrc(1, c);
1938 src2 = fetchSrc(2, c);
1939 mkOp3(OP_MAD, TYPE_F32, dst0[c],
1940 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
1941 }
1942 break;
1943 case TGSI_OPCODE_LIT:
1944 handleLIT(dst0);
1945 break;
1946 case TGSI_OPCODE_XPD:
1947 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1948 if (c < 3) {
1949 val0 = getSSA();
1950 src0 = fetchSrc(1, (c + 1) % 3);
1951 src1 = fetchSrc(0, (c + 2) % 3);
1952 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
1953 mkOp1(OP_NEG, TYPE_F32, val0, val0);
1954
1955 src0 = fetchSrc(0, (c + 1) % 3);
1956 src1 = fetchSrc(1, (c + 2) % 3);
1957 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
1958 } else {
1959 loadImm(dst0[c], 1.0f);
1960 }
1961 }
1962 break;
1963 case TGSI_OPCODE_ISSG:
1964 case TGSI_OPCODE_SSG:
1965 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1966 src0 = fetchSrc(0, c);
1967 val0 = getScratch();
1968 val1 = getScratch();
1969 mkCmp(OP_SET, CC_GT, srcTy, val0, src0, zero);
1970 mkCmp(OP_SET, CC_LT, srcTy, val1, src0, zero);
1971 if (srcTy == TYPE_F32)
1972 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
1973 else
1974 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
1975 }
1976 break;
1977 case TGSI_OPCODE_UCMP:
1978 case TGSI_OPCODE_CMP:
1979 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1980 src0 = fetchSrc(0, c);
1981 src1 = fetchSrc(1, c);
1982 src2 = fetchSrc(2, c);
1983 if (src1 == src2)
1984 mkMov(dst0[c], src1);
1985 else
1986 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
1987 srcTy, dst0[c], src1, src2, src0);
1988 }
1989 break;
1990 case TGSI_OPCODE_FRC:
1991 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
1992 src0 = fetchSrc(0, c);
1993 val0 = getScratch();
1994 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
1995 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
1996 }
1997 break;
1998 case TGSI_OPCODE_ROUND:
1999 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2000 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2001 ->rnd = ROUND_NI;
2002 break;
2003 case TGSI_OPCODE_CLAMP:
2004 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2005 src0 = fetchSrc(0, c);
2006 src1 = fetchSrc(1, c);
2007 src2 = fetchSrc(2, c);
2008 val0 = getScratch();
2009 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2010 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2011 }
2012 break;
2013 case TGSI_OPCODE_SLT:
2014 case TGSI_OPCODE_SGE:
2015 case TGSI_OPCODE_SEQ:
2016 case TGSI_OPCODE_SFL:
2017 case TGSI_OPCODE_SGT:
2018 case TGSI_OPCODE_SLE:
2019 case TGSI_OPCODE_SNE:
2020 case TGSI_OPCODE_STR:
2021 case TGSI_OPCODE_ISGE:
2022 case TGSI_OPCODE_ISLT:
2023 case TGSI_OPCODE_USEQ:
2024 case TGSI_OPCODE_USGE:
2025 case TGSI_OPCODE_USLT:
2026 case TGSI_OPCODE_USNE:
2027 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2028 src0 = fetchSrc(0, c);
2029 src1 = fetchSrc(1, c);
2030 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], src0, src1);
2031 }
2032 break;
2033 case TGSI_OPCODE_KIL:
2034 val0 = new_LValue(func, FILE_PREDICATE);
2035 for (c = 0; c < 4; ++c) {
2036 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, fetchSrc(0, c), zero);
2037 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2038 }
2039 break;
2040 case TGSI_OPCODE_KILP:
2041 mkOp(OP_DISCARD, TYPE_NONE, NULL);
2042 break;
2043 case TGSI_OPCODE_TEX:
2044 case TGSI_OPCODE_TXB:
2045 case TGSI_OPCODE_TXL:
2046 case TGSI_OPCODE_TXP:
2047 // R S L C Dx Dy
2048 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2049 break;
2050 case TGSI_OPCODE_TXD:
2051 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2052 break;
2053 case TGSI_OPCODE_TEX2:
2054 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2055 break;
2056 case TGSI_OPCODE_TXB2:
2057 case TGSI_OPCODE_TXL2:
2058 handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
2059 break;
2060 case TGSI_OPCODE_SAMPLE:
2061 case TGSI_OPCODE_SAMPLE_B:
2062 case TGSI_OPCODE_SAMPLE_D:
2063 case TGSI_OPCODE_SAMPLE_L:
2064 case TGSI_OPCODE_SAMPLE_C:
2065 case TGSI_OPCODE_SAMPLE_C_LZ:
2066 handleTEX(dst0, 1, 2, 0x30, 0x31, 0x40, 0x50);
2067 break;
2068 case TGSI_OPCODE_TXF:
2069 case TGSI_OPCODE_LOAD:
2070 handleTXF(dst0, 1);
2071 break;
2072 case TGSI_OPCODE_TXQ:
2073 case TGSI_OPCODE_SVIEWINFO:
2074 handleTXQ(dst0, TXQ_DIMS);
2075 break;
2076 case TGSI_OPCODE_F2I:
2077 case TGSI_OPCODE_F2U:
2078 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2079 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2080 break;
2081 case TGSI_OPCODE_I2F:
2082 case TGSI_OPCODE_U2F:
2083 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2084 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2085 break;
2086 case TGSI_OPCODE_EMIT:
2087 case TGSI_OPCODE_ENDPRIM:
2088 // get vertex stream if specified (must be immediate)
2089 src0 = tgsi.srcCount() ?
2090 mkImm(tgsi.getSrc(0).getValueU32(0, info)) : zero;
2091 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2092 break;
2093 case TGSI_OPCODE_IF:
2094 {
2095 BasicBlock *ifBB = new BasicBlock(func);
2096
2097 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2098 condBBs.push(bb);
2099 joinBBs.push(bb);
2100
2101 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
2102
2103 setPosition(ifBB, true);
2104 }
2105 break;
2106 case TGSI_OPCODE_ELSE:
2107 {
2108 BasicBlock *elseBB = new BasicBlock(func);
2109 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2110
2111 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2112 condBBs.push(bb);
2113
2114 forkBB->getExit()->asFlow()->target.bb = elseBB;
2115 if (!bb->isTerminated())
2116 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2117
2118 setPosition(elseBB, true);
2119 }
2120 break;
2121 case TGSI_OPCODE_ENDIF:
2122 {
2123 BasicBlock *convBB = new BasicBlock(func);
2124 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2125 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2126
2127 if (!bb->isTerminated()) {
2128 // we only want join if none of the clauses ended with CONT/BREAK/RET
2129 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2130 insertConvergenceOps(convBB, forkBB);
2131 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2132 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2133 }
2134
2135 if (prevBB->getExit()->op == OP_BRA) {
2136 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2137 prevBB->getExit()->asFlow()->target.bb = convBB;
2138 }
2139 setPosition(convBB, true);
2140 }
2141 break;
2142 case TGSI_OPCODE_BGNLOOP:
2143 {
2144 BasicBlock *lbgnBB = new BasicBlock(func);
2145 BasicBlock *lbrkBB = new BasicBlock(func);
2146
2147 loopBBs.push(lbgnBB);
2148 breakBBs.push(lbrkBB);
2149 if (loopBBs.getSize() > func->loopNestingBound)
2150 func->loopNestingBound++;
2151
2152 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2153
2154 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2155 setPosition(lbgnBB, true);
2156 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2157 }
2158 break;
2159 case TGSI_OPCODE_ENDLOOP:
2160 {
2161 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2162
2163 if (!bb->isTerminated()) {
2164 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2165 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2166 }
2167 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2168 }
2169 break;
2170 case TGSI_OPCODE_BRK:
2171 {
2172 if (bb->isTerminated())
2173 break;
2174 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2175 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2176 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2177 }
2178 break;
2179 case TGSI_OPCODE_CONT:
2180 {
2181 if (bb->isTerminated())
2182 break;
2183 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2184 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2185 contBB->explicitCont = true;
2186 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2187 }
2188 break;
2189 case TGSI_OPCODE_BGNSUB:
2190 {
2191 Subroutine *s = getSubroutine(ip);
2192 BasicBlock *entry = new BasicBlock(s->f);
2193 BasicBlock *leave = new BasicBlock(s->f);
2194
2195 // multiple entrypoints possible, keep the graph connected
2196 if (prog->getType() == Program::TYPE_COMPUTE)
2197 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2198
2199 sub.cur = s;
2200 s->f->setEntry(entry);
2201 s->f->setExit(leave);
2202 setPosition(entry, true);
2203 return true;
2204 }
2205 case TGSI_OPCODE_ENDSUB:
2206 {
2207 sub.cur = getSubroutine(prog->main);
2208 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2209 return true;
2210 }
2211 case TGSI_OPCODE_CAL:
2212 {
2213 Subroutine *s = getSubroutine(tgsi.getLabel());
2214 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2215 func->call.attach(&s->f->call, Graph::Edge::TREE);
2216 return true;
2217 }
2218 case TGSI_OPCODE_RET:
2219 {
2220 if (bb->isTerminated())
2221 return true;
2222 BasicBlock *leave = BasicBlock::get(func->cfgExit);
2223
2224 if (!isEndOfSubroutine(ip + 1)) {
2225 // insert a PRERET at the entry if this is an early return
2226 // (only needed for sharing code in the epilogue)
2227 BasicBlock *pos = getBB();
2228 setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2229 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2230 setPosition(pos, true);
2231 }
2232 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2233 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2234 }
2235 break;
2236 case TGSI_OPCODE_END:
2237 {
2238 // attach and generate epilogue code
2239 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2240 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2241 setPosition(epilogue, true);
2242 if (prog->getType() == Program::TYPE_FRAGMENT)
2243 exportOutputs();
2244 if (info->io.genUserClip > 0)
2245 handleUserClipPlanes();
2246 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2247 }
2248 break;
2249 case TGSI_OPCODE_SWITCH:
2250 case TGSI_OPCODE_CASE:
2251 ERROR("switch/case opcode encountered, should have been lowered\n");
2252 abort();
2253 break;
2254 default:
2255 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
2256 assert(0);
2257 break;
2258 }
2259
2260 if (tgsi.dstCount()) {
2261 for (c = 0; c < 4; ++c) {
2262 if (!dst0[c])
2263 continue;
2264 if (dst0[c] != rDst0[c])
2265 mkMov(rDst0[c], dst0[c]);
2266 storeDst(0, c, rDst0[c]);
2267 }
2268 }
2269 vtxBaseValid = 0;
2270
2271 return true;
2272 }
2273
2274 void
2275 Converter::handleUserClipPlanes()
2276 {
2277 Value *res[8];
2278 int n, i, c;
2279
2280 for (c = 0; c < 4; ++c) {
2281 for (i = 0; i < info->io.genUserClip; ++i) {
2282 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpBinding,
2283 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
2284 Value *ucp = mkLoad(TYPE_F32, sym, NULL);
2285 if (c == 0)
2286 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
2287 else
2288 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
2289 }
2290 }
2291
2292 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
2293
2294 for (i = 0; i < info->io.genUserClip; ++i) {
2295 n = i / 4 + first;
2296 c = i % 4;
2297 Symbol *sym =
2298 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
2299 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
2300 }
2301 }
2302
2303 void
2304 Converter::exportOutputs()
2305 {
2306 for (unsigned int i = 0; i < info->numOutputs; ++i) {
2307 for (unsigned int c = 0; c < 4; ++c) {
2308 if (!oData.exists(sub.cur->values, i, c))
2309 continue;
2310 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
2311 info->out[i].slot[c] * 4);
2312 Value *val = oData.load(sub.cur->values, i, c, NULL);
2313 if (val)
2314 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
2315 }
2316 }
2317 }
2318
2319 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
2320 code(code),
2321 tgsi(NULL),
2322 tData(this), aData(this), pData(this), oData(this)
2323 {
2324 info = code->info;
2325
2326 const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
2327
2328 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
2329 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
2330 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
2331 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
2332
2333 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
2334 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
2335 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_ADDRESS, 0);
2336 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
2337
2338 for (int vol = 0, i = 0; i < code->tempArrayCount; ++i) {
2339 int len = code->tempArrays[i].u32 >> 2;
2340 int dim = code->tempArrays[i].u32 & 3;
2341
2342 lData.push_back(DataArray(this));
2343 lData.back().setup(TGSI_FILE_TEMPORARY_ARRAY, i, vol, len, dim, 4,
2344 FILE_MEMORY_LOCAL, 0);
2345
2346 vol += (len * dim * 4 + 0xf) & ~0xf;
2347 }
2348
2349 for (int vol = 0, i = 0; i < code->immdArrayCount; ++i) {
2350 int len = code->immdArrays[i].u32 >> 2;
2351 int dim = code->immdArrays[i].u32 & 3;
2352
2353 lData.push_back(DataArray(this));
2354 lData.back().setup(TGSI_FILE_IMMEDIATE_ARRAY, i, vol, len, dim, 4,
2355 FILE_MEMORY_CONST, 14);
2356
2357 vol += (len * dim * 4 + 0xf) & ~0xf;
2358 }
2359
2360 zero = mkImm((uint32_t)0);
2361
2362 vtxBaseValid = 0;
2363 }
2364
2365 Converter::~Converter()
2366 {
2367 }
2368
2369 template<typename T> inline void
2370 Converter::BindArgumentsPass::updateCallArgs(
2371 Instruction *i, void (Instruction::*setArg)(int, Value *),
2372 T (Function::*proto))
2373 {
2374 Function *g = i->asFlow()->target.fn;
2375 Subroutine *subg = conv.getSubroutine(g);
2376
2377 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
2378 Value *v = (g->*proto)[a].get();
2379 const Converter::Location &l = subg->values.l.find(v)->second;
2380 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
2381
2382 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
2383 }
2384 }
2385
2386 template<typename T> inline void
2387 Converter::BindArgumentsPass::updatePrototype(
2388 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
2389 {
2390 (func->*updateSet)();
2391
2392 for (unsigned i = 0; i < set->getSize(); ++i) {
2393 Value *v = func->getLValue(i);
2394
2395 // only include values with a matching TGSI register
2396 if (set->test(i) && sub->values.l.find(v) != sub->values.l.end())
2397 (func->*proto).push_back(v);
2398 }
2399 }
2400
2401 bool
2402 Converter::BindArgumentsPass::visit(Function *f)
2403 {
2404 sub = conv.getSubroutine(f);
2405
2406 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
2407 !bi.end(); bi.next()) {
2408 for (Instruction *i = BasicBlock::get(bi)->getFirst();
2409 i; i = i->next) {
2410 if (i->op == OP_CALL && !i->asFlow()->builtin) {
2411 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
2412 updateCallArgs(i, &Instruction::setDef, &Function::outs);
2413 }
2414 }
2415 }
2416
2417 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
2418 return true;
2419 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
2420 &Function::buildLiveSets, &Function::ins);
2421 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
2422 &Function::buildDefSets, &Function::outs);
2423
2424 return true;
2425 }
2426
2427 bool
2428 Converter::run()
2429 {
2430 BasicBlock *entry = new BasicBlock(prog->main);
2431 BasicBlock *leave = new BasicBlock(prog->main);
2432
2433 prog->main->setEntry(entry);
2434 prog->main->setExit(leave);
2435
2436 setPosition(entry, true);
2437 sub.cur = getSubroutine(prog->main);
2438
2439 if (info->io.genUserClip > 0) {
2440 for (int c = 0; c < 4; ++c)
2441 clipVtx[c] = getScratch();
2442 }
2443
2444 if (prog->getType() == Program::TYPE_FRAGMENT) {
2445 Symbol *sv = mkSysVal(SV_POSITION, 3);
2446 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
2447 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
2448 }
2449
2450 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
2451 if (!handleInstruction(&code->insns[ip]))
2452 return false;
2453 }
2454
2455 if (!BindArgumentsPass(*this).run(prog))
2456 return false;
2457
2458 return true;
2459 }
2460
2461 } // unnamed namespace
2462
2463 namespace nv50_ir {
2464
2465 bool
2466 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
2467 {
2468 tgsi::Source src(info);
2469 if (!src.scanSource())
2470 return false;
2471 tlsSize = info->bin.tlsSpace;
2472
2473 Converter builder(this, &src);
2474 return builder.run();
2475 }
2476
2477 } // namespace nv50_ir