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nv50: alloc_reg on reg_instance
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* STACK: Conditionals and loops have to use the (per warp) stack.
102 * Stack entries consist of an entry type (divergent path, join at),
103 * a mask indicating the active threads of the warp, and an address.
104 * MPs can store 12 stack entries internally, if we need more (and
105 * we probably do), we have to create a stack buffer in VRAM.
106 */
107 /* impose low limits for now */
108 #define NV50_MAX_COND_NESTING 4
109 #define NV50_MAX_LOOP_NESTING 3
110
111 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
112
113 struct nv50_pc {
114 struct nv50_program *p;
115
116 /* hw resources */
117 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
118 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
119
120 /* tgsi resources */
121 struct nv50_reg *temp;
122 int temp_nr;
123 struct nv50_reg *attr;
124 int attr_nr;
125 struct nv50_reg *result;
126 int result_nr;
127 struct nv50_reg *param;
128 int param_nr;
129 struct nv50_reg *immd;
130 uint32_t *immd_buf;
131 int immd_nr;
132 struct nv50_reg **addr;
133 int addr_nr;
134 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
135
136 struct nv50_reg *temp_temp[16];
137 unsigned temp_temp_nr;
138
139 /* broadcast and destination replacement regs */
140 struct nv50_reg *r_brdc;
141 struct nv50_reg *r_dst[4];
142
143 struct nv50_reg reg_instances[16];
144 unsigned reg_instance_nr;
145
146 unsigned interp_mode[32];
147 /* perspective interpolation registers */
148 struct nv50_reg *iv_p;
149 struct nv50_reg *iv_c;
150
151 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
152 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
153 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
154 int if_lvl, loop_lvl;
155 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
156
157 /* current instruction and total number of insns */
158 unsigned insn_cur;
159 unsigned insn_nr;
160
161 boolean allow32;
162
163 uint8_t edgeflag_out;
164 };
165
166 static INLINE void
167 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
168 {
169 reg->type = type;
170 reg->index = index;
171 reg->hw = hw;
172 reg->mod = 0;
173 reg->rhw = -1;
174 reg->acc = 0;
175 }
176
177 static INLINE unsigned
178 popcnt4(uint32_t val)
179 {
180 static const unsigned cnt[16]
181 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
182 return cnt[val & 0xf];
183 }
184
185 static void
186 terminate_mbb(struct nv50_pc *pc)
187 {
188 int i;
189
190 /* remove records of temporary address register values */
191 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
192 pc->r_addr[i].rhw = -1;
193 }
194
195 static void
196 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
197 {
198 int i = 0;
199
200 if (reg->type == P_RESULT) {
201 if (pc->p->cfg.high_result < (reg->hw + 1))
202 pc->p->cfg.high_result = reg->hw + 1;
203 }
204
205 if (reg->type != P_TEMP)
206 return;
207
208 if (reg->hw >= 0) {
209 /*XXX: do this here too to catch FP temp-as-attr usage..
210 * not clean, but works */
211 if (pc->p->cfg.high_temp < (reg->hw + 1))
212 pc->p->cfg.high_temp = reg->hw + 1;
213 return;
214 }
215
216 if (reg->rhw != -1) {
217 /* try to allocate temporary with index rhw first */
218 if (!(pc->r_temp[reg->rhw])) {
219 pc->r_temp[reg->rhw] = reg;
220 reg->hw = reg->rhw;
221 if (pc->p->cfg.high_temp < (reg->rhw + 1))
222 pc->p->cfg.high_temp = reg->rhw + 1;
223 return;
224 }
225 /* make sure we don't get things like $r0 needs to go
226 * in $r1 and $r1 in $r0
227 */
228 i = pc->result_nr * 4;
229 }
230
231 for (; i < NV50_SU_MAX_TEMP; i++) {
232 if (!(pc->r_temp[i])) {
233 pc->r_temp[i] = reg;
234 reg->hw = i;
235 if (pc->p->cfg.high_temp < (i + 1))
236 pc->p->cfg.high_temp = i + 1;
237 return;
238 }
239 }
240
241 assert(0);
242 }
243
244 static INLINE struct nv50_reg *
245 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
246 {
247 struct nv50_reg *ri;
248
249 assert(pc->reg_instance_nr < 16);
250 ri = &pc->reg_instances[pc->reg_instance_nr++];
251 if (reg) {
252 alloc_reg(pc, reg);
253 *ri = *reg;
254 reg->mod = 0;
255 }
256 return ri;
257 }
258
259 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
260 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
261 * lest we risk temp_temps overwriting regs alloc'd "later".
262 */
263 static struct nv50_reg *
264 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
265 {
266 struct nv50_reg *r;
267 int i;
268
269 if (dst && dst->type == P_TEMP && dst->hw == -1)
270 return dst;
271
272 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
273 if (!pc->r_temp[i]) {
274 r = MALLOC_STRUCT(nv50_reg);
275 ctor_reg(r, P_TEMP, -1, i);
276 pc->r_temp[i] = r;
277 return r;
278 }
279 }
280
281 assert(0);
282 return NULL;
283 }
284
285 /* Assign the hw of the discarded temporary register src
286 * to the tgsi register dst and free src.
287 */
288 static void
289 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
290 {
291 assert(src->index == -1 && src->hw != -1);
292
293 if (dst->hw != -1)
294 pc->r_temp[dst->hw] = NULL;
295 pc->r_temp[src->hw] = dst;
296 dst->hw = src->hw;
297
298 FREE(src);
299 }
300
301 /* release the hardware resource held by r */
302 static void
303 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
304 {
305 assert(r->type == P_TEMP);
306 if (r->hw == -1)
307 return;
308
309 assert(pc->r_temp[r->hw] == r);
310 pc->r_temp[r->hw] = NULL;
311
312 r->acc = 0;
313 if (r->index == -1)
314 FREE(r);
315 }
316
317 static void
318 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
319 {
320 if (r->index == -1) {
321 unsigned hw = r->hw;
322
323 FREE(pc->r_temp[hw]);
324 pc->r_temp[hw] = NULL;
325 }
326 }
327
328 static int
329 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
330 {
331 int i;
332
333 if ((idx + 4) >= NV50_SU_MAX_TEMP)
334 return 1;
335
336 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
337 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
338 return alloc_temp4(pc, dst, idx + 4);
339
340 for (i = 0; i < 4; i++) {
341 dst[i] = MALLOC_STRUCT(nv50_reg);
342 ctor_reg(dst[i], P_TEMP, -1, idx + i);
343 pc->r_temp[idx + i] = dst[i];
344 }
345
346 return 0;
347 }
348
349 static void
350 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
351 {
352 int i;
353
354 for (i = 0; i < 4; i++)
355 free_temp(pc, reg[i]);
356 }
357
358 static struct nv50_reg *
359 temp_temp(struct nv50_pc *pc)
360 {
361 if (pc->temp_temp_nr >= 16)
362 assert(0);
363
364 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
365 return pc->temp_temp[pc->temp_temp_nr++];
366 }
367
368 static void
369 kill_temp_temp(struct nv50_pc *pc)
370 {
371 int i;
372
373 for (i = 0; i < pc->temp_temp_nr; i++)
374 free_temp(pc, pc->temp_temp[i]);
375 pc->temp_temp_nr = 0;
376 }
377
378 static int
379 ctor_immd_4u32(struct nv50_pc *pc,
380 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
381 {
382 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
383
384 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
385
386 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
387 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
388 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
389 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
390
391 return pc->immd_nr++;
392 }
393
394 static INLINE int
395 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
396 {
397 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
398 }
399
400 static struct nv50_reg *
401 alloc_immd(struct nv50_pc *pc, float f)
402 {
403 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
404 unsigned hw;
405
406 for (hw = 0; hw < pc->immd_nr * 4; hw++)
407 if (pc->immd_buf[hw] == fui(f))
408 break;
409
410 if (hw == pc->immd_nr * 4)
411 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
412
413 ctor_reg(r, P_IMMD, -1, hw);
414 return r;
415 }
416
417 static struct nv50_program_exec *
418 exec(struct nv50_pc *pc)
419 {
420 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
421
422 e->param.index = -1;
423 return e;
424 }
425
426 static void
427 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
428 {
429 struct nv50_program *p = pc->p;
430
431 if (p->exec_tail)
432 p->exec_tail->next = e;
433 if (!p->exec_head)
434 p->exec_head = e;
435 p->exec_tail = e;
436 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
437 }
438
439 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
440
441 static boolean
442 is_long(struct nv50_program_exec *e)
443 {
444 if (e->inst[0] & 1)
445 return TRUE;
446 return FALSE;
447 }
448
449 static boolean
450 is_immd(struct nv50_program_exec *e)
451 {
452 if (is_long(e) && (e->inst[1] & 3) == 3)
453 return TRUE;
454 return FALSE;
455 }
456
457 static INLINE void
458 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
459 struct nv50_program_exec *e)
460 {
461 set_long(pc, e);
462 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
463 e->inst[1] |= (pred << 7) | (idx << 12);
464 }
465
466 static INLINE void
467 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
468 struct nv50_program_exec *e)
469 {
470 set_long(pc, e);
471 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
472 e->inst[1] |= (idx << 4) | (on << 6);
473 }
474
475 static INLINE void
476 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
477 {
478 if (is_long(e))
479 return;
480
481 e->inst[0] |= 1;
482 set_pred(pc, 0xf, 0, e);
483 set_pred_wr(pc, 0, 0, e);
484 }
485
486 static INLINE void
487 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
488 {
489 if (dst->type == P_RESULT) {
490 set_long(pc, e);
491 e->inst[1] |= 0x00000008;
492 }
493
494 alloc_reg(pc, dst);
495 if (dst->hw > 63)
496 set_long(pc, e);
497 e->inst[0] |= (dst->hw << 2);
498 }
499
500 static INLINE void
501 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
502 {
503 set_long(pc, e);
504 /* XXX: can't be predicated - bits overlap; cases where both
505 * are required should be avoided by using pc->allow32 */
506 set_pred(pc, 0, 0, e);
507 set_pred_wr(pc, 0, 0, e);
508
509 e->inst[1] |= 0x00000002 | 0x00000001;
510 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
511 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
512 }
513
514 static INLINE void
515 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
516 {
517 assert(!(e->inst[0] & 0x0c000000));
518 assert(!(e->inst[1] & 0x00000004));
519
520 e->inst[0] |= (a->hw & 3) << 26;
521 e->inst[1] |= (a->hw >> 2) << 2;
522 }
523
524 static void
525 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
526 struct nv50_reg *src0, uint16_t src1_val)
527 {
528 struct nv50_program_exec *e = exec(pc);
529
530 e->inst[0] = 0xd0000000 | (src1_val << 9);
531 e->inst[1] = 0x20000000;
532 set_long(pc, e);
533 e->inst[0] |= dst->hw << 2;
534 if (src0) /* otherwise will add to $a0, which is always 0 */
535 set_addr(e, src0);
536
537 emit(pc, e);
538 }
539
540 static struct nv50_reg *
541 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
542 {
543 struct nv50_reg *a_tgsi = NULL, *a = NULL;
544 int i;
545 uint8_t avail = ~pc->addr_alloc;
546
547 if (!ref) {
548 /* allocate for TGSI_FILE_ADDRESS */
549 while (avail) {
550 i = ffs(avail) - 1;
551
552 if (pc->r_addr[i].rhw < 0 ||
553 pc->r_addr[i].acc != pc->insn_cur) {
554 pc->addr_alloc |= (1 << i);
555
556 pc->r_addr[i].rhw = -1;
557 pc->r_addr[i].index = i;
558 return &pc->r_addr[i];
559 }
560 avail &= ~(1 << i);
561 }
562 assert(0);
563 return NULL;
564 }
565
566 /* Allocate and set an address reg so we can access 'ref'.
567 *
568 * If and r_addr->index will be -1 or the hw index the value
569 * value in rhw is relative to. If rhw < 0, the reg has not
570 * been initialized or is in use for TGSI_FILE_ADDRESS.
571 */
572 while (avail) { /* only consider regs that are not TGSI */
573 i = ffs(avail) - 1;
574 avail &= ~(1 << i);
575
576 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
577 /* prefer an usused reg with low hw index */
578 a = &pc->r_addr[i];
579 continue;
580 }
581 if (!a && pc->r_addr[i].acc != pc->insn_cur)
582 a = &pc->r_addr[i];
583
584 if (ref->hw - pc->r_addr[i].rhw >= 128)
585 continue;
586
587 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
588 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
589 pc->r_addr[i].acc = pc->insn_cur;
590 return &pc->r_addr[i];
591 }
592 }
593 assert(a);
594
595 if (ref->acc < 0)
596 a_tgsi = pc->addr[ref->index];
597
598 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
599
600 a->rhw = ref->hw & ~0x7f;
601 a->acc = pc->insn_cur;
602 a->index = a_tgsi ? ref->index : -1;
603 return a;
604 }
605
606 #define INTERP_LINEAR 0
607 #define INTERP_FLAT 1
608 #define INTERP_PERSPECTIVE 2
609 #define INTERP_CENTROID 4
610
611 /* interpolant index has been stored in dst->rhw */
612 static void
613 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
614 unsigned mode)
615 {
616 assert(dst->rhw != -1);
617 struct nv50_program_exec *e = exec(pc);
618
619 e->inst[0] |= 0x80000000;
620 set_dst(pc, dst, e);
621 e->inst[0] |= (dst->rhw << 16);
622
623 if (mode & INTERP_FLAT) {
624 e->inst[0] |= (1 << 8);
625 } else {
626 if (mode & INTERP_PERSPECTIVE) {
627 e->inst[0] |= (1 << 25);
628 alloc_reg(pc, iv);
629 e->inst[0] |= (iv->hw << 9);
630 }
631
632 if (mode & INTERP_CENTROID)
633 e->inst[0] |= (1 << 24);
634 }
635
636 emit(pc, e);
637 }
638
639 static void
640 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
641 struct nv50_program_exec *e)
642 {
643 set_long(pc, e);
644
645 e->param.index = src->hw & 127;
646 e->param.shift = s;
647 e->param.mask = m << (s % 32);
648
649 if (src->hw > 127)
650 set_addr(e, alloc_addr(pc, src));
651 else
652 if (src->acc < 0) {
653 assert(src->type == P_CONST);
654 set_addr(e, pc->addr[src->index]);
655 }
656
657 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
658 }
659
660 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
661 static void
662 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
663 {
664 struct nv50_program_exec *e = exec(pc);
665
666 e->inst[0] = 0x10000000;
667 if (!pc->allow32)
668 set_long(pc, e);
669
670 set_dst(pc, dst, e);
671
672 if (!is_long(e) && src->type == P_IMMD) {
673 set_immd(pc, src, e);
674 /*XXX: 32-bit, but steals part of "half" reg space - need to
675 * catch and handle this case if/when we do half-regs
676 */
677 } else
678 if (src->type == P_IMMD || src->type == P_CONST) {
679 set_long(pc, e);
680 set_data(pc, src, 0x7f, 9, e);
681 e->inst[1] |= 0x20000000; /* mov from c[] */
682 } else {
683 if (src->type == P_ATTR) {
684 set_long(pc, e);
685 e->inst[1] |= 0x00200000;
686 }
687
688 alloc_reg(pc, src);
689 if (src->hw > 63)
690 set_long(pc, e);
691 e->inst[0] |= (src->hw << 9);
692 }
693
694 if (is_long(e) && !is_immd(e)) {
695 e->inst[1] |= 0x04000000; /* 32-bit */
696 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
697 if (!(e->inst[1] & 0x20000000))
698 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
699 } else
700 e->inst[0] |= 0x00008000;
701
702 emit(pc, e);
703 }
704
705 static INLINE void
706 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
707 {
708 struct nv50_reg *imm = alloc_immd(pc, f);
709 emit_mov(pc, dst, imm);
710 FREE(imm);
711 }
712
713 static void
714 emit_nop(struct nv50_pc *pc)
715 {
716 struct nv50_program_exec *e = exec(pc);
717
718 e->inst[0] = 0xf0000000;
719 set_long(pc, e);
720 e->inst[1] = 0xe0000000;
721 emit(pc, e);
722 }
723
724 static boolean
725 check_swap_src_0_1(struct nv50_pc *pc,
726 struct nv50_reg **s0, struct nv50_reg **s1)
727 {
728 struct nv50_reg *src0 = *s0, *src1 = *s1;
729
730 if (src0->type == P_CONST) {
731 if (src1->type != P_CONST) {
732 *s0 = src1;
733 *s1 = src0;
734 return TRUE;
735 }
736 } else
737 if (src1->type == P_ATTR) {
738 if (src0->type != P_ATTR) {
739 *s0 = src1;
740 *s1 = src0;
741 return TRUE;
742 }
743 }
744
745 return FALSE;
746 }
747
748 static void
749 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
750 struct nv50_program_exec *e)
751 {
752 struct nv50_reg *temp;
753
754 if (src->type != P_TEMP) {
755 temp = temp_temp(pc);
756 emit_mov(pc, temp, src);
757 src = temp;
758 }
759
760 alloc_reg(pc, src);
761 if (src->hw > 63)
762 set_long(pc, e);
763 e->inst[0] |= (src->hw << 9);
764 }
765
766 static void
767 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
768 {
769 if (src->type == P_ATTR) {
770 set_long(pc, e);
771 e->inst[1] |= 0x00200000;
772 } else
773 if (src->type == P_CONST || src->type == P_IMMD) {
774 struct nv50_reg *temp = temp_temp(pc);
775
776 emit_mov(pc, temp, src);
777 src = temp;
778 }
779
780 alloc_reg(pc, src);
781 if (src->hw > 63)
782 set_long(pc, e);
783 e->inst[0] |= (src->hw << 9);
784 }
785
786 static void
787 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
788 {
789 if (src->type == P_ATTR) {
790 struct nv50_reg *temp = temp_temp(pc);
791
792 emit_mov(pc, temp, src);
793 src = temp;
794 } else
795 if (src->type == P_CONST || src->type == P_IMMD) {
796 assert(!(e->inst[0] & 0x00800000));
797 if (e->inst[0] & 0x01000000) {
798 struct nv50_reg *temp = temp_temp(pc);
799
800 emit_mov(pc, temp, src);
801 src = temp;
802 } else {
803 set_data(pc, src, 0x7f, 16, e);
804 e->inst[0] |= 0x00800000;
805 }
806 }
807
808 alloc_reg(pc, src);
809 if (src->hw > 63)
810 set_long(pc, e);
811 e->inst[0] |= ((src->hw & 127) << 16);
812 }
813
814 static void
815 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
816 {
817 set_long(pc, e);
818
819 if (src->type == P_ATTR) {
820 struct nv50_reg *temp = temp_temp(pc);
821
822 emit_mov(pc, temp, src);
823 src = temp;
824 } else
825 if (src->type == P_CONST || src->type == P_IMMD) {
826 assert(!(e->inst[0] & 0x01000000));
827 if (e->inst[0] & 0x00800000) {
828 struct nv50_reg *temp = temp_temp(pc);
829
830 emit_mov(pc, temp, src);
831 src = temp;
832 } else {
833 set_data(pc, src, 0x7f, 32+14, e);
834 e->inst[0] |= 0x01000000;
835 }
836 }
837
838 alloc_reg(pc, src);
839 e->inst[1] |= ((src->hw & 127) << 14);
840 }
841
842 static void
843 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
844 {
845 struct nv50_program_exec *e = exec(pc);
846
847 assert(dst->type == P_TEMP);
848 e->inst[1] = 0x20000000 | (pred << 12);
849 set_long(pc, e);
850 set_dst(pc, dst, e);
851
852 emit(pc, e);
853 }
854
855 static void
856 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
857 {
858 struct nv50_program_exec *e = exec(pc);
859
860 e->inst[0] = 0x000001fc;
861 e->inst[1] = 0xa0000008;
862 set_long(pc, e);
863 set_pred_wr(pc, 1, pred, e);
864 set_src_0_restricted(pc, src, e);
865
866 emit(pc, e);
867 }
868
869 static void
870 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
871 struct nv50_reg *src1)
872 {
873 struct nv50_program_exec *e = exec(pc);
874
875 e->inst[0] |= 0xc0000000;
876
877 if (!pc->allow32)
878 set_long(pc, e);
879
880 check_swap_src_0_1(pc, &src0, &src1);
881 set_dst(pc, dst, e);
882 set_src_0(pc, src0, e);
883 if (src1->type == P_IMMD && !is_long(e)) {
884 if (src0->mod ^ src1->mod)
885 e->inst[0] |= 0x00008000;
886 set_immd(pc, src1, e);
887 } else {
888 set_src_1(pc, src1, e);
889 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
890 if (is_long(e))
891 e->inst[1] |= 0x08000000;
892 else
893 e->inst[0] |= 0x00008000;
894 }
895 }
896
897 emit(pc, e);
898 }
899
900 static void
901 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
902 struct nv50_reg *src0, struct nv50_reg *src1)
903 {
904 struct nv50_program_exec *e = exec(pc);
905
906 e->inst[0] = 0xb0000000;
907
908 alloc_reg(pc, src1);
909 check_swap_src_0_1(pc, &src0, &src1);
910
911 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
912 set_long(pc, e);
913 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
914 ((src1->mod & NV50_MOD_NEG) << 27);
915 }
916
917 set_dst(pc, dst, e);
918 set_src_0(pc, src0, e);
919 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
920 set_src_2(pc, src1, e);
921 else
922 if (src1->type == P_IMMD)
923 set_immd(pc, src1, e);
924 else
925 set_src_1(pc, src1, e);
926
927 emit(pc, e);
928 }
929
930 static void
931 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
932 uint8_t s)
933 {
934 struct nv50_program_exec *e = exec(pc);
935
936 set_long(pc, e);
937 e->inst[1] |= 0xc0000000;
938
939 e->inst[0] |= dst->hw << 2;
940 e->inst[0] |= s << 16; /* shift left */
941 set_src_0_restricted(pc, src, e);
942
943 emit(pc, e);
944 }
945
946 static void
947 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
948 struct nv50_reg *src0, struct nv50_reg *src1)
949 {
950 struct nv50_program_exec *e = exec(pc);
951
952 set_long(pc, e);
953 e->inst[0] |= 0xb0000000;
954 e->inst[1] |= (sub << 29);
955
956 check_swap_src_0_1(pc, &src0, &src1);
957 set_dst(pc, dst, e);
958 set_src_0(pc, src0, e);
959 set_src_1(pc, src1, e);
960
961 if (src0->mod & NV50_MOD_ABS)
962 e->inst[1] |= 0x00100000;
963 if (src1->mod & NV50_MOD_ABS)
964 e->inst[1] |= 0x00080000;
965
966 emit(pc, e);
967 }
968
969 static INLINE void
970 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
971 struct nv50_reg *src1)
972 {
973 src1->mod ^= NV50_MOD_NEG;
974 emit_add(pc, dst, src0, src1);
975 src1->mod ^= NV50_MOD_NEG;
976 }
977
978 static void
979 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
980 struct nv50_reg *src1, unsigned op)
981 {
982 struct nv50_program_exec *e = exec(pc);
983
984 e->inst[0] = 0xd0000000;
985 set_long(pc, e);
986
987 check_swap_src_0_1(pc, &src0, &src1);
988 set_dst(pc, dst, e);
989 set_src_0(pc, src0, e);
990
991 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
992 op != TGSI_OPCODE_XOR)
993 assert(!"invalid bit op");
994
995 assert(!(src0->mod | src1->mod));
996
997 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
998 set_immd(pc, src1, e);
999 if (op == TGSI_OPCODE_OR)
1000 e->inst[0] |= 0x0100;
1001 else
1002 if (op == TGSI_OPCODE_XOR)
1003 e->inst[0] |= 0x8000;
1004 } else {
1005 set_src_1(pc, src1, e);
1006 e->inst[1] |= 0x04000000; /* 32 bit */
1007 if (op == TGSI_OPCODE_OR)
1008 e->inst[1] |= 0x4000;
1009 else
1010 if (op == TGSI_OPCODE_XOR)
1011 e->inst[1] |= 0x8000;
1012 }
1013
1014 emit(pc, e);
1015 }
1016
1017 static void
1018 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1019 struct nv50_reg *src1, struct nv50_reg *src2)
1020 {
1021 struct nv50_program_exec *e = exec(pc);
1022
1023 e->inst[0] |= 0xe0000000;
1024
1025 check_swap_src_0_1(pc, &src0, &src1);
1026 set_dst(pc, dst, e);
1027 set_src_0(pc, src0, e);
1028 set_src_1(pc, src1, e);
1029 set_src_2(pc, src2, e);
1030
1031 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1032 e->inst[1] |= 0x04000000;
1033 if (src2->mod & NV50_MOD_NEG)
1034 e->inst[1] |= 0x08000000;
1035
1036 emit(pc, e);
1037 }
1038
1039 static INLINE void
1040 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1041 struct nv50_reg *src1, struct nv50_reg *src2)
1042 {
1043 src2->mod ^= NV50_MOD_NEG;
1044 emit_mad(pc, dst, src0, src1, src2);
1045 src2->mod ^= NV50_MOD_NEG;
1046 }
1047
1048 #define NV50_FLOP_RCP 0
1049 #define NV50_FLOP_RSQ 2
1050 #define NV50_FLOP_LG2 3
1051 #define NV50_FLOP_SIN 4
1052 #define NV50_FLOP_COS 5
1053 #define NV50_FLOP_EX2 6
1054
1055 /* rcp, rsqrt, lg2 support neg and abs */
1056 static void
1057 emit_flop(struct nv50_pc *pc, unsigned sub,
1058 struct nv50_reg *dst, struct nv50_reg *src)
1059 {
1060 struct nv50_program_exec *e = exec(pc);
1061
1062 e->inst[0] |= 0x90000000;
1063 if (sub || src->mod) {
1064 set_long(pc, e);
1065 e->inst[1] |= (sub << 29);
1066 }
1067
1068 set_dst(pc, dst, e);
1069 set_src_0_restricted(pc, src, e);
1070
1071 assert(!src->mod || sub < 4);
1072
1073 if (src->mod & NV50_MOD_NEG)
1074 e->inst[1] |= 0x04000000;
1075 if (src->mod & NV50_MOD_ABS)
1076 e->inst[1] |= 0x00100000;
1077
1078 emit(pc, e);
1079 }
1080
1081 static void
1082 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1083 {
1084 struct nv50_program_exec *e = exec(pc);
1085
1086 e->inst[0] |= 0xb0000000;
1087
1088 set_dst(pc, dst, e);
1089 set_src_0(pc, src, e);
1090 set_long(pc, e);
1091 e->inst[1] |= (6 << 29) | 0x00004000;
1092
1093 if (src->mod & NV50_MOD_NEG)
1094 e->inst[1] |= 0x04000000;
1095 if (src->mod & NV50_MOD_ABS)
1096 e->inst[1] |= 0x00100000;
1097
1098 emit(pc, e);
1099 }
1100
1101 static void
1102 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1103 {
1104 struct nv50_program_exec *e = exec(pc);
1105
1106 e->inst[0] |= 0xb0000000;
1107
1108 set_dst(pc, dst, e);
1109 set_src_0(pc, src, e);
1110 set_long(pc, e);
1111 e->inst[1] |= (6 << 29);
1112
1113 if (src->mod & NV50_MOD_NEG)
1114 e->inst[1] |= 0x04000000;
1115 if (src->mod & NV50_MOD_ABS)
1116 e->inst[1] |= 0x00100000;
1117
1118 emit(pc, e);
1119 }
1120
1121 #define CVTOP_RN 0x01
1122 #define CVTOP_FLOOR 0x03
1123 #define CVTOP_CEIL 0x05
1124 #define CVTOP_TRUNC 0x07
1125 #define CVTOP_SAT 0x08
1126 #define CVTOP_ABS 0x10
1127
1128 /* 0x04 == 32 bit dst */
1129 /* 0x40 == dst is float */
1130 /* 0x80 == src is float */
1131 #define CVT_F32_F32 0xc4
1132 #define CVT_F32_S32 0x44
1133 #define CVT_S32_F32 0x8c
1134 #define CVT_S32_S32 0x0c
1135 #define CVT_NEG 0x20
1136 #define CVT_RI 0x08
1137
1138 static void
1139 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1140 int wp, unsigned cvn, unsigned fmt)
1141 {
1142 struct nv50_program_exec *e;
1143
1144 e = exec(pc);
1145 set_long(pc, e);
1146
1147 e->inst[0] |= 0xa0000000;
1148 e->inst[1] |= 0x00004000; /* 32 bit src */
1149 e->inst[1] |= (cvn << 16);
1150 e->inst[1] |= (fmt << 24);
1151 set_src_0(pc, src, e);
1152
1153 if (wp >= 0)
1154 set_pred_wr(pc, 1, wp, e);
1155
1156 if (dst)
1157 set_dst(pc, dst, e);
1158 else {
1159 e->inst[0] |= 0x000001fc;
1160 e->inst[1] |= 0x00000008;
1161 }
1162
1163 emit(pc, e);
1164 }
1165
1166 /* nv50 Condition codes:
1167 * 0x1 = LT
1168 * 0x2 = EQ
1169 * 0x3 = LE
1170 * 0x4 = GT
1171 * 0x5 = NE
1172 * 0x6 = GE
1173 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1174 * 0x8 = unordered bit (allows NaN)
1175 */
1176 static void
1177 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1178 struct nv50_reg *src0, struct nv50_reg *src1)
1179 {
1180 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1181
1182 struct nv50_program_exec *e = exec(pc);
1183 struct nv50_reg *rdst;
1184
1185 assert(ccode < 16);
1186 if (check_swap_src_0_1(pc, &src0, &src1))
1187 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1188
1189 rdst = dst;
1190 if (dst && dst->type != P_TEMP)
1191 dst = alloc_temp(pc, NULL);
1192
1193 /* set.u32 */
1194 set_long(pc, e);
1195 e->inst[0] |= 0xb0000000;
1196 e->inst[1] |= 0x60000000 | (ccode << 14);
1197
1198 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1199 * that doesn't seem to match what the hw actually does
1200 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1201 */
1202
1203 if (wp >= 0)
1204 set_pred_wr(pc, 1, wp, e);
1205 if (dst)
1206 set_dst(pc, dst, e);
1207 else {
1208 e->inst[0] |= 0x000001fc;
1209 e->inst[1] |= 0x00000008;
1210 }
1211
1212 set_src_0(pc, src0, e);
1213 set_src_1(pc, src1, e);
1214
1215 emit(pc, e);
1216
1217 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1218 if (rdst)
1219 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1220 if (rdst && rdst != dst)
1221 free_temp(pc, dst);
1222 }
1223
1224 static INLINE unsigned
1225 map_tgsi_setop_cc(unsigned op)
1226 {
1227 switch (op) {
1228 case TGSI_OPCODE_SLT: return 0x1;
1229 case TGSI_OPCODE_SGE: return 0x6;
1230 case TGSI_OPCODE_SEQ: return 0x2;
1231 case TGSI_OPCODE_SGT: return 0x4;
1232 case TGSI_OPCODE_SLE: return 0x3;
1233 case TGSI_OPCODE_SNE: return 0xd;
1234 default:
1235 assert(0);
1236 return 0;
1237 }
1238 }
1239
1240 static INLINE void
1241 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1242 {
1243 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1244 }
1245
1246 static void
1247 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1248 struct nv50_reg *v, struct nv50_reg *e)
1249 {
1250 struct nv50_reg *temp = alloc_temp(pc, NULL);
1251
1252 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1253 emit_mul(pc, temp, temp, e);
1254 emit_preex2(pc, temp, temp);
1255 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1256
1257 free_temp(pc, temp);
1258 }
1259
1260 static INLINE void
1261 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1262 {
1263 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1264 }
1265
1266 static INLINE void
1267 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1268 {
1269 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1270 }
1271
1272 static void
1273 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1274 struct nv50_reg **src)
1275 {
1276 struct nv50_reg *one = alloc_immd(pc, 1.0);
1277 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1278 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1279 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1280 struct nv50_reg *tmp[4];
1281 boolean allow32 = pc->allow32;
1282
1283 pc->allow32 = FALSE;
1284
1285 if (mask & (3 << 1)) {
1286 tmp[0] = alloc_temp(pc, NULL);
1287 emit_minmax(pc, 4, tmp[0], src[0], zero);
1288 }
1289
1290 if (mask & (1 << 2)) {
1291 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1292
1293 tmp[1] = temp_temp(pc);
1294 emit_minmax(pc, 4, tmp[1], src[1], zero);
1295
1296 tmp[3] = temp_temp(pc);
1297 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1298 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1299
1300 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1301 emit_mov(pc, dst[2], zero);
1302 set_pred(pc, 3, 0, pc->p->exec_tail);
1303 }
1304
1305 if (mask & (1 << 1))
1306 assimilate_temp(pc, dst[1], tmp[0]);
1307 else
1308 if (mask & (1 << 2))
1309 free_temp(pc, tmp[0]);
1310
1311 pc->allow32 = allow32;
1312
1313 /* do this last, in case src[i,j] == dst[0,3] */
1314 if (mask & (1 << 0))
1315 emit_mov(pc, dst[0], one);
1316
1317 if (mask & (1 << 3))
1318 emit_mov(pc, dst[3], one);
1319
1320 FREE(pos128);
1321 FREE(neg128);
1322 FREE(zero);
1323 FREE(one);
1324 }
1325
1326 static INLINE void
1327 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1328 {
1329 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1330 }
1331
1332 static void
1333 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1334 {
1335 struct nv50_program_exec *e;
1336 const int r_pred = 1;
1337
1338 e = exec(pc);
1339 e->inst[0] = 0x00000002; /* discard */
1340 set_long(pc, e); /* sets cond code to ALWAYS */
1341
1342 if (src) {
1343 unsigned cvn = CVT_F32_F32;
1344
1345 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1346
1347 if (src->mod & NV50_MOD_NEG)
1348 cvn |= CVT_NEG;
1349 /* write predicate reg */
1350 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1351 }
1352
1353 emit(pc, e);
1354 }
1355
1356 static struct nv50_program_exec *
1357 emit_breakaddr(struct nv50_pc *pc)
1358 {
1359 struct nv50_program_exec *e = exec(pc);
1360
1361 e->inst[0] = 0x40000002;
1362 set_long(pc, e);
1363
1364 emit(pc, e);
1365 return e;
1366 }
1367
1368 static void
1369 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1370 {
1371 struct nv50_program_exec *e = exec(pc);
1372
1373 e->inst[0] = 0x50000002;
1374 set_long(pc, e);
1375 if (pred >= 0)
1376 set_pred(pc, cc, pred, e);
1377
1378 emit(pc, e);
1379 }
1380
1381 static struct nv50_program_exec *
1382 emit_joinat(struct nv50_pc *pc)
1383 {
1384 struct nv50_program_exec *e = exec(pc);
1385
1386 e->inst[0] = 0xa0000002;
1387 set_long(pc, e);
1388
1389 emit(pc, e);
1390 return e;
1391 }
1392
1393 static struct nv50_program_exec *
1394 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1395 {
1396 struct nv50_program_exec *e = exec(pc);
1397
1398 e->inst[0] = 0x10000002;
1399 set_long(pc, e);
1400 if (pred >= 0)
1401 set_pred(pc, cc, pred, e);
1402 emit(pc, e);
1403 return pc->p->exec_tail;
1404 }
1405
1406 static void
1407 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1408 {
1409 struct nv50_program_exec *e = exec(pc);
1410
1411 e->inst[0] = 0x30000002;
1412 set_long(pc, e);
1413 if (pred >= 0)
1414 set_pred(pc, cc, pred, e);
1415
1416 emit(pc, e);
1417 }
1418
1419 #define QOP_ADD 0
1420 #define QOP_SUBR 1
1421 #define QOP_SUB 2
1422 #define QOP_MOV_SRC1 3
1423
1424 /* For a quad of threads / top left, top right, bottom left, bottom right
1425 * pixels, do a different operation, and take src0 from a specific thread.
1426 */
1427 static void
1428 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1429 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1430 {
1431 struct nv50_program_exec *e = exec(pc);
1432
1433 e->inst[0] = 0xc0000000;
1434 e->inst[1] = 0x80000000;
1435 set_long(pc, e);
1436 e->inst[0] |= lane_src0 << 16;
1437 set_src_0(pc, src0, e);
1438 set_src_2(pc, src1, e);
1439
1440 if (wp >= 0)
1441 set_pred_wr(pc, 1, wp, e);
1442
1443 if (dst)
1444 set_dst(pc, dst, e);
1445 else {
1446 e->inst[0] |= 0x000001fc;
1447 e->inst[1] |= 0x00000008;
1448 }
1449
1450 e->inst[0] |= (qop & 3) << 20;
1451 e->inst[1] |= (qop >> 2) << 22;
1452
1453 emit(pc, e);
1454 }
1455
1456 static void
1457 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1458 struct nv50_reg **src, unsigned arg, boolean proj)
1459 {
1460 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1461
1462 src[0]->mod |= NV50_MOD_ABS;
1463 src[1]->mod |= NV50_MOD_ABS;
1464 src[2]->mod |= NV50_MOD_ABS;
1465
1466 emit_minmax(pc, 4, t[2], src[0], src[1]);
1467 emit_minmax(pc, 4, t[2], src[2], t[2]);
1468
1469 src[0]->mod = mod[0];
1470 src[1]->mod = mod[1];
1471 src[2]->mod = mod[2];
1472
1473 if (proj && 0 /* looks more correct without this */)
1474 emit_mul(pc, t[2], t[2], src[3]);
1475 else
1476 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1477 emit_mov(pc, t[3], src[3]);
1478
1479 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1480
1481 emit_mul(pc, t[0], src[0], t[2]);
1482 emit_mul(pc, t[1], src[1], t[2]);
1483 emit_mul(pc, t[2], src[2], t[2]);
1484 }
1485
1486 static void
1487 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1488 struct nv50_reg **src, unsigned dim, unsigned arg)
1489 {
1490 unsigned c, mode;
1491
1492 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1493 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1494
1495 t[3]->rhw = src[3]->rhw;
1496 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1497 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1498
1499 for (c = 0; c < dim; ++c) {
1500 t[c]->rhw = src[c]->rhw;
1501 emit_interp(pc, t[c], t[3], mode);
1502 }
1503 if (arg != dim) { /* depth reference value */
1504 t[dim]->rhw = src[2]->rhw;
1505 emit_interp(pc, t[dim], t[3], mode);
1506 }
1507 } else {
1508 /* XXX: for some reason the blob sometimes uses MAD
1509 * (mad f32 $rX $rY $rZ neg $r63)
1510 */
1511 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1512 for (c = 0; c < dim; ++c)
1513 emit_mul(pc, t[c], src[c], t[3]);
1514 if (arg != dim) /* depth reference value */
1515 emit_mul(pc, t[dim], src[2], t[3]);
1516 }
1517 }
1518
1519 static INLINE void
1520 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1521 {
1522 switch (type) {
1523 case TGSI_TEXTURE_1D:
1524 *arg = *dim = 1;
1525 break;
1526 case TGSI_TEXTURE_SHADOW1D:
1527 *dim = 1;
1528 *arg = 2;
1529 break;
1530 case TGSI_TEXTURE_UNKNOWN:
1531 case TGSI_TEXTURE_2D:
1532 case TGSI_TEXTURE_RECT:
1533 *arg = *dim = 2;
1534 break;
1535 case TGSI_TEXTURE_SHADOW2D:
1536 case TGSI_TEXTURE_SHADOWRECT:
1537 *dim = 2;
1538 *arg = 3;
1539 break;
1540 case TGSI_TEXTURE_3D:
1541 case TGSI_TEXTURE_CUBE:
1542 *dim = *arg = 3;
1543 break;
1544 default:
1545 assert(0);
1546 break;
1547 }
1548 }
1549
1550 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1551 * different LOD values, so branch off groups of equal LOD.
1552 */
1553 static void
1554 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1555 struct nv50_reg *src, struct nv50_program_exec *tex)
1556 {
1557 struct nv50_program_exec *join_at;
1558 unsigned i, target = pc->p->exec_size + 7 * 2;
1559
1560 /* Subtract lod of each pixel from lod of top left pixel, jump
1561 * texlod insn if result is 0, then repeat for 2 other pixels.
1562 */
1563 join_at = emit_joinat(pc);
1564 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1565 emit_branch(pc, 0, 2)->param.index = target;
1566
1567 for (i = 1; i < 4; ++i) {
1568 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1569 emit_branch(pc, 0, 2)->param.index = target;
1570 }
1571
1572 emit_mov(pc, tlod, src); /* target */
1573 emit(pc, tex); /* texlod */
1574
1575 join_at->param.index = target + 2 * 2;
1576 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1577 }
1578
1579 static void
1580 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1581 struct nv50_program_exec *tex)
1582 {
1583 struct nv50_program_exec *e;
1584 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1585 int r_pred = 0;
1586 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1587
1588 pc->allow32 = FALSE;
1589 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1590
1591 /* Subtract bias value of thread i from bias values of each thread,
1592 * store result in r_pred, and set bit i in r_bits if result was 0.
1593 */
1594 assert(arg < 4);
1595 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1596 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1597 emit_mov(pc, r_bits, &imm_1248);
1598 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1599 }
1600 emit_mov_to_pred(pc, r_pred, r_bits);
1601
1602 /* The lanes of a quad are now grouped by the bit in r_pred they have
1603 * set. Put the input values for TEX into a new register set for each
1604 * group and execute TEX only for a specific group.
1605 * We cannot use the same register set for each group because we need
1606 * the derivatives, which are implicitly calculated, to be correct.
1607 */
1608 for (i = 1; i < 4; ++i) {
1609 alloc_temp4(pc, t123[i], 0);
1610
1611 for (c = 0; c <= arg; ++c)
1612 emit_mov(pc, t123[i][c], t[c]);
1613
1614 *(e = exec(pc)) = *(tex);
1615 e->inst[0] &= ~0x01fc;
1616 set_dst(pc, t123[i][0], e);
1617 set_pred(pc, cc[i], r_pred, e);
1618 emit(pc, e);
1619 }
1620 /* finally TEX on the original regs (where we kept the input) */
1621 set_pred(pc, cc[0], r_pred, tex);
1622 emit(pc, tex);
1623
1624 /* put the 3 * n other results into regs for lane 0 */
1625 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1626 for (i = 1; i < 4; ++i) {
1627 for (c = 0; c < n; ++c) {
1628 emit_mov(pc, t[c], t123[i][c]);
1629 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1630 }
1631 free_temp4(pc, t123[i]);
1632 }
1633
1634 emit_nop(pc);
1635 free_temp(pc, r_bits);
1636 }
1637
1638 static void
1639 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1640 struct nv50_reg **src, unsigned unit, unsigned type,
1641 boolean proj, int bias_lod)
1642 {
1643 struct nv50_reg *t[4];
1644 struct nv50_program_exec *e;
1645 unsigned c, dim, arg;
1646
1647 /* t[i] must be within a single 128 bit super-reg */
1648 alloc_temp4(pc, t, 0);
1649
1650 e = exec(pc);
1651 e->inst[0] = 0xf0000000;
1652 set_long(pc, e);
1653 set_dst(pc, t[0], e);
1654
1655 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1656 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1657
1658 /* live flag (don't set if TEX results affect input to another TEX): */
1659 /* e->inst[0] |= 0x00000004; */
1660
1661 get_tex_dim(type, &dim, &arg);
1662
1663 if (type == TGSI_TEXTURE_CUBE) {
1664 e->inst[0] |= 0x08000000;
1665 load_cube_tex_coords(pc, t, src, arg, proj);
1666 } else
1667 if (proj)
1668 load_proj_tex_coords(pc, t, src, dim, arg);
1669 else {
1670 for (c = 0; c < dim; c++)
1671 emit_mov(pc, t[c], src[c]);
1672 if (arg != dim) /* depth reference value (always src.z here) */
1673 emit_mov(pc, t[dim], src[2]);
1674 }
1675
1676 e->inst[0] |= (mask & 0x3) << 25;
1677 e->inst[1] |= (mask & 0xc) << 12;
1678
1679 if (!bias_lod) {
1680 e->inst[0] |= (arg - 1) << 22;
1681 emit(pc, e);
1682 } else
1683 if (bias_lod < 0) {
1684 e->inst[0] |= arg << 22;
1685 e->inst[1] |= 0x20000000; /* texbias */
1686 emit_mov(pc, t[arg], src[3]);
1687 emit_texbias_sequence(pc, t, arg, e);
1688 } else {
1689 e->inst[0] |= arg << 22;
1690 e->inst[1] |= 0x40000000; /* texlod */
1691 emit_mov(pc, t[arg], src[3]);
1692 emit_texlod_sequence(pc, t[arg], src[3], e);
1693 }
1694
1695 #if 1
1696 c = 0;
1697 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1698 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1699 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1700 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1701
1702 free_temp4(pc, t);
1703 #else
1704 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1705 * the texture coordinates, not the fetched values: latency ? */
1706
1707 for (c = 0; c < 4; c++) {
1708 if (mask & (1 << c))
1709 assimilate_temp(pc, dst[c], t[c]);
1710 else
1711 free_temp(pc, t[c]);
1712 }
1713 #endif
1714 }
1715
1716 static void
1717 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1718 {
1719 struct nv50_program_exec *e = exec(pc);
1720
1721 assert(src->type == P_TEMP);
1722
1723 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1724 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1725 set_long(pc, e);
1726 set_dst(pc, dst, e);
1727 set_src_0(pc, src, e);
1728 set_src_2(pc, src, e);
1729
1730 emit(pc, e);
1731 }
1732
1733 static void
1734 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1735 {
1736 struct nv50_program_exec *e = exec(pc);
1737
1738 assert(src->type == P_TEMP);
1739
1740 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1741 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1742 set_long(pc, e);
1743 set_dst(pc, dst, e);
1744 set_src_0(pc, src, e);
1745 set_src_2(pc, src, e);
1746
1747 emit(pc, e);
1748 }
1749
1750 static void
1751 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1752 {
1753 unsigned q = 0, m = ~0;
1754
1755 assert(!is_long(e));
1756
1757 switch (e->inst[0] >> 28) {
1758 case 0x1:
1759 /* MOV */
1760 q = 0x0403c000;
1761 m = 0xffff7fff;
1762 break;
1763 case 0x8:
1764 /* INTERP (move centroid, perspective and flat bits) */
1765 m = ~0x03000100;
1766 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1767 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1768 break;
1769 case 0x9:
1770 /* RCP */
1771 break;
1772 case 0xB:
1773 /* ADD */
1774 m = ~(127 << 16);
1775 q = ((e->inst[0] & (~m)) >> 2);
1776 break;
1777 case 0xC:
1778 /* MUL */
1779 m = ~0x00008000;
1780 q = ((e->inst[0] & (~m)) << 12);
1781 break;
1782 case 0xE:
1783 /* MAD (if src2 == dst) */
1784 q = ((e->inst[0] & 0x1fc) << 12);
1785 break;
1786 default:
1787 assert(0);
1788 break;
1789 }
1790
1791 set_long(pc, e);
1792 pc->p->exec_size++;
1793
1794 e->inst[0] &= m;
1795 e->inst[1] |= q;
1796 }
1797
1798 /* Some operations support an optional negation flag. */
1799 static boolean
1800 negate_supported(const struct tgsi_full_instruction *insn, int i)
1801 {
1802 switch (insn->Instruction.Opcode) {
1803 case TGSI_OPCODE_ADD:
1804 case TGSI_OPCODE_COS:
1805 case TGSI_OPCODE_DDX:
1806 case TGSI_OPCODE_DDY:
1807 case TGSI_OPCODE_DP3:
1808 case TGSI_OPCODE_DP4:
1809 case TGSI_OPCODE_EX2:
1810 case TGSI_OPCODE_KIL:
1811 case TGSI_OPCODE_LG2:
1812 case TGSI_OPCODE_MAD:
1813 case TGSI_OPCODE_MUL:
1814 case TGSI_OPCODE_POW:
1815 case TGSI_OPCODE_RCP:
1816 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
1817 case TGSI_OPCODE_SCS:
1818 case TGSI_OPCODE_SIN:
1819 case TGSI_OPCODE_SUB:
1820 return TRUE;
1821 default:
1822 return FALSE;
1823 }
1824 }
1825
1826 /* Return a read mask for source registers deduced from opcode & write mask. */
1827 static unsigned
1828 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1829 {
1830 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1831
1832 switch (insn->Instruction.Opcode) {
1833 case TGSI_OPCODE_COS:
1834 case TGSI_OPCODE_SIN:
1835 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1836 case TGSI_OPCODE_DP3:
1837 return 0x7;
1838 case TGSI_OPCODE_DP4:
1839 case TGSI_OPCODE_DPH:
1840 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1841 return 0xf;
1842 case TGSI_OPCODE_DST:
1843 return mask & (c ? 0xa : 0x6);
1844 case TGSI_OPCODE_EX2:
1845 case TGSI_OPCODE_LG2:
1846 case TGSI_OPCODE_POW:
1847 case TGSI_OPCODE_RCP:
1848 case TGSI_OPCODE_RSQ:
1849 case TGSI_OPCODE_SCS:
1850 return 0x1;
1851 case TGSI_OPCODE_IF:
1852 return 0x1;
1853 case TGSI_OPCODE_LIT:
1854 return 0xb;
1855 case TGSI_OPCODE_TEX:
1856 case TGSI_OPCODE_TXB:
1857 case TGSI_OPCODE_TXL:
1858 case TGSI_OPCODE_TXP:
1859 {
1860 const struct tgsi_instruction_texture *tex;
1861
1862 assert(insn->Instruction.Texture);
1863 tex = &insn->Texture;
1864
1865 mask = 0x7;
1866 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1867 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1868 mask |= 0x8; /* bias, lod or proj */
1869
1870 switch (tex->Texture) {
1871 case TGSI_TEXTURE_1D:
1872 mask &= 0x9;
1873 break;
1874 case TGSI_TEXTURE_SHADOW1D:
1875 mask &= 0x5;
1876 break;
1877 case TGSI_TEXTURE_2D:
1878 mask &= 0xb;
1879 break;
1880 default:
1881 break;
1882 }
1883 }
1884 return mask;
1885 case TGSI_OPCODE_XPD:
1886 x = 0;
1887 if (mask & 1) x |= 0x6;
1888 if (mask & 2) x |= 0x5;
1889 if (mask & 4) x |= 0x3;
1890 return x;
1891 default:
1892 break;
1893 }
1894
1895 return mask;
1896 }
1897
1898 static struct nv50_reg *
1899 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1900 {
1901 switch (dst->Register.File) {
1902 case TGSI_FILE_TEMPORARY:
1903 return &pc->temp[dst->Register.Index * 4 + c];
1904 case TGSI_FILE_OUTPUT:
1905 return &pc->result[dst->Register.Index * 4 + c];
1906 case TGSI_FILE_ADDRESS:
1907 {
1908 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1909 if (!r) {
1910 r = alloc_addr(pc, NULL);
1911 pc->addr[dst->Register.Index * 4 + c] = r;
1912 }
1913 assert(r);
1914 return r;
1915 }
1916 case TGSI_FILE_NULL:
1917 return NULL;
1918 default:
1919 break;
1920 }
1921
1922 return NULL;
1923 }
1924
1925 static struct nv50_reg *
1926 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1927 boolean neg)
1928 {
1929 struct nv50_reg *r = NULL;
1930 struct nv50_reg *temp;
1931 unsigned sgn, c, swz;
1932
1933 if (src->Register.File != TGSI_FILE_CONSTANT)
1934 assert(!src->Register.Indirect);
1935
1936 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1937
1938 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1939 switch (c) {
1940 case TGSI_SWIZZLE_X:
1941 case TGSI_SWIZZLE_Y:
1942 case TGSI_SWIZZLE_Z:
1943 case TGSI_SWIZZLE_W:
1944 switch (src->Register.File) {
1945 case TGSI_FILE_INPUT:
1946 r = &pc->attr[src->Register.Index * 4 + c];
1947 break;
1948 case TGSI_FILE_TEMPORARY:
1949 r = &pc->temp[src->Register.Index * 4 + c];
1950 break;
1951 case TGSI_FILE_CONSTANT:
1952 if (!src->Register.Indirect) {
1953 r = &pc->param[src->Register.Index * 4 + c];
1954 break;
1955 }
1956 /* Indicate indirection by setting r->acc < 0 and
1957 * use the index field to select the address reg.
1958 */
1959 r = reg_instance(pc, NULL);
1960 swz = tgsi_util_get_src_register_swizzle(
1961 &src->Indirect, 0);
1962 ctor_reg(r, P_CONST,
1963 src->Indirect.Index * 4 + swz,
1964 src->Register.Index * 4 + c);
1965 r->acc = -1;
1966 break;
1967 case TGSI_FILE_IMMEDIATE:
1968 r = &pc->immd[src->Register.Index * 4 + c];
1969 break;
1970 case TGSI_FILE_SAMPLER:
1971 break;
1972 case TGSI_FILE_ADDRESS:
1973 r = pc->addr[src->Register.Index * 4 + c];
1974 assert(r);
1975 break;
1976 default:
1977 assert(0);
1978 break;
1979 }
1980 break;
1981 default:
1982 assert(0);
1983 break;
1984 }
1985
1986 switch (sgn) {
1987 case TGSI_UTIL_SIGN_KEEP:
1988 break;
1989 case TGSI_UTIL_SIGN_CLEAR:
1990 temp = temp_temp(pc);
1991 emit_abs(pc, temp, r);
1992 r = temp;
1993 break;
1994 case TGSI_UTIL_SIGN_TOGGLE:
1995 if (neg)
1996 r->mod = NV50_MOD_NEG;
1997 else {
1998 temp = temp_temp(pc);
1999 emit_neg(pc, temp, r);
2000 r = temp;
2001 }
2002 break;
2003 case TGSI_UTIL_SIGN_SET:
2004 temp = temp_temp(pc);
2005 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
2006 r = temp;
2007 break;
2008 default:
2009 assert(0);
2010 break;
2011 }
2012
2013 if (r && r->acc >= 0 && r != temp)
2014 return reg_instance(pc, r);
2015 return r;
2016 }
2017
2018 /* return TRUE for ops that produce only a single result */
2019 static boolean
2020 is_scalar_op(unsigned op)
2021 {
2022 switch (op) {
2023 case TGSI_OPCODE_COS:
2024 case TGSI_OPCODE_DP2:
2025 case TGSI_OPCODE_DP3:
2026 case TGSI_OPCODE_DP4:
2027 case TGSI_OPCODE_DPH:
2028 case TGSI_OPCODE_EX2:
2029 case TGSI_OPCODE_LG2:
2030 case TGSI_OPCODE_POW:
2031 case TGSI_OPCODE_RCP:
2032 case TGSI_OPCODE_RSQ:
2033 case TGSI_OPCODE_SIN:
2034 /*
2035 case TGSI_OPCODE_KIL:
2036 case TGSI_OPCODE_LIT:
2037 case TGSI_OPCODE_SCS:
2038 */
2039 return TRUE;
2040 default:
2041 return FALSE;
2042 }
2043 }
2044
2045 /* Returns a bitmask indicating which dst components depend
2046 * on source s, component c (reverse of nv50_tgsi_src_mask).
2047 */
2048 static unsigned
2049 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2050 {
2051 if (is_scalar_op(op))
2052 return 0x1;
2053
2054 switch (op) {
2055 case TGSI_OPCODE_DST:
2056 return (1 << c) & (s ? 0xa : 0x6);
2057 case TGSI_OPCODE_XPD:
2058 switch (c) {
2059 case 0: return 0x6;
2060 case 1: return 0x5;
2061 case 2: return 0x3;
2062 case 3: return 0x0;
2063 default:
2064 assert(0);
2065 return 0x0;
2066 }
2067 case TGSI_OPCODE_LIT:
2068 case TGSI_OPCODE_SCS:
2069 case TGSI_OPCODE_TEX:
2070 case TGSI_OPCODE_TXB:
2071 case TGSI_OPCODE_TXL:
2072 case TGSI_OPCODE_TXP:
2073 /* these take care of dangerous swizzles themselves */
2074 return 0x0;
2075 case TGSI_OPCODE_IF:
2076 case TGSI_OPCODE_KIL:
2077 /* don't call this function for these ops */
2078 assert(0);
2079 return 0;
2080 default:
2081 /* linear vector instruction */
2082 return (1 << c);
2083 }
2084 }
2085
2086 static INLINE boolean
2087 has_pred(struct nv50_program_exec *e, unsigned cc)
2088 {
2089 if (!is_long(e) || is_immd(e))
2090 return FALSE;
2091 return ((e->inst[1] & 0x780) == (cc << 7));
2092 }
2093
2094 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2095 * join_at ENDIF
2096 * @p0.eq bra ENDIF
2097 * single_op
2098 * ENDIF: nop.join
2099 */
2100 static boolean
2101 nv50_kill_branch(struct nv50_pc *pc)
2102 {
2103 int lvl = pc->if_lvl;
2104
2105 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2106 return FALSE;
2107
2108 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2109 * reg may no longer be valid, since we currently always use $p0
2110 */
2111 if (has_pred(pc->if_insn[lvl], 0xf))
2112 return FALSE;
2113 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2114
2115 /* We'll use the exec allocated for JOIN_AT (we can't easily
2116 * access nv50_program_exec's prev).
2117 */
2118 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2119
2120 *pc->if_join[lvl] = *pc->p->exec_tail;
2121
2122 FREE(pc->if_insn[lvl]);
2123 FREE(pc->p->exec_tail);
2124
2125 pc->p->exec_tail = pc->if_join[lvl];
2126 pc->p->exec_tail->next = NULL;
2127 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2128
2129 return TRUE;
2130 }
2131
2132 static void
2133 nv50_fp_move_results(struct nv50_pc *pc)
2134 {
2135 struct nv50_reg reg;
2136 unsigned i;
2137
2138 ctor_reg(&reg, P_TEMP, -1, -1);
2139
2140 for (i = 0; i < pc->result_nr * 4; ++i) {
2141 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2142 continue;
2143 if (pc->result[i].rhw != pc->result[i].hw) {
2144 reg.hw = pc->result[i].rhw;
2145 emit_mov(pc, &reg, &pc->result[i]);
2146 }
2147 }
2148 }
2149
2150 static boolean
2151 nv50_program_tx_insn(struct nv50_pc *pc,
2152 const struct tgsi_full_instruction *inst)
2153 {
2154 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2155 unsigned mask, sat, unit;
2156 int i, c;
2157
2158 mask = inst->Dst[0].Register.WriteMask;
2159 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2160
2161 memset(src, 0, sizeof(src));
2162
2163 for (c = 0; c < 4; c++) {
2164 if ((mask & (1 << c)) && !pc->r_dst[c])
2165 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2166 else
2167 dst[c] = pc->r_dst[c];
2168 rdst[c] = dst[c];
2169 }
2170
2171 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2172 const struct tgsi_full_src_register *fs = &inst->Src[i];
2173 unsigned src_mask;
2174 boolean neg_supp;
2175
2176 src_mask = nv50_tgsi_src_mask(inst, i);
2177 neg_supp = negate_supported(inst, i);
2178
2179 if (fs->Register.File == TGSI_FILE_SAMPLER)
2180 unit = fs->Register.Index;
2181
2182 for (c = 0; c < 4; c++)
2183 if (src_mask & (1 << c))
2184 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
2185 }
2186
2187 brdc = temp = pc->r_brdc;
2188 if (brdc && brdc->type != P_TEMP) {
2189 temp = temp_temp(pc);
2190 if (sat)
2191 brdc = temp;
2192 } else
2193 if (sat) {
2194 for (c = 0; c < 4; c++) {
2195 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2196 continue;
2197 /* rdst[c] = dst[c]; */ /* done above */
2198 dst[c] = temp_temp(pc);
2199 }
2200 }
2201
2202 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2203
2204 switch (inst->Instruction.Opcode) {
2205 case TGSI_OPCODE_ABS:
2206 for (c = 0; c < 4; c++) {
2207 if (!(mask & (1 << c)))
2208 continue;
2209 emit_abs(pc, dst[c], src[0][c]);
2210 }
2211 break;
2212 case TGSI_OPCODE_ADD:
2213 for (c = 0; c < 4; c++) {
2214 if (!(mask & (1 << c)))
2215 continue;
2216 emit_add(pc, dst[c], src[0][c], src[1][c]);
2217 }
2218 break;
2219 case TGSI_OPCODE_AND:
2220 case TGSI_OPCODE_XOR:
2221 case TGSI_OPCODE_OR:
2222 for (c = 0; c < 4; c++) {
2223 if (!(mask & (1 << c)))
2224 continue;
2225 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2226 inst->Instruction.Opcode);
2227 }
2228 break;
2229 case TGSI_OPCODE_ARL:
2230 assert(src[0][0]);
2231 temp = temp_temp(pc);
2232 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2233 emit_arl(pc, dst[0], temp, 4);
2234 break;
2235 case TGSI_OPCODE_BGNLOOP:
2236 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2237 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2238 terminate_mbb(pc);
2239 break;
2240 case TGSI_OPCODE_BRK:
2241 assert(pc->loop_lvl > 0);
2242 emit_break(pc, -1, 0);
2243 break;
2244 case TGSI_OPCODE_CEIL:
2245 for (c = 0; c < 4; c++) {
2246 if (!(mask & (1 << c)))
2247 continue;
2248 emit_cvt(pc, dst[c], src[0][c], -1,
2249 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2250 }
2251 break;
2252 case TGSI_OPCODE_CMP:
2253 pc->allow32 = FALSE;
2254 for (c = 0; c < 4; c++) {
2255 if (!(mask & (1 << c)))
2256 continue;
2257 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2258 emit_mov(pc, dst[c], src[1][c]);
2259 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2260 emit_mov(pc, dst[c], src[2][c]);
2261 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2262 }
2263 break;
2264 case TGSI_OPCODE_CONT:
2265 assert(pc->loop_lvl > 0);
2266 emit_branch(pc, -1, 0)->param.index =
2267 pc->loop_pos[pc->loop_lvl - 1];
2268 break;
2269 case TGSI_OPCODE_COS:
2270 if (mask & 8) {
2271 emit_precossin(pc, temp, src[0][3]);
2272 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2273 if (!(mask &= 7))
2274 break;
2275 if (temp == dst[3])
2276 temp = brdc = temp_temp(pc);
2277 }
2278 emit_precossin(pc, temp, src[0][0]);
2279 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2280 break;
2281 case TGSI_OPCODE_DDX:
2282 for (c = 0; c < 4; c++) {
2283 if (!(mask & (1 << c)))
2284 continue;
2285 emit_ddx(pc, dst[c], src[0][c]);
2286 }
2287 break;
2288 case TGSI_OPCODE_DDY:
2289 for (c = 0; c < 4; c++) {
2290 if (!(mask & (1 << c)))
2291 continue;
2292 emit_ddy(pc, dst[c], src[0][c]);
2293 }
2294 break;
2295 case TGSI_OPCODE_DP3:
2296 emit_mul(pc, temp, src[0][0], src[1][0]);
2297 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2298 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2299 break;
2300 case TGSI_OPCODE_DP4:
2301 emit_mul(pc, temp, src[0][0], src[1][0]);
2302 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2303 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2304 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2305 break;
2306 case TGSI_OPCODE_DPH:
2307 emit_mul(pc, temp, src[0][0], src[1][0]);
2308 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2309 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2310 emit_add(pc, brdc, src[1][3], temp);
2311 break;
2312 case TGSI_OPCODE_DST:
2313 if (mask & (1 << 1))
2314 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2315 if (mask & (1 << 2))
2316 emit_mov(pc, dst[2], src[0][2]);
2317 if (mask & (1 << 3))
2318 emit_mov(pc, dst[3], src[1][3]);
2319 if (mask & (1 << 0))
2320 emit_mov_immdval(pc, dst[0], 1.0f);
2321 break;
2322 case TGSI_OPCODE_ELSE:
2323 emit_branch(pc, -1, 0);
2324 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2325 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2326 terminate_mbb(pc);
2327 break;
2328 case TGSI_OPCODE_ENDIF:
2329 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2330
2331 /* try to replace branch over 1 insn with a predicated insn */
2332 if (nv50_kill_branch(pc) == TRUE)
2333 break;
2334
2335 if (pc->if_join[pc->if_lvl]) {
2336 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2337 pc->if_join[pc->if_lvl] = NULL;
2338 }
2339 terminate_mbb(pc);
2340 /* emit a NOP as join point, we could set it on the next
2341 * one, but would have to make sure it is long and !immd
2342 */
2343 JOIN_ON(emit_nop(pc));
2344 break;
2345 case TGSI_OPCODE_ENDLOOP:
2346 emit_branch(pc, -1, 0)->param.index =
2347 pc->loop_pos[--pc->loop_lvl];
2348 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2349 terminate_mbb(pc);
2350 break;
2351 case TGSI_OPCODE_EX2:
2352 emit_preex2(pc, temp, src[0][0]);
2353 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2354 break;
2355 case TGSI_OPCODE_FLR:
2356 for (c = 0; c < 4; c++) {
2357 if (!(mask & (1 << c)))
2358 continue;
2359 emit_flr(pc, dst[c], src[0][c]);
2360 }
2361 break;
2362 case TGSI_OPCODE_FRC:
2363 temp = temp_temp(pc);
2364 for (c = 0; c < 4; c++) {
2365 if (!(mask & (1 << c)))
2366 continue;
2367 emit_flr(pc, temp, src[0][c]);
2368 emit_sub(pc, dst[c], src[0][c], temp);
2369 }
2370 break;
2371 case TGSI_OPCODE_IF:
2372 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2373 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2374 CVT_F32_F32);
2375 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2376 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2377 terminate_mbb(pc);
2378 break;
2379 case TGSI_OPCODE_KIL:
2380 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2381 emit_kil(pc, src[0][0]);
2382 emit_kil(pc, src[0][1]);
2383 emit_kil(pc, src[0][2]);
2384 emit_kil(pc, src[0][3]);
2385 break;
2386 case TGSI_OPCODE_KILP:
2387 emit_kil(pc, NULL);
2388 break;
2389 case TGSI_OPCODE_LIT:
2390 emit_lit(pc, &dst[0], mask, &src[0][0]);
2391 break;
2392 case TGSI_OPCODE_LG2:
2393 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2394 break;
2395 case TGSI_OPCODE_LRP:
2396 temp = temp_temp(pc);
2397 for (c = 0; c < 4; c++) {
2398 if (!(mask & (1 << c)))
2399 continue;
2400 emit_sub(pc, temp, src[1][c], src[2][c]);
2401 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2402 }
2403 break;
2404 case TGSI_OPCODE_MAD:
2405 for (c = 0; c < 4; c++) {
2406 if (!(mask & (1 << c)))
2407 continue;
2408 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2409 }
2410 break;
2411 case TGSI_OPCODE_MAX:
2412 for (c = 0; c < 4; c++) {
2413 if (!(mask & (1 << c)))
2414 continue;
2415 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2416 }
2417 break;
2418 case TGSI_OPCODE_MIN:
2419 for (c = 0; c < 4; c++) {
2420 if (!(mask & (1 << c)))
2421 continue;
2422 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2423 }
2424 break;
2425 case TGSI_OPCODE_MOV:
2426 for (c = 0; c < 4; c++) {
2427 if (!(mask & (1 << c)))
2428 continue;
2429 emit_mov(pc, dst[c], src[0][c]);
2430 }
2431 break;
2432 case TGSI_OPCODE_MUL:
2433 for (c = 0; c < 4; c++) {
2434 if (!(mask & (1 << c)))
2435 continue;
2436 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2437 }
2438 break;
2439 case TGSI_OPCODE_POW:
2440 emit_pow(pc, brdc, src[0][0], src[1][0]);
2441 break;
2442 case TGSI_OPCODE_RCP:
2443 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2444 break;
2445 case TGSI_OPCODE_RET:
2446 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2447 nv50_fp_move_results(pc);
2448 emit_ret(pc, -1, 0);
2449 break;
2450 case TGSI_OPCODE_RSQ:
2451 src[0][0]->mod |= NV50_MOD_ABS;
2452 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2453 break;
2454 case TGSI_OPCODE_SCS:
2455 temp = temp_temp(pc);
2456 if (mask & 3)
2457 emit_precossin(pc, temp, src[0][0]);
2458 if (mask & (1 << 0))
2459 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2460 if (mask & (1 << 1))
2461 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2462 if (mask & (1 << 2))
2463 emit_mov_immdval(pc, dst[2], 0.0);
2464 if (mask & (1 << 3))
2465 emit_mov_immdval(pc, dst[3], 1.0);
2466 break;
2467 case TGSI_OPCODE_SIN:
2468 if (mask & 8) {
2469 emit_precossin(pc, temp, src[0][3]);
2470 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2471 if (!(mask &= 7))
2472 break;
2473 if (temp == dst[3])
2474 temp = brdc = temp_temp(pc);
2475 }
2476 emit_precossin(pc, temp, src[0][0]);
2477 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2478 break;
2479 case TGSI_OPCODE_SLT:
2480 case TGSI_OPCODE_SGE:
2481 case TGSI_OPCODE_SEQ:
2482 case TGSI_OPCODE_SGT:
2483 case TGSI_OPCODE_SLE:
2484 case TGSI_OPCODE_SNE:
2485 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2486 for (c = 0; c < 4; c++) {
2487 if (!(mask & (1 << c)))
2488 continue;
2489 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2490 }
2491 break;
2492 case TGSI_OPCODE_SUB:
2493 for (c = 0; c < 4; c++) {
2494 if (!(mask & (1 << c)))
2495 continue;
2496 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2497 }
2498 break;
2499 case TGSI_OPCODE_TEX:
2500 emit_tex(pc, dst, mask, src[0], unit,
2501 inst->Texture.Texture, FALSE, 0);
2502 break;
2503 case TGSI_OPCODE_TXB:
2504 emit_tex(pc, dst, mask, src[0], unit,
2505 inst->Texture.Texture, FALSE, -1);
2506 break;
2507 case TGSI_OPCODE_TXL:
2508 emit_tex(pc, dst, mask, src[0], unit,
2509 inst->Texture.Texture, FALSE, 1);
2510 break;
2511 case TGSI_OPCODE_TXP:
2512 emit_tex(pc, dst, mask, src[0], unit,
2513 inst->Texture.Texture, TRUE, 0);
2514 break;
2515 case TGSI_OPCODE_TRUNC:
2516 for (c = 0; c < 4; c++) {
2517 if (!(mask & (1 << c)))
2518 continue;
2519 emit_cvt(pc, dst[c], src[0][c], -1,
2520 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2521 }
2522 break;
2523 case TGSI_OPCODE_XPD:
2524 temp = temp_temp(pc);
2525 if (mask & (1 << 0)) {
2526 emit_mul(pc, temp, src[0][2], src[1][1]);
2527 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2528 }
2529 if (mask & (1 << 1)) {
2530 emit_mul(pc, temp, src[0][0], src[1][2]);
2531 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2532 }
2533 if (mask & (1 << 2)) {
2534 emit_mul(pc, temp, src[0][1], src[1][0]);
2535 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2536 }
2537 if (mask & (1 << 3))
2538 emit_mov_immdval(pc, dst[3], 1.0);
2539 break;
2540 case TGSI_OPCODE_END:
2541 break;
2542 default:
2543 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2544 return FALSE;
2545 }
2546
2547 if (brdc) {
2548 if (sat)
2549 emit_sat(pc, brdc, brdc);
2550 for (c = 0; c < 4; c++)
2551 if ((mask & (1 << c)) && dst[c] != brdc)
2552 emit_mov(pc, dst[c], brdc);
2553 } else
2554 if (sat) {
2555 for (c = 0; c < 4; c++) {
2556 if (!(mask & (1 << c)))
2557 continue;
2558 /* In this case we saturate later, and dst[c] won't
2559 * be another temp_temp (and thus lost), since rdst
2560 * already is TEMP (see above). */
2561 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2562 continue;
2563 emit_sat(pc, rdst[c], dst[c]);
2564 }
2565 }
2566
2567 kill_temp_temp(pc);
2568 pc->reg_instance_nr = 0;
2569
2570 return TRUE;
2571 }
2572
2573 static void
2574 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2575 {
2576 struct nv50_reg *reg = NULL;
2577 const struct tgsi_full_src_register *src;
2578 const struct tgsi_dst_register *dst;
2579 unsigned i, c, k, mask;
2580
2581 dst = &insn->Dst[0].Register;
2582 mask = dst->WriteMask;
2583
2584 if (dst->File == TGSI_FILE_TEMPORARY)
2585 reg = pc->temp;
2586 else
2587 if (dst->File == TGSI_FILE_OUTPUT) {
2588 reg = pc->result;
2589
2590 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2591 dst->Index == pc->edgeflag_out &&
2592 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2593 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2594 }
2595
2596 if (reg) {
2597 for (c = 0; c < 4; c++) {
2598 if (!(mask & (1 << c)))
2599 continue;
2600 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2601 }
2602 }
2603
2604 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2605 src = &insn->Src[i];
2606
2607 if (src->Register.File == TGSI_FILE_TEMPORARY)
2608 reg = pc->temp;
2609 else
2610 if (src->Register.File == TGSI_FILE_INPUT)
2611 reg = pc->attr;
2612 else
2613 continue;
2614
2615 mask = nv50_tgsi_src_mask(insn, i);
2616
2617 for (c = 0; c < 4; c++) {
2618 if (!(mask & (1 << c)))
2619 continue;
2620 k = tgsi_util_get_full_src_register_swizzle(src, c);
2621
2622 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2623 }
2624 }
2625 }
2626
2627 /* Returns a bitmask indicating which dst components need to be
2628 * written to temporaries first to avoid 'corrupting' sources.
2629 *
2630 * m[i] (out) indicate component to write in the i-th position
2631 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2632 */
2633 static unsigned
2634 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2635 {
2636 unsigned i, c, x, unsafe;
2637
2638 for (c = 0; c < 4; c++)
2639 m[c] = c;
2640
2641 /* Swap as long as a dst component written earlier is depended on
2642 * by one written later, but the next one isn't depended on by it.
2643 */
2644 for (c = 0; c < 3; c++) {
2645 if (rdep[m[c + 1]] & (1 << m[c]))
2646 continue; /* if next one is depended on by us */
2647 for (i = c + 1; i < 4; i++)
2648 /* if we are depended on by a later one */
2649 if (rdep[m[c]] & (1 << m[i]))
2650 break;
2651 if (i == 4)
2652 continue;
2653 /* now, swap */
2654 x = m[c];
2655 m[c] = m[c + 1];
2656 m[c + 1] = x;
2657
2658 /* restart */
2659 c = 0;
2660 }
2661
2662 /* mark dependencies that could not be resolved by reordering */
2663 for (i = 0; i < 3; ++i)
2664 for (c = i + 1; c < 4; ++c)
2665 if (rdep[m[i]] & (1 << m[c]))
2666 unsafe |= (1 << i);
2667
2668 /* NOTE: $unsafe is with respect to order, not component */
2669 return unsafe;
2670 }
2671
2672 /* Select a suitable dst register for broadcasting scalar results,
2673 * or return NULL if we have to allocate an extra TEMP.
2674 *
2675 * If e.g. only 1 component is written, we may also emit the final
2676 * result to a write-only register.
2677 */
2678 static struct nv50_reg *
2679 tgsi_broadcast_dst(struct nv50_pc *pc,
2680 const struct tgsi_full_dst_register *fd, unsigned mask)
2681 {
2682 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2683 int c = ffs(~mask & fd->Register.WriteMask);
2684 if (c)
2685 return tgsi_dst(pc, c - 1, fd);
2686 } else {
2687 int c = ffs(fd->Register.WriteMask) - 1;
2688 if ((1 << c) == fd->Register.WriteMask)
2689 return tgsi_dst(pc, c, fd);
2690 }
2691
2692 return NULL;
2693 }
2694
2695 /* Scan source swizzles and return a bitmask indicating dst regs that
2696 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2697 */
2698 static unsigned
2699 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2700 unsigned rdep[4])
2701 {
2702 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2703 const struct tgsi_full_src_register *fs;
2704 unsigned i, deqs = 0;
2705
2706 for (i = 0; i < 4; ++i)
2707 rdep[i] = 0;
2708
2709 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2710 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2711 boolean neg_supp = negate_supported(insn, i);
2712
2713 fs = &insn->Src[i];
2714 if (fs->Register.File != fd->Register.File ||
2715 fs->Register.Index != fd->Register.Index)
2716 continue;
2717
2718 for (chn = 0; chn < 4; ++chn) {
2719 unsigned s, c;
2720
2721 if (!(mask & (1 << chn))) /* src is not read */
2722 continue;
2723 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2724 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2725
2726 if (!(fd->Register.WriteMask & (1 << c)))
2727 continue;
2728
2729 /* no danger if src is copied to TEMP first */
2730 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2731 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2732 continue;
2733
2734 rdep[c] |= nv50_tgsi_dst_revdep(
2735 insn->Instruction.Opcode, i, chn);
2736 deqs |= (1 << c);
2737 }
2738 }
2739
2740 return deqs;
2741 }
2742
2743 static boolean
2744 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2745 {
2746 struct tgsi_full_instruction insn = tok->FullInstruction;
2747 const struct tgsi_full_dst_register *fd;
2748 unsigned i, deqs, rdep[4], m[4];
2749
2750 fd = &tok->FullInstruction.Dst[0];
2751 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2752
2753 if (is_scalar_op(insn.Instruction.Opcode)) {
2754 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2755 if (!pc->r_brdc)
2756 pc->r_brdc = temp_temp(pc);
2757 return nv50_program_tx_insn(pc, &insn);
2758 }
2759 pc->r_brdc = NULL;
2760
2761 if (!deqs)
2762 return nv50_program_tx_insn(pc, &insn);
2763
2764 deqs = nv50_revdep_reorder(m, rdep);
2765
2766 for (i = 0; i < 4; ++i) {
2767 assert(pc->r_dst[m[i]] == NULL);
2768
2769 insn.Dst[0].Register.WriteMask =
2770 fd->Register.WriteMask & (1 << m[i]);
2771
2772 if (!insn.Dst[0].Register.WriteMask)
2773 continue;
2774
2775 if (deqs & (1 << i))
2776 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2777
2778 if (!nv50_program_tx_insn(pc, &insn))
2779 return FALSE;
2780 }
2781
2782 for (i = 0; i < 4; i++) {
2783 struct nv50_reg *reg = pc->r_dst[i];
2784 if (!reg)
2785 continue;
2786 pc->r_dst[i] = NULL;
2787
2788 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2789 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2790 else
2791 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2792 free_temp(pc, reg);
2793 }
2794
2795 return TRUE;
2796 }
2797
2798 static void
2799 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2800 {
2801 struct nv50_reg *iv, **ppiv;
2802 unsigned mode = pc->interp_mode[reg->index];
2803
2804 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2805 iv = *ppiv;
2806
2807 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2808 iv = *ppiv = alloc_temp(pc, NULL);
2809 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2810
2811 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2812 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
2813
2814 /* XXX: when loading interpolants dynamically, move these
2815 * to the program head, or make sure it can't be skipped.
2816 */
2817 }
2818
2819 emit_interp(pc, reg, iv, mode);
2820 }
2821
2822 /* The face input is always at v[255] (varying space), with a
2823 * value of 0 for back-facing, and 0xffffffff for front-facing.
2824 */
2825 static void
2826 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2827 {
2828 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2829
2830 assert(a->rhw == -1);
2831 alloc_reg(pc, a); /* do this before rhw is set */
2832 a->rhw = 255;
2833 load_interpolant(pc, a);
2834 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2835
2836 FREE(one);
2837 }
2838
2839 static boolean
2840 nv50_program_tx_prep(struct nv50_pc *pc)
2841 {
2842 struct tgsi_parse_context tp;
2843 struct nv50_program *p = pc->p;
2844 boolean ret = FALSE;
2845 unsigned i, c, flat_nr = 0;
2846
2847 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2848 while (!tgsi_parse_end_of_tokens(&tp)) {
2849 const union tgsi_full_token *tok = &tp.FullToken;
2850
2851 tgsi_parse_token(&tp);
2852 switch (tok->Token.Type) {
2853 case TGSI_TOKEN_TYPE_IMMEDIATE:
2854 {
2855 const struct tgsi_full_immediate *imm =
2856 &tp.FullToken.FullImmediate;
2857
2858 ctor_immd_4f32(pc, imm->u[0].Float,
2859 imm->u[1].Float,
2860 imm->u[2].Float,
2861 imm->u[3].Float);
2862 }
2863 break;
2864 case TGSI_TOKEN_TYPE_DECLARATION:
2865 {
2866 const struct tgsi_full_declaration *d;
2867 unsigned si, last, first, mode;
2868
2869 d = &tp.FullToken.FullDeclaration;
2870 first = d->Range.First;
2871 last = d->Range.Last;
2872
2873 switch (d->Declaration.File) {
2874 case TGSI_FILE_TEMPORARY:
2875 break;
2876 case TGSI_FILE_OUTPUT:
2877 if (!d->Declaration.Semantic ||
2878 p->type == PIPE_SHADER_FRAGMENT)
2879 break;
2880
2881 si = d->Semantic.Index;
2882 switch (d->Semantic.Name) {
2883 case TGSI_SEMANTIC_BCOLOR:
2884 p->cfg.two_side[si].hw = first;
2885 if (p->cfg.io_nr > first)
2886 p->cfg.io_nr = first;
2887 break;
2888 case TGSI_SEMANTIC_PSIZE:
2889 p->cfg.psiz = first;
2890 if (p->cfg.io_nr > first)
2891 p->cfg.io_nr = first;
2892 break;
2893 case TGSI_SEMANTIC_EDGEFLAG:
2894 pc->edgeflag_out = first;
2895 break;
2896 /*
2897 case TGSI_SEMANTIC_CLIP_DISTANCE:
2898 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2899 break;
2900 */
2901 default:
2902 break;
2903 }
2904 break;
2905 case TGSI_FILE_INPUT:
2906 {
2907 if (p->type != PIPE_SHADER_FRAGMENT)
2908 break;
2909
2910 switch (d->Declaration.Interpolate) {
2911 case TGSI_INTERPOLATE_CONSTANT:
2912 mode = INTERP_FLAT;
2913 flat_nr++;
2914 break;
2915 case TGSI_INTERPOLATE_PERSPECTIVE:
2916 mode = INTERP_PERSPECTIVE;
2917 p->cfg.regs[1] |= 0x08 << 24;
2918 break;
2919 default:
2920 mode = INTERP_LINEAR;
2921 break;
2922 }
2923 if (d->Declaration.Centroid)
2924 mode |= INTERP_CENTROID;
2925
2926 assert(last < 32);
2927 for (i = first; i <= last; i++)
2928 pc->interp_mode[i] = mode;
2929 }
2930 break;
2931 case TGSI_FILE_ADDRESS:
2932 case TGSI_FILE_CONSTANT:
2933 case TGSI_FILE_SAMPLER:
2934 break;
2935 default:
2936 NOUVEAU_ERR("bad decl file %d\n",
2937 d->Declaration.File);
2938 goto out_err;
2939 }
2940 }
2941 break;
2942 case TGSI_TOKEN_TYPE_INSTRUCTION:
2943 pc->insn_nr++;
2944 prep_inspect_insn(pc, &tok->FullInstruction);
2945 break;
2946 default:
2947 break;
2948 }
2949 }
2950
2951 if (p->type == PIPE_SHADER_VERTEX) {
2952 int rid = 0;
2953
2954 for (i = 0; i < pc->attr_nr * 4; ++i) {
2955 if (pc->attr[i].acc) {
2956 pc->attr[i].hw = rid++;
2957 p->cfg.attr[i / 32] |= 1 << (i % 32);
2958 }
2959 }
2960
2961 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2962 p->cfg.io[i].hw = rid;
2963 p->cfg.io[i].id = i;
2964
2965 for (c = 0; c < 4; ++c) {
2966 int n = i * 4 + c;
2967 if (!pc->result[n].acc)
2968 continue;
2969 pc->result[n].hw = rid++;
2970 p->cfg.io[i].mask |= 1 << c;
2971 }
2972 }
2973
2974 for (c = 0; c < 2; ++c)
2975 if (p->cfg.two_side[c].hw < 0x40)
2976 p->cfg.two_side[c] = p->cfg.io[
2977 p->cfg.two_side[c].hw];
2978
2979 if (p->cfg.psiz < 0x40)
2980 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2981 } else
2982 if (p->type == PIPE_SHADER_FRAGMENT) {
2983 int rid, aid;
2984 unsigned n = 0, m = pc->attr_nr - flat_nr;
2985
2986 pc->allow32 = TRUE;
2987
2988 int base = (TGSI_SEMANTIC_POSITION ==
2989 p->info.input_semantic_name[0]) ? 0 : 1;
2990
2991 /* non-flat interpolants have to be mapped to
2992 * the lower hardware IDs, so sort them:
2993 */
2994 for (i = 0; i < pc->attr_nr; i++) {
2995 if (pc->interp_mode[i] == INTERP_FLAT)
2996 p->cfg.io[m++].id = i;
2997 else {
2998 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2999 p->cfg.io[n].linear = TRUE;
3000 p->cfg.io[n++].id = i;
3001 }
3002 }
3003
3004 if (!base) /* set w-coordinate mask from perspective interp */
3005 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3006
3007 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3008 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3009
3010 for (n = 0; n < pc->attr_nr; ++n) {
3011 p->cfg.io[n].hw = rid = aid;
3012 i = p->cfg.io[n].id;
3013
3014 if (p->info.input_semantic_name[n] ==
3015 TGSI_SEMANTIC_FACE) {
3016 load_frontfacing(pc, &pc->attr[i * 4]);
3017 continue;
3018 }
3019
3020 for (c = 0; c < 4; ++c) {
3021 if (!pc->attr[i * 4 + c].acc)
3022 continue;
3023 pc->attr[i * 4 + c].rhw = rid++;
3024 p->cfg.io[n].mask |= 1 << c;
3025
3026 load_interpolant(pc, &pc->attr[i * 4 + c]);
3027 }
3028 aid += popcnt4(p->cfg.io[n].mask);
3029 }
3030
3031 if (!base)
3032 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3033
3034 m = popcnt4(p->cfg.regs[1] >> 24);
3035
3036 /* set count of non-position inputs and of non-flat
3037 * non-position inputs for FP_INTERPOLANT_CTRL
3038 */
3039 p->cfg.regs[1] |= aid - m;
3040
3041 if (flat_nr) {
3042 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3043 p->cfg.regs[1] |= (i - m) << 16;
3044 } else
3045 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3046
3047 /* mark color semantic for light-twoside */
3048 n = 0x40;
3049 for (i = 0; i < pc->attr_nr; i++) {
3050 ubyte si, sn;
3051
3052 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3053 si = p->info.input_semantic_index[p->cfg.io[i].id];
3054
3055 if (sn == TGSI_SEMANTIC_COLOR) {
3056 p->cfg.two_side[si] = p->cfg.io[i];
3057
3058 /* increase colour count */
3059 p->cfg.regs[0] += popcnt4(
3060 p->cfg.two_side[si].mask) << 16;
3061
3062 n = MIN2(n, p->cfg.io[i].hw - m);
3063 }
3064 }
3065 if (n < 0x40)
3066 p->cfg.regs[0] += n;
3067
3068 /* Initialize FP results:
3069 * FragDepth is always first TGSI and last hw output
3070 */
3071 i = p->info.writes_z ? 4 : 0;
3072 for (rid = 0; i < pc->result_nr * 4; i++)
3073 pc->result[i].rhw = rid++;
3074 if (p->info.writes_z)
3075 pc->result[2].rhw = rid;
3076
3077 p->cfg.high_result = rid;
3078
3079 /* separate/different colour results for MRTs ? */
3080 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3081 p->cfg.regs[2] |= 1;
3082 }
3083
3084 if (pc->immd_nr) {
3085 int rid = 0;
3086
3087 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3088 if (!pc->immd)
3089 goto out_err;
3090
3091 for (i = 0; i < pc->immd_nr; i++) {
3092 for (c = 0; c < 4; c++, rid++)
3093 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3094 }
3095 }
3096
3097 ret = TRUE;
3098 out_err:
3099 if (pc->iv_p)
3100 free_temp(pc, pc->iv_p);
3101 if (pc->iv_c)
3102 free_temp(pc, pc->iv_c);
3103
3104 tgsi_parse_free(&tp);
3105 return ret;
3106 }
3107
3108 static void
3109 free_nv50_pc(struct nv50_pc *pc)
3110 {
3111 if (pc->immd)
3112 FREE(pc->immd);
3113 if (pc->param)
3114 FREE(pc->param);
3115 if (pc->result)
3116 FREE(pc->result);
3117 if (pc->attr)
3118 FREE(pc->attr);
3119 if (pc->temp)
3120 FREE(pc->temp);
3121
3122 FREE(pc);
3123 }
3124
3125 static boolean
3126 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3127 {
3128 int i, c;
3129 unsigned rtype[2] = { P_ATTR, P_RESULT };
3130
3131 pc->p = p;
3132 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3133 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3134 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3135 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3136 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3137 assert(pc->addr_nr <= 2);
3138
3139 p->cfg.high_temp = 4;
3140
3141 p->cfg.two_side[0].hw = 0x40;
3142 p->cfg.two_side[1].hw = 0x40;
3143
3144 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3145
3146 switch (p->type) {
3147 case PIPE_SHADER_VERTEX:
3148 p->cfg.psiz = 0x40;
3149 p->cfg.clpd = 0x40;
3150 p->cfg.io_nr = pc->result_nr;
3151 break;
3152 case PIPE_SHADER_FRAGMENT:
3153 rtype[0] = rtype[1] = P_TEMP;
3154
3155 p->cfg.regs[0] = 0x01000004;
3156 p->cfg.io_nr = pc->attr_nr;
3157
3158 if (p->info.writes_z) {
3159 p->cfg.regs[2] |= 0x00000100;
3160 p->cfg.regs[3] |= 0x00000011;
3161 }
3162 if (p->info.uses_kill)
3163 p->cfg.regs[2] |= 0x00100000;
3164 break;
3165 }
3166
3167 if (pc->temp_nr) {
3168 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3169 if (!pc->temp)
3170 return FALSE;
3171
3172 for (i = 0; i < pc->temp_nr * 4; ++i)
3173 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3174 }
3175
3176 if (pc->attr_nr) {
3177 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3178 if (!pc->attr)
3179 return FALSE;
3180
3181 for (i = 0; i < pc->attr_nr * 4; ++i)
3182 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3183 }
3184
3185 if (pc->result_nr) {
3186 unsigned nr = pc->result_nr * 4;
3187
3188 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3189 if (!pc->result)
3190 return FALSE;
3191
3192 for (i = 0; i < nr; ++i)
3193 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3194 }
3195
3196 if (pc->param_nr) {
3197 int rid = 0;
3198
3199 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3200 if (!pc->param)
3201 return FALSE;
3202
3203 for (i = 0; i < pc->param_nr; ++i)
3204 for (c = 0; c < 4; ++c, ++rid)
3205 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3206 }
3207
3208 if (pc->addr_nr) {
3209 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3210 if (!pc->addr)
3211 return FALSE;
3212 }
3213 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3214 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3215
3216 return TRUE;
3217 }
3218
3219 static void
3220 nv50_program_fixup_insns(struct nv50_pc *pc)
3221 {
3222 struct nv50_program_exec *e, **bra_list;
3223 unsigned i, n, pos;
3224
3225 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3226
3227 /* Collect branch instructions, we need to adjust their offsets
3228 * when converting 32 bit instructions to 64 bit ones
3229 */
3230 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3231 if (e->param.index >= 0 && !e->param.mask)
3232 bra_list[n++] = e;
3233
3234 /* last instruction must be long so it can have the exit bit set */
3235 if (!is_long(pc->p->exec_tail))
3236 convert_to_long(pc, pc->p->exec_tail);
3237 /* set exit bit */
3238 pc->p->exec_tail->inst[1] |= 1;
3239
3240 /* !immd on exit insn simultaneously means !join */
3241 assert(!is_immd(pc->p->exec_head));
3242 assert(!is_immd(pc->p->exec_tail));
3243
3244 /* Make sure we don't have any single 32 bit instructions. */
3245 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3246 pos += is_long(e) ? 2 : 1;
3247
3248 if ((pos & 1) && (!e->next || is_long(e->next))) {
3249 for (i = 0; i < n; ++i)
3250 if (bra_list[i]->param.index >= pos)
3251 bra_list[i]->param.index += 1;
3252 convert_to_long(pc, e);
3253 ++pos;
3254 }
3255 }
3256
3257 FREE(bra_list);
3258 }
3259
3260 static boolean
3261 nv50_program_tx(struct nv50_program *p)
3262 {
3263 struct tgsi_parse_context parse;
3264 struct nv50_pc *pc;
3265 boolean ret;
3266
3267 pc = CALLOC_STRUCT(nv50_pc);
3268 if (!pc)
3269 return FALSE;
3270
3271 ret = ctor_nv50_pc(pc, p);
3272 if (ret == FALSE)
3273 goto out_cleanup;
3274
3275 ret = nv50_program_tx_prep(pc);
3276 if (ret == FALSE)
3277 goto out_cleanup;
3278
3279 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3280 while (!tgsi_parse_end_of_tokens(&parse)) {
3281 const union tgsi_full_token *tok = &parse.FullToken;
3282
3283 /* don't allow half insn/immd on first and last instruction */
3284 pc->allow32 = TRUE;
3285 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
3286 pc->allow32 = FALSE;
3287
3288 tgsi_parse_token(&parse);
3289
3290 switch (tok->Token.Type) {
3291 case TGSI_TOKEN_TYPE_INSTRUCTION:
3292 ++pc->insn_cur;
3293 ret = nv50_tgsi_insn(pc, tok);
3294 if (ret == FALSE)
3295 goto out_err;
3296 break;
3297 default:
3298 break;
3299 }
3300 }
3301
3302 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3303 nv50_fp_move_results(pc);
3304
3305 nv50_program_fixup_insns(pc);
3306
3307 p->param_nr = pc->param_nr * 4;
3308 p->immd_nr = pc->immd_nr * 4;
3309 p->immd = pc->immd_buf;
3310
3311 out_err:
3312 tgsi_parse_free(&parse);
3313
3314 out_cleanup:
3315 free_nv50_pc(pc);
3316 return ret;
3317 }
3318
3319 static void
3320 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3321 {
3322 if (nv50_program_tx(p) == FALSE)
3323 assert(0);
3324 p->translated = TRUE;
3325 }
3326
3327 static void
3328 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3329 unsigned start, unsigned count, unsigned cbuf)
3330 {
3331 struct nouveau_channel *chan = nv50->screen->base.channel;
3332 struct nouveau_grobj *tesla = nv50->screen->tesla;
3333
3334 while (count) {
3335 unsigned nr = count > 2047 ? 2047 : count;
3336
3337 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3338 OUT_RING (chan, (cbuf << 0) | (start << 8));
3339 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3340 OUT_RINGp (chan, map, nr);
3341
3342 map += nr;
3343 start += nr;
3344 count -= nr;
3345 }
3346 }
3347
3348 static void
3349 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3350 {
3351 struct pipe_screen *pscreen = nv50->pipe.screen;
3352
3353 if (!p->data[0] && p->immd_nr) {
3354 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3355
3356 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3357 while (heap->next && heap->size < p->immd_nr) {
3358 struct nv50_program *evict = heap->next->priv;
3359 nouveau_resource_free(&evict->data[0]);
3360 }
3361
3362 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3363 &p->data[0]))
3364 assert(0);
3365 }
3366
3367 /* immediates only need to be uploaded again when freed */
3368 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3369 p->immd_nr, NV50_CB_PMISC);
3370 }
3371
3372 assert(p->param_nr <= 512);
3373
3374 if (p->param_nr) {
3375 unsigned cb;
3376 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3377 PIPE_BUFFER_USAGE_CPU_READ);
3378
3379 if (p->type == PIPE_SHADER_VERTEX)
3380 cb = NV50_CB_PVP;
3381 else
3382 cb = NV50_CB_PFP;
3383
3384 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3385 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3386 }
3387 }
3388
3389 static void
3390 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3391 {
3392 struct nouveau_channel *chan = nv50->screen->base.channel;
3393 struct nv50_program_exec *e;
3394 uint32_t *up, i;
3395 boolean upload = FALSE;
3396
3397 if (!p->bo) {
3398 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3399 p->exec_size * 4, &p->bo);
3400 upload = TRUE;
3401 }
3402
3403 if (p->data[0] && p->data[0]->start != p->data_start[0])
3404 upload = TRUE;
3405
3406 if (!upload)
3407 return;
3408
3409 up = MALLOC(p->exec_size * 4);
3410
3411 for (i = 0, e = p->exec_head; e; e = e->next) {
3412 unsigned ei, ci, bs;
3413
3414 if (e->param.index >= 0 && e->param.mask) {
3415 bs = (e->inst[1] >> 22) & 0x07;
3416 assert(bs < 2);
3417 ei = e->param.shift >> 5;
3418 ci = e->param.index;
3419 if (bs == 0)
3420 ci += p->data[bs]->start;
3421
3422 e->inst[ei] &= ~e->param.mask;
3423 e->inst[ei] |= (ci << e->param.shift);
3424 } else
3425 if (e->param.index >= 0) {
3426 /* zero mask means param is a jump/branch offset */
3427 assert(!(e->param.index & 1));
3428 /* seem to be 8 byte steps */
3429 ei = (e->param.index >> 1) + 0 /* START_ID */;
3430
3431 e->inst[0] &= 0xf0000fff;
3432 e->inst[0] |= ei << 12;
3433 }
3434
3435 up[i++] = e->inst[0];
3436 if (is_long(e))
3437 up[i++] = e->inst[1];
3438 }
3439 assert(i == p->exec_size);
3440
3441 if (p->data[0])
3442 p->data_start[0] = p->data[0]->start;
3443
3444 #ifdef NV50_PROGRAM_DUMP
3445 NOUVEAU_ERR("-------\n");
3446 for (e = p->exec_head; e; e = e->next) {
3447 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3448 if (is_long(e))
3449 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3450 }
3451 #endif
3452 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3453 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3454 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3455 0, 0, p->exec_size * 4, 1, 1);
3456
3457 FREE(up);
3458 }
3459
3460 void
3461 nv50_vertprog_validate(struct nv50_context *nv50)
3462 {
3463 struct nouveau_grobj *tesla = nv50->screen->tesla;
3464 struct nv50_program *p = nv50->vertprog;
3465 struct nouveau_stateobj *so;
3466
3467 if (!p->translated) {
3468 nv50_program_validate(nv50, p);
3469 if (!p->translated)
3470 assert(0);
3471 }
3472
3473 nv50_program_validate_data(nv50, p);
3474 nv50_program_validate_code(nv50, p);
3475
3476 so = so_new(13, 2);
3477 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3478 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3479 NOUVEAU_BO_HIGH, 0, 0);
3480 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3481 NOUVEAU_BO_LOW, 0, 0);
3482 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3483 so_data (so, p->cfg.attr[0]);
3484 so_data (so, p->cfg.attr[1]);
3485 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3486 so_data (so, p->cfg.high_result);
3487 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3488 so_data (so, p->cfg.high_result); //8);
3489 so_data (so, p->cfg.high_temp);
3490 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3491 so_data (so, 0); /* program start offset */
3492 so_ref(so, &nv50->state.vertprog);
3493 so_ref(NULL, &so);
3494 }
3495
3496 void
3497 nv50_fragprog_validate(struct nv50_context *nv50)
3498 {
3499 struct nouveau_grobj *tesla = nv50->screen->tesla;
3500 struct nv50_program *p = nv50->fragprog;
3501 struct nouveau_stateobj *so;
3502
3503 if (!p->translated) {
3504 nv50_program_validate(nv50, p);
3505 if (!p->translated)
3506 assert(0);
3507 }
3508
3509 nv50_program_validate_data(nv50, p);
3510 nv50_program_validate_code(nv50, p);
3511
3512 so = so_new(64, 2);
3513 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3514 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3515 NOUVEAU_BO_HIGH, 0, 0);
3516 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3517 NOUVEAU_BO_LOW, 0, 0);
3518 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3519 so_data (so, p->cfg.high_temp);
3520 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3521 so_data (so, p->cfg.high_result);
3522 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3523 so_data (so, p->cfg.regs[2]);
3524 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3525 so_data (so, p->cfg.regs[3]);
3526 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3527 so_data (so, 0); /* program start offset */
3528 so_ref(so, &nv50->state.fragprog);
3529 so_ref(NULL, &so);
3530 }
3531
3532 static void
3533 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3534 {
3535 struct nv50_program *fp = nv50->fragprog;
3536 struct nv50_program *vp = nv50->vertprog;
3537 unsigned i, c, m = base;
3538
3539 /* XXX: this might not work correctly in all cases yet - we'll
3540 * just assume that an FP generic input that is not written in
3541 * the VP is PointCoord.
3542 */
3543 memset(pntc, 0, 8 * sizeof(uint32_t));
3544
3545 for (i = 0; i < fp->cfg.io_nr; i++) {
3546 uint8_t sn, si;
3547 uint8_t j, k = fp->cfg.io[i].id;
3548 unsigned n = popcnt4(fp->cfg.io[i].mask);
3549
3550 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3551 m += n;
3552 continue;
3553 }
3554
3555 for (j = 0; j < vp->info.num_outputs; ++j) {
3556 sn = vp->info.output_semantic_name[j];
3557 si = vp->info.output_semantic_index[j];
3558
3559 if (sn == fp->info.input_semantic_name[k] &&
3560 si == fp->info.input_semantic_index[k])
3561 break;
3562 }
3563
3564 if (j < vp->info.num_outputs) {
3565 ubyte mode =
3566 nv50->rasterizer->pipe.sprite_coord_mode[si];
3567
3568 if (mode == PIPE_SPRITE_COORD_NONE) {
3569 m += n;
3570 continue;
3571 }
3572 }
3573
3574 /* this is either PointCoord or replaced by sprite coords */
3575 for (c = 0; c < 4; c++) {
3576 if (!(fp->cfg.io[i].mask & (1 << c)))
3577 continue;
3578 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3579 ++m;
3580 }
3581 }
3582 }
3583
3584 static int
3585 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3586 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3587 {
3588 int c;
3589 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3590 uint8_t *map = (uint8_t *)p_map;
3591
3592 for (c = 0; c < 4; ++c) {
3593 if (mf & 1) {
3594 if (fpi->linear == TRUE)
3595 lin[mid / 32] |= 1 << (mid % 32);
3596 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3597 }
3598
3599 oid += mv & 1;
3600 mf >>= 1;
3601 mv >>= 1;
3602 }
3603
3604 return mid;
3605 }
3606
3607 void
3608 nv50_linkage_validate(struct nv50_context *nv50)
3609 {
3610 struct nouveau_grobj *tesla = nv50->screen->tesla;
3611 struct nv50_program *vp = nv50->vertprog;
3612 struct nv50_program *fp = nv50->fragprog;
3613 struct nouveau_stateobj *so;
3614 struct nv50_sreg4 dummy, *vpo;
3615 int i, n, c, m = 0;
3616 uint32_t map[16], lin[4], reg[5], pcrd[8];
3617
3618 memset(map, 0, sizeof(map));
3619 memset(lin, 0, sizeof(lin));
3620
3621 reg[1] = 0x00000004; /* low and high clip distance map ids */
3622 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3623 reg[3] = 0x00000000; /* point size map id & enable */
3624 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3625 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3626
3627 dummy.linear = FALSE;
3628 dummy.mask = 0xf; /* map all components of HPOS */
3629 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3630
3631 dummy.mask = 0x0;
3632
3633 if (vp->cfg.clpd < 0x40) {
3634 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3635 map[m++] = vp->cfg.clpd + c;
3636 reg[1] = (m << 8);
3637 }
3638
3639 reg[0] |= m << 8; /* adjust BFC0 id */
3640
3641 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3642 if (nv50->rasterizer->pipe.light_twoside) {
3643 vpo = &vp->cfg.two_side[0];
3644
3645 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3646 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3647 }
3648
3649 reg[0] += m - 4; /* adjust FFC0 id */
3650 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3651
3652 for (i = 0; i < fp->cfg.io_nr; i++) {
3653 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3654 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3655
3656 /* position must be mapped first */
3657 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3658
3659 /* maybe even remove these from cfg.io */
3660 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3661 continue;
3662
3663 /* VP outputs and vp->cfg.io are in the same order */
3664 for (n = 0; n < vp->info.num_outputs; ++n) {
3665 if (vp->info.output_semantic_name[n] == sn &&
3666 vp->info.output_semantic_index[n] == si)
3667 break;
3668 }
3669 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3670
3671 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3672 }
3673
3674 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3675 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3676 reg[3] = (m++ << 4) | 1;
3677 }
3678
3679 /* now fill the stateobj */
3680 so = so_new(64, 0);
3681
3682 n = (m + 3) / 4;
3683 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3684 so_data (so, m);
3685 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3686 so_datap (so, map, n);
3687
3688 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3689 so_datap (so, reg, 4);
3690
3691 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3692 so_data (so, reg[4]);
3693
3694 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3695 so_datap (so, lin, 4);
3696
3697 if (nv50->rasterizer->pipe.point_sprite) {
3698 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3699
3700 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3701 so_datap (so, pcrd, 8);
3702 }
3703
3704 so_ref(so, &nv50->state.programs);
3705 so_ref(NULL, &so);
3706 }
3707
3708 void
3709 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3710 {
3711 while (p->exec_head) {
3712 struct nv50_program_exec *e = p->exec_head;
3713
3714 p->exec_head = e->next;
3715 FREE(e);
3716 }
3717 p->exec_tail = NULL;
3718 p->exec_size = 0;
3719
3720 nouveau_bo_ref(NULL, &p->bo);
3721
3722 nouveau_resource_free(&p->data[0]);
3723
3724 p->translated = 0;
3725 }