2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 64
35 #define NV50_SU_MAX_ADDR 7
36 //#define NV50_PROGRAM_DUMP
38 /* ARL - gallium craps itself on progs/vp/arl.txt
40 * MSB - Like MAD, but MUL+SUB
41 * - Fuck it off, introduce a way to negate args for ops that
44 * Look into inlining IMMD for ops other than MOV (make it general?)
45 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
46 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
48 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
49 * case, if the emit_src() causes the inst to suddenly become long.
51 * Verify half-insns work where expected - and force disable them where they
52 * don't work - MUL has it forcibly disabled atm as it fixes POW..
54 * FUCK! watch dst==src vectors, can overwrite components that are needed.
55 * ie. SUB R0, R0.yzxw, R0
57 * Things to check with renouveau:
58 * FP attr/result assignment - how?
60 * - 0x16bc maps vp output onto fp hpos
61 * - 0x16c0 maps vp output onto fp col0
65 * 0x16bc->0x16e8 --> some binding between vp/fp regs
66 * 0x16b8 --> VP output count
68 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
69 * "MOV rcol.x, fcol.y" = 0x00000004
70 * 0x19a8 --> as above but 0x00000100 and 0x00000000
71 * - 0x00100000 used when KIL used
72 * 0x196c --> as above but 0x00000011 and 0x00000000
74 * 0x1988 --> 0xXXNNNNNN
75 * - XX == FP high something
91 int rhw
; /* result hw for FP outputs, or interpolant index */
92 int acc
; /* instruction where this reg is last read (first insn == 1) */
95 /* arbitrary limits */
96 #define MAX_IF_DEPTH 4
97 #define MAX_LOOP_DEPTH 4
100 struct nv50_program
*p
;
103 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
104 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
107 struct nv50_reg
*temp
;
109 struct nv50_reg
*attr
;
111 struct nv50_reg
*result
;
113 struct nv50_reg
*param
;
115 struct nv50_reg
*immd
;
118 struct nv50_reg
**addr
;
121 struct nv50_reg
*temp_temp
[16];
122 unsigned temp_temp_nr
;
124 /* broadcast and destination replacement regs */
125 struct nv50_reg
*r_brdc
;
126 struct nv50_reg
*r_dst
[4];
128 unsigned interp_mode
[32];
129 /* perspective interpolation registers */
130 struct nv50_reg
*iv_p
;
131 struct nv50_reg
*iv_c
;
133 struct nv50_program_exec
*if_cond
;
134 struct nv50_program_exec
*if_insn
[MAX_IF_DEPTH
];
135 struct nv50_program_exec
*br_join
[MAX_IF_DEPTH
];
136 struct nv50_program_exec
*br_loop
[MAX_LOOP_DEPTH
]; /* for BRK branch */
137 int if_lvl
, loop_lvl
;
138 unsigned loop_pos
[MAX_LOOP_DEPTH
];
140 /* current instruction and total number of insns */
148 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
158 static INLINE
unsigned
159 popcnt4(uint32_t val
)
161 static const unsigned cnt
[16]
162 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
163 return cnt
[val
& 0xf];
167 terminate_mbb(struct nv50_pc
*pc
)
171 /* remove records of temporary address register values */
172 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
173 if (pc
->r_addr
[i
].index
< 0)
174 pc
->r_addr
[i
].rhw
= -1;
178 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
182 if (reg
->type
== P_RESULT
) {
183 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
184 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
187 if (reg
->type
!= P_TEMP
)
191 /*XXX: do this here too to catch FP temp-as-attr usage..
192 * not clean, but works */
193 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
194 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
198 if (reg
->rhw
!= -1) {
199 /* try to allocate temporary with index rhw first */
200 if (!(pc
->r_temp
[reg
->rhw
])) {
201 pc
->r_temp
[reg
->rhw
] = reg
;
203 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
204 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
207 /* make sure we don't get things like $r0 needs to go
208 * in $r1 and $r1 in $r0
210 i
= pc
->result_nr
* 4;
213 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
214 if (!(pc
->r_temp
[i
])) {
217 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
218 pc
->p
->cfg
.high_temp
= i
+ 1;
226 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
227 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
228 * lest we risk temp_temps overwriting regs alloc'd "later".
230 static struct nv50_reg
*
231 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
236 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
239 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
240 if (!pc
->r_temp
[i
]) {
241 r
= MALLOC_STRUCT(nv50_reg
);
242 ctor_reg(r
, P_TEMP
, -1, i
);
252 /* Assign the hw of the discarded temporary register src
253 * to the tgsi register dst and free src.
256 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
258 assert(src
->index
== -1 && src
->hw
!= -1);
261 pc
->r_temp
[dst
->hw
] = NULL
;
262 pc
->r_temp
[src
->hw
] = dst
;
268 /* release the hardware resource held by r */
270 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
272 assert(r
->type
== P_TEMP
);
276 assert(pc
->r_temp
[r
->hw
] == r
);
277 pc
->r_temp
[r
->hw
] = NULL
;
285 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
287 if (r
->index
== -1) {
290 FREE(pc
->r_temp
[hw
]);
291 pc
->r_temp
[hw
] = NULL
;
296 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
300 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
303 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
304 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
305 return alloc_temp4(pc
, dst
, idx
+ 4);
307 for (i
= 0; i
< 4; i
++) {
308 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
309 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
310 pc
->r_temp
[idx
+ i
] = dst
[i
];
317 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
321 for (i
= 0; i
< 4; i
++)
322 free_temp(pc
, reg
[i
]);
325 static struct nv50_reg
*
326 temp_temp(struct nv50_pc
*pc
)
328 if (pc
->temp_temp_nr
>= 16)
331 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
332 return pc
->temp_temp
[pc
->temp_temp_nr
++];
336 kill_temp_temp(struct nv50_pc
*pc
)
340 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
341 free_temp(pc
, pc
->temp_temp
[i
]);
342 pc
->temp_temp_nr
= 0;
346 ctor_immd(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
348 pc
->immd_buf
= REALLOC(pc
->immd_buf
, (pc
->immd_nr
* 4 * sizeof(float)),
349 (pc
->immd_nr
+ 1) * 4 * sizeof(float));
350 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
351 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
352 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
353 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
355 return pc
->immd_nr
++;
358 static struct nv50_reg
*
359 alloc_immd(struct nv50_pc
*pc
, float f
)
361 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
364 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
365 if (pc
->immd_buf
[hw
] == f
)
368 if (hw
== pc
->immd_nr
* 4)
369 hw
= ctor_immd(pc
, f
, -f
, 0.5 * f
, 0) * 4;
371 ctor_reg(r
, P_IMMD
, -1, hw
);
375 static struct nv50_program_exec
*
376 exec(struct nv50_pc
*pc
)
378 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
385 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
387 struct nv50_program
*p
= pc
->p
;
390 p
->exec_tail
->next
= e
;
394 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
397 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
400 is_long(struct nv50_program_exec
*e
)
408 is_immd(struct nv50_program_exec
*e
)
410 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
416 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
417 struct nv50_program_exec
*e
)
420 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
421 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
425 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
426 struct nv50_program_exec
*e
)
429 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
430 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
434 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
440 set_pred(pc
, 0xf, 0, e
);
441 set_pred_wr(pc
, 0, 0, e
);
445 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
447 if (dst
->type
== P_RESULT
) {
449 e
->inst
[1] |= 0x00000008;
453 e
->inst
[0] |= (dst
->hw
<< 2);
457 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
459 float f
= pc
->immd_buf
[imm
->hw
];
460 unsigned val
= fui(imm
->neg
? -f
: f
);
463 /*XXX: can't be predicated - bits overlap.. catch cases where both
464 * are required and avoid them. */
465 set_pred(pc
, 0, 0, e
);
466 set_pred_wr(pc
, 0, 0, e
);
468 e
->inst
[1] |= 0x00000002 | 0x00000001;
469 e
->inst
[0] |= (val
& 0x3f) << 16;
470 e
->inst
[1] |= (val
>> 6) << 2;
474 emit_set_addr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, unsigned val
)
476 struct nv50_program_exec
*e
= exec(pc
);
478 assert(val
<= 0xffff);
479 e
->inst
[0] = 0xd0000000 | ((val
& 0xffff) << 9);
480 e
->inst
[1] = 0x20000000;
481 e
->inst
[0] |= dst
->hw
<< 2;
487 static struct nv50_reg
*
488 alloc_addr(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
491 struct nv50_reg
*a
= NULL
;
494 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
) {
495 if (pc
->r_addr
[i
].index
>= 0)
497 if (pc
->r_addr
[i
].rhw
>= 0 &&
498 pc
->r_addr
[i
].acc
== pc
->insn_cur
)
501 pc
->r_addr
[i
].rhw
= -1;
502 pc
->r_addr
[i
].index
= i
;
503 return &pc
->r_addr
[i
];
509 for (i
= NV50_SU_MAX_ADDR
- 1; i
>= 0; --i
) {
510 if (pc
->r_addr
[i
].index
>= 0) /* occupied for TGSI */
512 if (pc
->r_addr
[i
].rhw
< 0) { /* unused */
516 if (!a
&& pc
->r_addr
[i
].acc
!= pc
->insn_cur
)
519 if (ref
->hw
- pc
->r_addr
[i
].rhw
< 128) {
520 /* alloc'd & suitable */
521 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
522 return &pc
->r_addr
[i
];
526 emit_set_addr(pc
, a
, ref
->hw
* 4);
528 a
->rhw
= ref
->hw
% 128;
529 a
->acc
= pc
->insn_cur
;
533 #define INTERP_LINEAR 0
534 #define INTERP_FLAT 1
535 #define INTERP_PERSPECTIVE 2
536 #define INTERP_CENTROID 4
538 /* interpolant index has been stored in dst->rhw */
540 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
543 assert(dst
->rhw
!= -1);
544 struct nv50_program_exec
*e
= exec(pc
);
546 e
->inst
[0] |= 0x80000000;
548 e
->inst
[0] |= (dst
->rhw
<< 16);
550 if (mode
& INTERP_FLAT
) {
551 e
->inst
[0] |= (1 << 8);
553 if (mode
& INTERP_PERSPECTIVE
) {
554 e
->inst
[0] |= (1 << 25);
556 e
->inst
[0] |= (iv
->hw
<< 9);
559 if (mode
& INTERP_CENTROID
)
560 e
->inst
[0] |= (1 << 24);
567 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
569 assert(!(e
->inst
[0] & 0x0c000000));
570 assert(!(e
->inst
[1] & 0x00000004));
572 e
->inst
[0] |= (a
->hw
& 3) << 26;
573 e
->inst
[1] |= (a
->hw
>> 2) << 2;
577 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
578 struct nv50_program_exec
*e
)
582 e
->param
.index
= src
->hw
;
584 e
->param
.mask
= m
<< (s
% 32);
587 set_addr(e
, alloc_addr(pc
, src
));
590 assert(src
->type
== P_CONST
);
591 set_addr(e
, pc
->addr
[src
->index
]);
594 e
->inst
[1] |= (((src
->type
== P_IMMD
) ? 0 : 1) << 22);
598 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
600 struct nv50_program_exec
*e
= exec(pc
);
602 e
->inst
[0] = 0x10000000;
608 if (!is_long(e
) && src
->type
== P_IMMD
) {
609 set_immd(pc
, src
, e
);
610 /*XXX: 32-bit, but steals part of "half" reg space - need to
611 * catch and handle this case if/when we do half-regs
614 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
616 set_data(pc
, src
, 0x7f, 9, e
);
617 e
->inst
[1] |= 0x20000000; /* src0 const? */
619 if (src
->type
== P_ATTR
) {
621 e
->inst
[1] |= 0x00200000;
625 e
->inst
[0] |= (src
->hw
<< 9);
628 if (is_long(e
) && !is_immd(e
)) {
629 e
->inst
[1] |= 0x04000000; /* 32-bit */
630 e
->inst
[1] |= 0x0000c000; /* "subsubop" 0x3 */
631 if (!(e
->inst
[1] & 0x20000000))
632 e
->inst
[1] |= 0x00030000; /* "subsubop" 0xf */
634 e
->inst
[0] |= 0x00008000;
640 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
642 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
643 emit_mov(pc
, dst
, imm
);
648 check_swap_src_0_1(struct nv50_pc
*pc
,
649 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
651 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
653 if (src0
->type
== P_CONST
) {
654 if (src1
->type
!= P_CONST
) {
660 if (src1
->type
== P_ATTR
) {
661 if (src0
->type
!= P_ATTR
) {
672 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
673 struct nv50_program_exec
*e
)
675 struct nv50_reg
*temp
;
677 if (src
->type
!= P_TEMP
) {
678 temp
= temp_temp(pc
);
679 emit_mov(pc
, temp
, src
);
684 e
->inst
[0] |= (src
->hw
<< 9);
688 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
690 if (src
->type
== P_ATTR
) {
692 e
->inst
[1] |= 0x00200000;
694 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
695 struct nv50_reg
*temp
= temp_temp(pc
);
697 emit_mov(pc
, temp
, src
);
702 e
->inst
[0] |= (src
->hw
<< 9);
706 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
708 if (src
->type
== P_ATTR
) {
709 struct nv50_reg
*temp
= temp_temp(pc
);
711 emit_mov(pc
, temp
, src
);
714 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
715 assert(!(e
->inst
[0] & 0x00800000));
716 if (e
->inst
[0] & 0x01000000) {
717 struct nv50_reg
*temp
= temp_temp(pc
);
719 emit_mov(pc
, temp
, src
);
722 set_data(pc
, src
, 0x7f, 16, e
);
723 e
->inst
[0] |= 0x00800000;
728 e
->inst
[0] |= ((src
->hw
& 127) << 16);
732 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
736 if (src
->type
== P_ATTR
) {
737 struct nv50_reg
*temp
= temp_temp(pc
);
739 emit_mov(pc
, temp
, src
);
742 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
743 assert(!(e
->inst
[0] & 0x01000000));
744 if (e
->inst
[0] & 0x00800000) {
745 struct nv50_reg
*temp
= temp_temp(pc
);
747 emit_mov(pc
, temp
, src
);
750 set_data(pc
, src
, 0x7f, 32+14, e
);
751 e
->inst
[0] |= 0x01000000;
756 e
->inst
[1] |= ((src
->hw
& 127) << 14);
760 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
761 struct nv50_reg
*src1
)
763 struct nv50_program_exec
*e
= exec(pc
);
765 e
->inst
[0] |= 0xc0000000;
770 check_swap_src_0_1(pc
, &src0
, &src1
);
772 set_src_0(pc
, src0
, e
);
773 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
775 e
->inst
[0] |= 0x00008000;
776 set_immd(pc
, src1
, e
);
778 set_src_1(pc
, src1
, e
);
779 if (src0
->neg
^ src1
->neg
) {
781 e
->inst
[1] |= 0x08000000;
783 e
->inst
[0] |= 0x00008000;
791 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
792 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
794 struct nv50_program_exec
*e
= exec(pc
);
796 e
->inst
[0] |= 0xb0000000;
798 check_swap_src_0_1(pc
, &src0
, &src1
);
800 if (!pc
->allow32
|| src0
->neg
|| src1
->neg
) {
802 e
->inst
[1] |= (src0
->neg
<< 26) | (src1
->neg
<< 27);
806 set_src_0(pc
, src0
, e
);
807 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
808 set_src_2(pc
, src1
, e
);
810 if (src1
->type
== P_IMMD
)
811 set_immd(pc
, src1
, e
);
813 set_src_1(pc
, src1
, e
);
819 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
822 struct nv50_program_exec
*e
= exec(pc
);
825 e
->inst
[1] |= 0xc0000000;
827 e
->inst
[0] |= dst
->hw
<< 2;
828 e
->inst
[0] |= s
<< 16; /* shift left */
829 set_src_0_restricted(pc
, src
, e
);
835 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
836 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
838 struct nv50_program_exec
*e
= exec(pc
);
841 e
->inst
[0] |= 0xb0000000;
842 e
->inst
[1] |= (sub
<< 29);
844 check_swap_src_0_1(pc
, &src0
, &src1
);
846 set_src_0(pc
, src0
, e
);
847 set_src_1(pc
, src1
, e
);
853 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
854 struct nv50_reg
*src1
)
857 emit_add(pc
, dst
, src0
, src1
);
862 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
863 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
865 struct nv50_program_exec
*e
= exec(pc
);
867 e
->inst
[0] |= 0xe0000000;
869 check_swap_src_0_1(pc
, &src0
, &src1
);
871 set_src_0(pc
, src0
, e
);
872 set_src_1(pc
, src1
, e
);
873 set_src_2(pc
, src2
, e
);
875 if (src0
->neg
^ src1
->neg
)
876 e
->inst
[1] |= 0x04000000;
878 e
->inst
[1] |= 0x08000000;
884 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
885 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
888 emit_mad(pc
, dst
, src0
, src1
, src2
);
893 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
894 struct nv50_reg
*dst
, struct nv50_reg
*src
)
896 struct nv50_program_exec
*e
= exec(pc
);
898 e
->inst
[0] |= 0x90000000;
901 e
->inst
[1] |= (sub
<< 29);
906 if (sub
== 0 || sub
== 2)
907 set_src_0_restricted(pc
, src
, e
);
909 set_src_0(pc
, src
, e
);
915 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
917 struct nv50_program_exec
*e
= exec(pc
);
919 e
->inst
[0] |= 0xb0000000;
922 set_src_0(pc
, src
, e
);
924 e
->inst
[1] |= (6 << 29) | 0x00004000;
930 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
932 struct nv50_program_exec
*e
= exec(pc
);
934 e
->inst
[0] |= 0xb0000000;
937 set_src_0(pc
, src
, e
);
939 e
->inst
[1] |= (6 << 29);
944 #define CVTOP_RN 0x01
945 #define CVTOP_FLOOR 0x03
946 #define CVTOP_CEIL 0x05
947 #define CVTOP_TRUNC 0x07
948 #define CVTOP_SAT 0x08
949 #define CVTOP_ABS 0x10
951 /* 0x04 == 32 bit dst */
952 /* 0x40 == dst is float */
953 /* 0x80 == src is float */
954 #define CVT_F32_F32 0xc4
955 #define CVT_F32_S32 0x44
956 #define CVT_F32_U32 0x64
957 #define CVT_S32_F32 0x8c
958 #define CVT_S32_S32 0x0c
963 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
964 int wp
, unsigned cvn
, unsigned fmt
)
966 struct nv50_program_exec
*e
;
971 e
->inst
[0] |= 0xa0000000;
972 e
->inst
[1] |= 0x00004000; /* 32 bit src */
973 e
->inst
[1] |= (cvn
<< 16);
974 e
->inst
[1] |= (fmt
<< 24);
975 set_src_0(pc
, src
, e
);
978 set_pred_wr(pc
, 1, wp
, e
);
983 e
->inst
[0] |= 0x000001fc;
984 e
->inst
[1] |= 0x00000008;
990 /* nv50 Condition codes:
997 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
998 * 0x8 = unordered bit (allows NaN)
1001 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1002 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1004 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1006 struct nv50_program_exec
*e
= exec(pc
);
1007 struct nv50_reg
*rdst
;
1010 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1011 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1014 if (dst
&& dst
->type
!= P_TEMP
)
1015 dst
= alloc_temp(pc
, NULL
);
1019 e
->inst
[0] |= 0xb0000000;
1020 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1022 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1023 * that doesn't seem to match what the hw actually does
1024 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1028 set_pred_wr(pc
, 1, wp
, e
);
1030 set_dst(pc
, dst
, e
);
1032 e
->inst
[0] |= 0x000001fc;
1033 e
->inst
[1] |= 0x00000008;
1036 set_src_0(pc
, src0
, e
);
1037 set_src_1(pc
, src1
, e
);
1040 pc
->if_cond
= pc
->p
->exec_tail
; /* record for OPCODE_IF */
1042 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1044 emit_cvt(pc
, rdst
, dst
, -1, CVTOP_ABS
| CVTOP_RN
, CVT_F32_S32
);
1045 if (rdst
&& rdst
!= dst
)
1049 static INLINE
unsigned
1050 map_tgsi_setop_cc(unsigned op
)
1053 case TGSI_OPCODE_SLT
: return 0x1;
1054 case TGSI_OPCODE_SGE
: return 0x6;
1055 case TGSI_OPCODE_SEQ
: return 0x2;
1056 case TGSI_OPCODE_SGT
: return 0x4;
1057 case TGSI_OPCODE_SLE
: return 0x3;
1058 case TGSI_OPCODE_SNE
: return 0xd;
1066 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1068 emit_cvt(pc
, dst
, src
, -1, CVTOP_FLOOR
, CVT_F32_F32
| CVT_RI
);
1072 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1073 struct nv50_reg
*v
, struct nv50_reg
*e
)
1075 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1077 emit_flop(pc
, 3, temp
, v
);
1078 emit_mul(pc
, temp
, temp
, e
);
1079 emit_preex2(pc
, temp
, temp
);
1080 emit_flop(pc
, 6, dst
, temp
);
1082 free_temp(pc
, temp
);
1086 emit_abs(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1088 emit_cvt(pc
, dst
, src
, -1, CVTOP_ABS
, CVT_F32_F32
);
1092 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1094 emit_cvt(pc
, dst
, src
, -1, CVTOP_SAT
, CVT_F32_F32
);
1098 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1099 struct nv50_reg
**src
)
1101 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1102 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1103 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1104 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1105 struct nv50_reg
*tmp
[4];
1106 boolean allow32
= pc
->allow32
;
1108 pc
->allow32
= FALSE
;
1110 if (mask
& (3 << 1)) {
1111 tmp
[0] = alloc_temp(pc
, NULL
);
1112 emit_minmax(pc
, 4, tmp
[0], src
[0], zero
);
1115 if (mask
& (1 << 2)) {
1116 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1118 tmp
[1] = temp_temp(pc
);
1119 emit_minmax(pc
, 4, tmp
[1], src
[1], zero
);
1121 tmp
[3] = temp_temp(pc
);
1122 emit_minmax(pc
, 4, tmp
[3], src
[3], neg128
);
1123 emit_minmax(pc
, 5, tmp
[3], tmp
[3], pos128
);
1125 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1126 emit_mov(pc
, dst
[2], zero
);
1127 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1130 if (mask
& (1 << 1))
1131 assimilate_temp(pc
, dst
[1], tmp
[0]);
1133 if (mask
& (1 << 2))
1134 free_temp(pc
, tmp
[0]);
1136 pc
->allow32
= allow32
;
1138 /* do this last, in case src[i,j] == dst[0,3] */
1139 if (mask
& (1 << 0))
1140 emit_mov(pc
, dst
[0], one
);
1142 if (mask
& (1 << 3))
1143 emit_mov(pc
, dst
[3], one
);
1152 emit_neg(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1154 emit_cvt(pc
, dst
, src
, -1, CVTOP_RN
, CVT_F32_F32
| CVT_NEG
);
1158 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1160 struct nv50_program_exec
*e
;
1161 const int r_pred
= 1;
1162 unsigned cvn
= CVT_F32_F32
;
1166 /* write predicate reg */
1167 emit_cvt(pc
, NULL
, src
, r_pred
, CVTOP_RN
, cvn
);
1169 /* conditional discard */
1171 e
->inst
[0] = 0x00000002;
1173 set_pred(pc
, 0x1 /* LT */, r_pred
, e
);
1178 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1179 struct nv50_reg
**src
, unsigned unit
, unsigned type
, boolean proj
)
1181 struct nv50_reg
*temp
, *t
[4];
1182 struct nv50_program_exec
*e
;
1184 unsigned c
, mode
, dim
;
1187 case TGSI_TEXTURE_1D
:
1190 case TGSI_TEXTURE_UNKNOWN
:
1191 case TGSI_TEXTURE_2D
:
1192 case TGSI_TEXTURE_SHADOW1D
: /* XXX: x, z */
1193 case TGSI_TEXTURE_RECT
:
1196 case TGSI_TEXTURE_3D
:
1197 case TGSI_TEXTURE_CUBE
:
1198 case TGSI_TEXTURE_SHADOW2D
:
1199 case TGSI_TEXTURE_SHADOWRECT
: /* XXX */
1207 /* some cards need t[0]'s hw index to be a multiple of 4 */
1208 alloc_temp4(pc
, t
, 0);
1211 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1212 mode
= pc
->interp_mode
[src
[0]->index
];
1214 t
[3]->rhw
= src
[3]->rhw
;
1215 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1216 emit_flop(pc
, 0, t
[3], t
[3]);
1218 for (c
= 0; c
< dim
; c
++) {
1219 t
[c
]->rhw
= src
[c
]->rhw
;
1220 emit_interp(pc
, t
[c
], t
[3],
1221 (mode
| INTERP_PERSPECTIVE
));
1224 emit_flop(pc
, 0, t
[3], src
[3]);
1225 for (c
= 0; c
< dim
; c
++)
1226 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1228 /* XXX: for some reason the blob sometimes uses MAD:
1229 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1230 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1234 if (type
== TGSI_TEXTURE_CUBE
) {
1235 temp
= temp_temp(pc
);
1236 emit_minmax(pc
, 4, temp
, src
[0], src
[1]);
1237 emit_minmax(pc
, 4, temp
, temp
, src
[2]);
1238 emit_flop(pc
, 0, temp
, temp
);
1239 for (c
= 0; c
< 3; c
++)
1240 emit_mul(pc
, t
[c
], src
[c
], temp
);
1242 for (c
= 0; c
< dim
; c
++)
1243 emit_mov(pc
, t
[c
], src
[c
]);
1249 e
->inst
[0] |= 0xf0000000;
1250 e
->inst
[1] |= 0x00000004;
1251 set_dst(pc
, t
[0], e
);
1252 e
->inst
[0] |= (unit
<< 9);
1255 e
->inst
[0] |= 0x00400000;
1258 e
->inst
[0] |= 0x00800000;
1260 e
->inst
[0] |= (mask
& 0x3) << 25;
1261 e
->inst
[1] |= (mask
& 0xc) << 12;
1267 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
1268 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
1269 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
1270 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
1274 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1275 * the texture coordinates, not the fetched values: latency ? */
1277 for (c
= 0; c
< 4; c
++) {
1278 if (mask
& (1 << c
))
1279 assimilate_temp(pc
, dst
[c
], t
[c
]);
1281 free_temp(pc
, t
[c
]);
1287 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
,
1288 struct nv50_program_exec
**join
)
1290 struct nv50_program_exec
*e
= exec(pc
);
1294 e
->inst
[0] |= 0xa0000002;
1301 e
->inst
[0] |= 0x10000002;
1303 set_pred(pc
, cc
, pred
, e
);
1308 emit_nop(struct nv50_pc
*pc
)
1310 struct nv50_program_exec
*e
= exec(pc
);
1312 e
->inst
[0] = 0xf0000000;
1314 e
->inst
[1] = 0xe0000000;
1319 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1321 struct nv50_program_exec
*e
= exec(pc
);
1323 assert(src
->type
== P_TEMP
);
1325 e
->inst
[0] = 0xc0140000;
1326 e
->inst
[1] = 0x89800000;
1328 set_dst(pc
, dst
, e
);
1329 set_src_0(pc
, src
, e
);
1330 set_src_2(pc
, src
, e
);
1336 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1338 struct nv50_program_exec
*e
= exec(pc
);
1340 assert(src
->type
== P_TEMP
);
1342 if (!src
->neg
) /* ! double negation */
1343 emit_neg(pc
, src
, src
);
1345 e
->inst
[0] = 0xc0150000;
1346 e
->inst
[1] = 0x8a400000;
1348 set_dst(pc
, dst
, e
);
1349 set_src_0(pc
, src
, e
);
1350 set_src_2(pc
, src
, e
);
1356 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
1358 unsigned q
= 0, m
= ~0;
1360 assert(!is_long(e
));
1362 switch (e
->inst
[0] >> 28) {
1369 /* INTERP (move centroid, perspective and flat bits) */
1371 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
1372 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
1380 q
= ((e
->inst
[0] & (~m
)) >> 2);
1385 q
= ((e
->inst
[0] & (~m
)) << 12);
1388 /* MAD (if src2 == dst) */
1389 q
= ((e
->inst
[0] & 0x1fc) << 12);
1403 /* Some operations support an optional negation flag. */
1405 negate_supported(const struct tgsi_full_instruction
*insn
, int i
)
1409 switch (insn
->Instruction
.Opcode
) {
1410 case TGSI_OPCODE_DDY
:
1411 case TGSI_OPCODE_DP3
:
1412 case TGSI_OPCODE_DP4
:
1413 case TGSI_OPCODE_MUL
:
1414 case TGSI_OPCODE_KIL
:
1415 case TGSI_OPCODE_ADD
:
1416 case TGSI_OPCODE_SUB
:
1417 case TGSI_OPCODE_MAD
:
1419 case TGSI_OPCODE_POW
:
1427 /* Watch out for possible multiple uses of an nv50_reg, we
1428 * can't use nv50_reg::neg in these cases.
1430 for (s
= 0; s
< insn
->Instruction
.NumSrcRegs
; ++s
) {
1433 if ((insn
->FullSrcRegisters
[s
].SrcRegister
.Index
==
1434 insn
->FullSrcRegisters
[i
].SrcRegister
.Index
) &&
1435 (insn
->FullSrcRegisters
[s
].SrcRegister
.File
==
1436 insn
->FullSrcRegisters
[i
].SrcRegister
.File
))
1443 /* Return a read mask for source registers deduced from opcode & write mask. */
1445 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
1447 unsigned x
, mask
= insn
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1449 switch (insn
->Instruction
.Opcode
) {
1450 case TGSI_OPCODE_COS
:
1451 case TGSI_OPCODE_SIN
:
1452 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
1453 case TGSI_OPCODE_DP3
:
1455 case TGSI_OPCODE_DP4
:
1456 case TGSI_OPCODE_DPH
:
1457 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
1459 case TGSI_OPCODE_DST
:
1460 return mask
& (c
? 0xa : 0x6);
1461 case TGSI_OPCODE_EX2
:
1462 case TGSI_OPCODE_LG2
:
1463 case TGSI_OPCODE_POW
:
1464 case TGSI_OPCODE_RCP
:
1465 case TGSI_OPCODE_RSQ
:
1466 case TGSI_OPCODE_SCS
:
1468 case TGSI_OPCODE_LIT
:
1470 case TGSI_OPCODE_TEX
:
1471 case TGSI_OPCODE_TXP
:
1473 const struct tgsi_instruction_ext_texture
*tex
;
1475 assert(insn
->Instruction
.Extended
);
1476 tex
= &insn
->InstructionExtTexture
;
1479 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
1482 switch (tex
->Texture
) {
1483 case TGSI_TEXTURE_1D
:
1486 case TGSI_TEXTURE_2D
:
1494 case TGSI_OPCODE_XPD
:
1496 if (mask
& 1) x
|= 0x6;
1497 if (mask
& 2) x
|= 0x5;
1498 if (mask
& 4) x
|= 0x3;
1507 static struct nv50_reg
*
1508 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
1510 switch (dst
->DstRegister
.File
) {
1511 case TGSI_FILE_TEMPORARY
:
1512 return &pc
->temp
[dst
->DstRegister
.Index
* 4 + c
];
1513 case TGSI_FILE_OUTPUT
:
1514 return &pc
->result
[dst
->DstRegister
.Index
* 4 + c
];
1515 case TGSI_FILE_ADDRESS
:
1517 struct nv50_reg
*r
= pc
->addr
[dst
->DstRegister
.Index
* 4 + c
];
1519 r
= alloc_addr(pc
, NULL
);
1520 pc
->addr
[dst
->DstRegister
.Index
* 4 + c
] = r
;
1525 case TGSI_FILE_NULL
:
1534 static struct nv50_reg
*
1535 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
1538 struct nv50_reg
*r
= NULL
;
1539 struct nv50_reg
*temp
;
1540 unsigned sgn
, c
, swz
;
1542 if (src
->SrcRegister
.File
!= TGSI_FILE_CONSTANT
)
1543 assert(!src
->SrcRegister
.Indirect
);
1545 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
1547 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
1549 case TGSI_SWIZZLE_X
:
1550 case TGSI_SWIZZLE_Y
:
1551 case TGSI_SWIZZLE_Z
:
1552 case TGSI_SWIZZLE_W
:
1553 switch (src
->SrcRegister
.File
) {
1554 case TGSI_FILE_INPUT
:
1555 r
= &pc
->attr
[src
->SrcRegister
.Index
* 4 + c
];
1557 case TGSI_FILE_TEMPORARY
:
1558 r
= &pc
->temp
[src
->SrcRegister
.Index
* 4 + c
];
1560 case TGSI_FILE_CONSTANT
:
1561 if (!src
->SrcRegister
.Indirect
) {
1562 r
= &pc
->param
[src
->SrcRegister
.Index
* 4 + c
];
1565 /* Indicate indirection by setting r->acc < 0 and
1566 * use the index field to select the address reg.
1568 r
= MALLOC_STRUCT(nv50_reg
);
1569 swz
= tgsi_util_get_src_register_swizzle(
1570 &src
->SrcRegisterInd
, 0);
1571 ctor_reg(r
, P_CONST
,
1572 src
->SrcRegisterInd
.Index
* 4 + swz
, c
);
1575 case TGSI_FILE_IMMEDIATE
:
1576 r
= &pc
->immd
[src
->SrcRegister
.Index
* 4 + c
];
1578 case TGSI_FILE_SAMPLER
:
1580 case TGSI_FILE_ADDRESS
:
1581 r
= pc
->addr
[src
->SrcRegister
.Index
* 4 + c
];
1595 case TGSI_UTIL_SIGN_KEEP
:
1597 case TGSI_UTIL_SIGN_CLEAR
:
1598 temp
= temp_temp(pc
);
1599 emit_abs(pc
, temp
, r
);
1602 case TGSI_UTIL_SIGN_TOGGLE
:
1606 temp
= temp_temp(pc
);
1607 emit_neg(pc
, temp
, r
);
1611 case TGSI_UTIL_SIGN_SET
:
1612 temp
= temp_temp(pc
);
1613 emit_abs(pc
, temp
, r
);
1617 emit_neg(pc
, temp
, temp
);
1628 /* return TRUE for ops that produce only a single result */
1630 is_scalar_op(unsigned op
)
1633 case TGSI_OPCODE_COS
:
1634 case TGSI_OPCODE_DP2
:
1635 case TGSI_OPCODE_DP3
:
1636 case TGSI_OPCODE_DP4
:
1637 case TGSI_OPCODE_DPH
:
1638 case TGSI_OPCODE_EX2
:
1639 case TGSI_OPCODE_LG2
:
1640 case TGSI_OPCODE_POW
:
1641 case TGSI_OPCODE_RCP
:
1642 case TGSI_OPCODE_RSQ
:
1643 case TGSI_OPCODE_SIN
:
1645 case TGSI_OPCODE_KIL:
1646 case TGSI_OPCODE_LIT:
1647 case TGSI_OPCODE_SCS:
1655 /* Returns a bitmask indicating which dst components depend
1656 * on source s, component c (reverse of nv50_tgsi_src_mask).
1659 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
1661 if (is_scalar_op(op
))
1665 case TGSI_OPCODE_DST
:
1666 return (1 << c
) & (s
? 0xa : 0x6);
1667 case TGSI_OPCODE_XPD
:
1677 case TGSI_OPCODE_LIT
:
1678 case TGSI_OPCODE_SCS
:
1679 case TGSI_OPCODE_TEX
:
1680 case TGSI_OPCODE_TXP
:
1681 /* these take care of dangerous swizzles themselves */
1683 case TGSI_OPCODE_IF
:
1684 case TGSI_OPCODE_KIL
:
1685 /* don't call this function for these ops */
1689 /* linear vector instruction */
1694 static INLINE boolean
1695 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
1697 if (!is_long(e
) || is_immd(e
))
1699 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
1702 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1709 nv50_kill_branch(struct nv50_pc
*pc
)
1711 int lvl
= pc
->if_lvl
;
1713 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
1716 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1717 * reg may no longer be valid, since we currently always use $p0
1719 if (has_pred(pc
->if_insn
[lvl
], 0xf))
1721 assert(pc
->if_insn
[lvl
] && pc
->br_join
[lvl
]);
1723 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1724 * update prev's next); if exec_tail is BRK, update the pointer.
1726 if (pc
->loop_lvl
&& pc
->br_loop
[pc
->loop_lvl
- 1] == pc
->p
->exec_tail
)
1727 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->br_join
[lvl
];
1729 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
1731 *pc
->br_join
[lvl
] = *pc
->p
->exec_tail
;
1733 FREE(pc
->if_insn
[lvl
]);
1734 FREE(pc
->p
->exec_tail
);
1736 pc
->p
->exec_tail
= pc
->br_join
[lvl
];
1737 pc
->p
->exec_tail
->next
= NULL
;
1738 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
1744 nv50_program_tx_insn(struct nv50_pc
*pc
,
1745 const struct tgsi_full_instruction
*inst
)
1747 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
1748 unsigned mask
, sat
, unit
;
1751 mask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1752 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
1754 memset(src
, 0, sizeof(src
));
1756 for (c
= 0; c
< 4; c
++) {
1757 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
1758 dst
[c
] = tgsi_dst(pc
, c
, &inst
->FullDstRegisters
[0]);
1760 dst
[c
] = pc
->r_dst
[c
];
1764 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1765 const struct tgsi_full_src_register
*fs
= &inst
->FullSrcRegisters
[i
];
1769 src_mask
= nv50_tgsi_src_mask(inst
, i
);
1770 neg_supp
= negate_supported(inst
, i
);
1772 if (fs
->SrcRegister
.File
== TGSI_FILE_SAMPLER
)
1773 unit
= fs
->SrcRegister
.Index
;
1775 for (c
= 0; c
< 4; c
++)
1776 if (src_mask
& (1 << c
))
1777 src
[i
][c
] = tgsi_src(pc
, c
, fs
, neg_supp
);
1780 brdc
= temp
= pc
->r_brdc
;
1781 if (brdc
&& brdc
->type
!= P_TEMP
) {
1782 temp
= temp_temp(pc
);
1787 for (c
= 0; c
< 4; c
++) {
1788 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
1791 dst
[c
] = temp_temp(pc
);
1795 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
1797 switch (inst
->Instruction
.Opcode
) {
1798 case TGSI_OPCODE_ABS
:
1799 for (c
= 0; c
< 4; c
++) {
1800 if (!(mask
& (1 << c
)))
1802 emit_abs(pc
, dst
[c
], src
[0][c
]);
1805 case TGSI_OPCODE_ADD
:
1806 for (c
= 0; c
< 4; c
++) {
1807 if (!(mask
& (1 << c
)))
1809 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1812 case TGSI_OPCODE_ARL
:
1814 temp
= temp_temp(pc
);
1815 emit_cvt(pc
, temp
, src
[0][0], -1, CVTOP_FLOOR
, CVT_S32_F32
);
1816 emit_arl(pc
, dst
[0], temp
, 4);
1818 case TGSI_OPCODE_BGNLOOP
:
1819 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
1822 case TGSI_OPCODE_BRK
:
1823 emit_branch(pc
, -1, 0, NULL
);
1824 assert(pc
->loop_lvl
> 0);
1825 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->p
->exec_tail
;
1827 case TGSI_OPCODE_CEIL
:
1828 for (c
= 0; c
< 4; c
++) {
1829 if (!(mask
& (1 << c
)))
1831 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
1832 CVTOP_CEIL
, CVT_F32_F32
| CVT_RI
);
1835 case TGSI_OPCODE_CMP
:
1836 pc
->allow32
= FALSE
;
1837 for (c
= 0; c
< 4; c
++) {
1838 if (!(mask
& (1 << c
)))
1840 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVTOP_RN
, CVT_F32_F32
);
1841 emit_mov(pc
, dst
[c
], src
[1][c
]);
1842 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
1843 emit_mov(pc
, dst
[c
], src
[2][c
]);
1844 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
1847 case TGSI_OPCODE_COS
:
1849 emit_precossin(pc
, temp
, src
[0][3]);
1850 emit_flop(pc
, 5, dst
[3], temp
);
1854 temp
= brdc
= temp_temp(pc
);
1856 emit_precossin(pc
, temp
, src
[0][0]);
1857 emit_flop(pc
, 5, brdc
, temp
);
1859 case TGSI_OPCODE_DDX
:
1860 for (c
= 0; c
< 4; c
++) {
1861 if (!(mask
& (1 << c
)))
1863 emit_ddx(pc
, dst
[c
], src
[0][c
]);
1866 case TGSI_OPCODE_DDY
:
1867 for (c
= 0; c
< 4; c
++) {
1868 if (!(mask
& (1 << c
)))
1870 emit_ddy(pc
, dst
[c
], src
[0][c
]);
1873 case TGSI_OPCODE_DP3
:
1874 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1875 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1876 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
1878 case TGSI_OPCODE_DP4
:
1879 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1880 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1881 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1882 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
1884 case TGSI_OPCODE_DPH
:
1885 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1886 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1887 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1888 emit_add(pc
, brdc
, src
[1][3], temp
);
1890 case TGSI_OPCODE_DST
:
1891 if (mask
& (1 << 1))
1892 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
1893 if (mask
& (1 << 2))
1894 emit_mov(pc
, dst
[2], src
[0][2]);
1895 if (mask
& (1 << 3))
1896 emit_mov(pc
, dst
[3], src
[1][3]);
1897 if (mask
& (1 << 0))
1898 emit_mov_immdval(pc
, dst
[0], 1.0f
);
1900 case TGSI_OPCODE_ELSE
:
1901 emit_branch(pc
, -1, 0, NULL
);
1902 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1903 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
1906 case TGSI_OPCODE_ENDIF
:
1907 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1909 /* try to replace branch over 1 insn with a predicated insn */
1910 if (nv50_kill_branch(pc
) == TRUE
)
1913 if (pc
->br_join
[pc
->if_lvl
]) {
1914 pc
->br_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1915 pc
->br_join
[pc
->if_lvl
] = NULL
;
1918 /* emit a NOP as join point, we could set it on the next
1919 * one, but would have to make sure it is long and !immd
1922 pc
->p
->exec_tail
->inst
[1] |= 2;
1924 case TGSI_OPCODE_ENDLOOP
:
1925 emit_branch(pc
, -1, 0, NULL
);
1926 pc
->p
->exec_tail
->param
.index
= pc
->loop_pos
[--pc
->loop_lvl
];
1927 pc
->br_loop
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
1930 case TGSI_OPCODE_EX2
:
1931 emit_preex2(pc
, temp
, src
[0][0]);
1932 emit_flop(pc
, 6, brdc
, temp
);
1934 case TGSI_OPCODE_FLR
:
1935 for (c
= 0; c
< 4; c
++) {
1936 if (!(mask
& (1 << c
)))
1938 emit_flr(pc
, dst
[c
], src
[0][c
]);
1941 case TGSI_OPCODE_FRC
:
1942 temp
= temp_temp(pc
);
1943 for (c
= 0; c
< 4; c
++) {
1944 if (!(mask
& (1 << c
)))
1946 emit_flr(pc
, temp
, src
[0][c
]);
1947 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
1950 case TGSI_OPCODE_IF
:
1951 /* emitting a join_at may not be necessary */
1952 assert(pc
->if_lvl
< MAX_IF_DEPTH
);
1953 set_pred_wr(pc
, 1, 0, pc
->if_cond
);
1954 emit_branch(pc
, 0, 2, &pc
->br_join
[pc
->if_lvl
]);
1955 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
1958 case TGSI_OPCODE_KIL
:
1959 emit_kil(pc
, src
[0][0]);
1960 emit_kil(pc
, src
[0][1]);
1961 emit_kil(pc
, src
[0][2]);
1962 emit_kil(pc
, src
[0][3]);
1964 case TGSI_OPCODE_LIT
:
1965 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
1967 case TGSI_OPCODE_LG2
:
1968 emit_flop(pc
, 3, brdc
, src
[0][0]);
1970 case TGSI_OPCODE_LRP
:
1971 temp
= temp_temp(pc
);
1972 for (c
= 0; c
< 4; c
++) {
1973 if (!(mask
& (1 << c
)))
1975 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
1976 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
1979 case TGSI_OPCODE_MAD
:
1980 for (c
= 0; c
< 4; c
++) {
1981 if (!(mask
& (1 << c
)))
1983 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
1986 case TGSI_OPCODE_MAX
:
1987 for (c
= 0; c
< 4; c
++) {
1988 if (!(mask
& (1 << c
)))
1990 emit_minmax(pc
, 4, dst
[c
], src
[0][c
], src
[1][c
]);
1993 case TGSI_OPCODE_MIN
:
1994 for (c
= 0; c
< 4; c
++) {
1995 if (!(mask
& (1 << c
)))
1997 emit_minmax(pc
, 5, dst
[c
], src
[0][c
], src
[1][c
]);
2000 case TGSI_OPCODE_MOV
:
2001 for (c
= 0; c
< 4; c
++) {
2002 if (!(mask
& (1 << c
)))
2004 emit_mov(pc
, dst
[c
], src
[0][c
]);
2007 case TGSI_OPCODE_MUL
:
2008 for (c
= 0; c
< 4; c
++) {
2009 if (!(mask
& (1 << c
)))
2011 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2014 case TGSI_OPCODE_POW
:
2015 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2017 case TGSI_OPCODE_RCP
:
2018 emit_flop(pc
, 0, brdc
, src
[0][0]);
2020 case TGSI_OPCODE_RSQ
:
2021 emit_flop(pc
, 2, brdc
, src
[0][0]);
2023 case TGSI_OPCODE_SCS
:
2024 temp
= temp_temp(pc
);
2026 emit_precossin(pc
, temp
, src
[0][0]);
2027 if (mask
& (1 << 0))
2028 emit_flop(pc
, 5, dst
[0], temp
);
2029 if (mask
& (1 << 1))
2030 emit_flop(pc
, 4, dst
[1], temp
);
2031 if (mask
& (1 << 2))
2032 emit_mov_immdval(pc
, dst
[2], 0.0);
2033 if (mask
& (1 << 3))
2034 emit_mov_immdval(pc
, dst
[3], 1.0);
2036 case TGSI_OPCODE_SIN
:
2038 emit_precossin(pc
, temp
, src
[0][3]);
2039 emit_flop(pc
, 4, dst
[3], temp
);
2043 temp
= brdc
= temp_temp(pc
);
2045 emit_precossin(pc
, temp
, src
[0][0]);
2046 emit_flop(pc
, 4, brdc
, temp
);
2048 case TGSI_OPCODE_SLT
:
2049 case TGSI_OPCODE_SGE
:
2050 case TGSI_OPCODE_SEQ
:
2051 case TGSI_OPCODE_SGT
:
2052 case TGSI_OPCODE_SLE
:
2053 case TGSI_OPCODE_SNE
:
2054 i
= map_tgsi_setop_cc(inst
->Instruction
.Opcode
);
2055 for (c
= 0; c
< 4; c
++) {
2056 if (!(mask
& (1 << c
)))
2058 emit_set(pc
, i
, dst
[c
], -1, src
[0][c
], src
[1][c
]);
2061 case TGSI_OPCODE_SUB
:
2062 for (c
= 0; c
< 4; c
++) {
2063 if (!(mask
& (1 << c
)))
2065 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2068 case TGSI_OPCODE_TEX
:
2069 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2070 inst
->InstructionExtTexture
.Texture
, FALSE
);
2072 case TGSI_OPCODE_TXP
:
2073 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2074 inst
->InstructionExtTexture
.Texture
, TRUE
);
2076 case TGSI_OPCODE_TRUNC
:
2077 for (c
= 0; c
< 4; c
++) {
2078 if (!(mask
& (1 << c
)))
2080 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2081 CVTOP_TRUNC
, CVT_F32_F32
| CVT_RI
);
2084 case TGSI_OPCODE_XPD
:
2085 temp
= temp_temp(pc
);
2086 if (mask
& (1 << 0)) {
2087 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
2088 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
2090 if (mask
& (1 << 1)) {
2091 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
2092 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
2094 if (mask
& (1 << 2)) {
2095 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
2096 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
2098 if (mask
& (1 << 3))
2099 emit_mov_immdval(pc
, dst
[3], 1.0);
2101 case TGSI_OPCODE_END
:
2104 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
2110 emit_sat(pc
, brdc
, brdc
);
2111 for (c
= 0; c
< 4; c
++)
2112 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
2113 emit_mov(pc
, dst
[c
], brdc
);
2116 for (c
= 0; c
< 4; c
++) {
2117 if (!(mask
& (1 << c
)))
2119 /* in this case we saturate later */
2120 if (dst
[c
]->type
== P_TEMP
&& dst
[c
]->index
< 0)
2122 emit_sat(pc
, rdst
[c
], dst
[c
]);
2126 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2127 for (c
= 0; c
< 4; c
++) {
2131 if (src
[i
][c
]->index
== -1 && src
[i
][c
]->type
== P_IMMD
)
2134 if (src
[i
][c
]->acc
< 0 && src
[i
][c
]->type
== P_CONST
)
2135 FREE(src
[i
][c
]); /* indirect constant */
2144 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
2146 struct nv50_reg
*reg
= NULL
;
2147 const struct tgsi_full_src_register
*src
;
2148 const struct tgsi_dst_register
*dst
;
2149 unsigned i
, c
, k
, mask
;
2151 dst
= &insn
->FullDstRegisters
[0].DstRegister
;
2152 mask
= dst
->WriteMask
;
2154 if (dst
->File
== TGSI_FILE_TEMPORARY
)
2157 if (dst
->File
== TGSI_FILE_OUTPUT
)
2161 for (c
= 0; c
< 4; c
++) {
2162 if (!(mask
& (1 << c
)))
2164 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
2168 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2169 src
= &insn
->FullSrcRegisters
[i
];
2171 if (src
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
)
2174 if (src
->SrcRegister
.File
== TGSI_FILE_INPUT
)
2179 mask
= nv50_tgsi_src_mask(insn
, i
);
2181 for (c
= 0; c
< 4; c
++) {
2182 if (!(mask
& (1 << c
)))
2184 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
2186 reg
[src
->SrcRegister
.Index
* 4 + k
].acc
= pc
->insn_nr
;
2191 /* Returns a bitmask indicating which dst components need to be
2192 * written to temporaries first to avoid 'corrupting' sources.
2194 * m[i] (out) indicate component to write in the i-th position
2195 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2198 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
2200 unsigned i
, c
, x
, unsafe
;
2202 for (c
= 0; c
< 4; c
++)
2205 /* Swap as long as a dst component written earlier is depended on
2206 * by one written later, but the next one isn't depended on by it.
2208 for (c
= 0; c
< 3; c
++) {
2209 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
2210 continue; /* if next one is depended on by us */
2211 for (i
= c
+ 1; i
< 4; i
++)
2212 /* if we are depended on by a later one */
2213 if (rdep
[m
[c
]] & (1 << m
[i
]))
2226 /* mark dependencies that could not be resolved by reordering */
2227 for (i
= 0; i
< 3; ++i
)
2228 for (c
= i
+ 1; c
< 4; ++c
)
2229 if (rdep
[m
[i
]] & (1 << m
[c
]))
2232 /* NOTE: $unsafe is with respect to order, not component */
2236 /* Select a suitable dst register for broadcasting scalar results,
2237 * or return NULL if we have to allocate an extra TEMP.
2239 * If e.g. only 1 component is written, we may also emit the final
2240 * result to a write-only register.
2242 static struct nv50_reg
*
2243 tgsi_broadcast_dst(struct nv50_pc
*pc
,
2244 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
2246 if (fd
->DstRegister
.File
== TGSI_FILE_TEMPORARY
) {
2247 int c
= ffs(~mask
& fd
->DstRegister
.WriteMask
);
2249 return tgsi_dst(pc
, c
- 1, fd
);
2251 int c
= ffs(fd
->DstRegister
.WriteMask
) - 1;
2252 if ((1 << c
) == fd
->DstRegister
.WriteMask
)
2253 return tgsi_dst(pc
, c
, fd
);
2259 /* Scan source swizzles and return a bitmask indicating dst regs that
2260 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2263 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
2266 const struct tgsi_full_dst_register
*fd
= &insn
->FullDstRegisters
[0];
2267 const struct tgsi_full_src_register
*fs
;
2268 unsigned i
, deqs
= 0;
2270 for (i
= 0; i
< 4; ++i
)
2273 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2274 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
2275 boolean neg_supp
= negate_supported(insn
, i
);
2277 fs
= &insn
->FullSrcRegisters
[i
];
2278 if (fs
->SrcRegister
.File
!= fd
->DstRegister
.File
||
2279 fs
->SrcRegister
.Index
!= fd
->DstRegister
.Index
)
2282 for (chn
= 0; chn
< 4; ++chn
) {
2285 if (!(mask
& (1 << chn
))) /* src is not read */
2287 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
2288 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
2290 if (!(fd
->DstRegister
.WriteMask
& (1 << c
)))
2293 /* no danger if src is copied to TEMP first */
2294 if ((s
!= TGSI_UTIL_SIGN_KEEP
) &&
2295 (s
!= TGSI_UTIL_SIGN_TOGGLE
|| !neg_supp
))
2298 rdep
[c
] |= nv50_tgsi_dst_revdep(
2299 insn
->Instruction
.Opcode
, i
, chn
);
2308 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
2310 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
2311 const struct tgsi_full_dst_register
*fd
;
2312 unsigned i
, deqs
, rdep
[4], m
[4];
2314 fd
= &tok
->FullInstruction
.FullDstRegisters
[0];
2315 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
2317 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
2318 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
2320 pc
->r_brdc
= temp_temp(pc
);
2321 return nv50_program_tx_insn(pc
, &insn
);
2326 return nv50_program_tx_insn(pc
, &insn
);
2328 deqs
= nv50_revdep_reorder(m
, rdep
);
2330 for (i
= 0; i
< 4; ++i
) {
2331 assert(pc
->r_dst
[m
[i
]] == NULL
);
2333 insn
.FullDstRegisters
[0].DstRegister
.WriteMask
=
2334 fd
->DstRegister
.WriteMask
& (1 << m
[i
]);
2336 if (!insn
.FullDstRegisters
[0].DstRegister
.WriteMask
)
2339 if (deqs
& (1 << i
))
2340 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
2342 if (!nv50_program_tx_insn(pc
, &insn
))
2346 for (i
= 0; i
< 4; i
++) {
2347 struct nv50_reg
*reg
= pc
->r_dst
[i
];
2350 pc
->r_dst
[i
] = NULL
;
2352 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
2353 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2355 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2363 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
2365 struct nv50_reg
*iv
, **ppiv
;
2366 unsigned mode
= pc
->interp_mode
[reg
->index
];
2368 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
2371 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
2372 iv
= *ppiv
= alloc_temp(pc
, NULL
);
2373 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
2375 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
2376 emit_flop(pc
, 0, iv
, iv
);
2378 /* XXX: when loading interpolants dynamically, move these
2379 * to the program head, or make sure it can't be skipped.
2383 emit_interp(pc
, reg
, iv
, mode
);
2387 nv50_program_tx_prep(struct nv50_pc
*pc
)
2389 struct tgsi_parse_context tp
;
2390 struct nv50_program
*p
= pc
->p
;
2391 boolean ret
= FALSE
;
2392 unsigned i
, c
, flat_nr
= 0;
2394 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
2395 while (!tgsi_parse_end_of_tokens(&tp
)) {
2396 const union tgsi_full_token
*tok
= &tp
.FullToken
;
2398 tgsi_parse_token(&tp
);
2399 switch (tok
->Token
.Type
) {
2400 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2402 const struct tgsi_full_immediate
*imm
=
2403 &tp
.FullToken
.FullImmediate
;
2405 ctor_immd(pc
, imm
->u
[0].Float
,
2411 case TGSI_TOKEN_TYPE_DECLARATION
:
2413 const struct tgsi_full_declaration
*d
;
2414 unsigned si
, last
, first
, mode
;
2416 d
= &tp
.FullToken
.FullDeclaration
;
2417 first
= d
->DeclarationRange
.First
;
2418 last
= d
->DeclarationRange
.Last
;
2420 switch (d
->Declaration
.File
) {
2421 case TGSI_FILE_TEMPORARY
:
2423 case TGSI_FILE_OUTPUT
:
2424 if (!d
->Declaration
.Semantic
||
2425 p
->type
== PIPE_SHADER_FRAGMENT
)
2428 si
= d
->Semantic
.SemanticIndex
;
2429 switch (d
->Semantic
.SemanticName
) {
2430 case TGSI_SEMANTIC_BCOLOR
:
2431 p
->cfg
.two_side
[si
].hw
= first
;
2432 if (p
->cfg
.io_nr
> first
)
2433 p
->cfg
.io_nr
= first
;
2435 case TGSI_SEMANTIC_PSIZE
:
2436 p
->cfg
.psiz
= first
;
2437 if (p
->cfg
.io_nr
> first
)
2438 p
->cfg
.io_nr
= first
;
2441 case TGSI_SEMANTIC_CLIP_DISTANCE:
2442 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2449 case TGSI_FILE_INPUT
:
2451 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
2454 switch (d
->Declaration
.Interpolate
) {
2455 case TGSI_INTERPOLATE_CONSTANT
:
2459 case TGSI_INTERPOLATE_PERSPECTIVE
:
2460 mode
= INTERP_PERSPECTIVE
;
2461 p
->cfg
.regs
[1] |= 0x08 << 24;
2464 mode
= INTERP_LINEAR
;
2467 if (d
->Declaration
.Centroid
)
2468 mode
|= INTERP_CENTROID
;
2471 for (i
= first
; i
<= last
; i
++)
2472 pc
->interp_mode
[i
] = mode
;
2475 case TGSI_FILE_ADDRESS
:
2476 case TGSI_FILE_CONSTANT
:
2477 case TGSI_FILE_SAMPLER
:
2480 NOUVEAU_ERR("bad decl file %d\n",
2481 d
->Declaration
.File
);
2486 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2488 prep_inspect_insn(pc
, &tok
->FullInstruction
);
2495 if (p
->type
== PIPE_SHADER_VERTEX
) {
2498 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
2499 if (pc
->attr
[i
].acc
) {
2500 pc
->attr
[i
].hw
= rid
++;
2501 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
2505 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
2506 p
->cfg
.io
[i
].hw
= rid
;
2507 p
->cfg
.io
[i
].id_vp
= i
;
2509 for (c
= 0; c
< 4; ++c
) {
2511 if (!pc
->result
[n
].acc
)
2513 pc
->result
[n
].hw
= rid
++;
2514 p
->cfg
.io
[i
].mask
|= 1 << c
;
2518 for (c
= 0; c
< 2; ++c
)
2519 if (p
->cfg
.two_side
[c
].hw
< 0x40)
2520 p
->cfg
.two_side
[c
] = p
->cfg
.io
[
2521 p
->cfg
.two_side
[c
].hw
];
2523 if (p
->cfg
.psiz
< 0x40)
2524 p
->cfg
.psiz
= p
->cfg
.io
[p
->cfg
.psiz
].hw
;
2526 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
2528 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
2530 int base
= (TGSI_SEMANTIC_POSITION
==
2531 p
->info
.input_semantic_name
[0]) ? 0 : 1;
2533 /* non-flat interpolants have to be mapped to
2534 * the lower hardware IDs, so sort them:
2536 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2537 if (pc
->interp_mode
[i
] == INTERP_FLAT
) {
2538 p
->cfg
.io
[m
].id_vp
= i
+ base
;
2539 p
->cfg
.io
[m
++].id_fp
= i
;
2541 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
2542 p
->cfg
.io
[n
].linear
= TRUE
;
2543 p
->cfg
.io
[n
].id_vp
= i
+ base
;
2544 p
->cfg
.io
[n
++].id_fp
= i
;
2548 if (!base
) /* set w-coordinate mask from perspective interp */
2549 p
->cfg
.io
[0].mask
|= p
->cfg
.regs
[1] >> 24;
2551 aid
= popcnt4( /* if fcrd isn't contained in cfg.io */
2552 base
? (p
->cfg
.regs
[1] >> 24) : p
->cfg
.io
[0].mask
);
2554 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
2555 p
->cfg
.io
[n
].hw
= rid
= aid
;
2556 i
= p
->cfg
.io
[n
].id_fp
;
2558 for (c
= 0; c
< 4; ++c
) {
2559 if (!pc
->attr
[i
* 4 + c
].acc
)
2561 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
2562 p
->cfg
.io
[n
].mask
|= 1 << c
;
2564 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
2566 aid
+= popcnt4(p
->cfg
.io
[n
].mask
);
2570 p
->cfg
.regs
[1] |= p
->cfg
.io
[0].mask
<< 24;
2572 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
2574 /* set count of non-position inputs and of non-flat
2575 * non-position inputs for FP_INTERPOLANT_CTRL
2577 p
->cfg
.regs
[1] |= aid
- m
;
2580 i
= p
->cfg
.io
[pc
->attr_nr
- flat_nr
].hw
;
2581 p
->cfg
.regs
[1] |= (i
- m
) << 16;
2583 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
2585 /* mark color semantic for light-twoside */
2587 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2590 sn
= p
->info
.input_semantic_name
[p
->cfg
.io
[i
].id_fp
];
2591 si
= p
->info
.input_semantic_index
[p
->cfg
.io
[i
].id_fp
];
2593 if (sn
== TGSI_SEMANTIC_COLOR
) {
2594 p
->cfg
.two_side
[si
] = p
->cfg
.io
[i
];
2596 /* increase colour count */
2597 p
->cfg
.regs
[0] += popcnt4(
2598 p
->cfg
.two_side
[si
].mask
) << 16;
2600 n
= MIN2(n
, p
->cfg
.io
[i
].hw
- m
);
2604 p
->cfg
.regs
[0] += n
;
2606 /* Initialize FP results:
2607 * FragDepth is always first TGSI and last hw output
2609 i
= p
->info
.writes_z
? 4 : 0;
2610 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
2611 pc
->result
[i
].rhw
= rid
++;
2612 if (p
->info
.writes_z
)
2613 pc
->result
[2].rhw
= rid
;
2615 p
->cfg
.high_result
= rid
;
2621 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
2625 for (i
= 0; i
< pc
->immd_nr
; i
++) {
2626 for (c
= 0; c
< 4; c
++, rid
++)
2627 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
2634 free_temp(pc
, pc
->iv_p
);
2636 free_temp(pc
, pc
->iv_c
);
2638 tgsi_parse_free(&tp
);
2643 free_nv50_pc(struct nv50_pc
*pc
)
2660 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
2663 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
2666 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
2667 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
2668 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
2669 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2670 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
2671 assert(pc
->addr_nr
<= 2);
2673 p
->cfg
.high_temp
= 4;
2675 p
->cfg
.two_side
[0].hw
= 0x40;
2676 p
->cfg
.two_side
[1].hw
= 0x40;
2679 case PIPE_SHADER_VERTEX
:
2682 p
->cfg
.io_nr
= pc
->result_nr
;
2684 case PIPE_SHADER_FRAGMENT
:
2685 rtype
[0] = rtype
[1] = P_TEMP
;
2687 p
->cfg
.regs
[0] = 0x01000004;
2688 p
->cfg
.io_nr
= pc
->attr_nr
;
2690 if (p
->info
.writes_z
) {
2691 p
->cfg
.regs
[2] |= 0x00000100;
2692 p
->cfg
.regs
[3] |= 0x00000011;
2694 if (p
->info
.uses_kill
)
2695 p
->cfg
.regs
[2] |= 0x00100000;
2700 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
2704 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
2705 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
2709 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
2713 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
2714 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
2717 if (pc
->result_nr
) {
2718 unsigned nr
= pc
->result_nr
* 4;
2720 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
2724 for (i
= 0; i
< nr
; ++i
)
2725 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
2731 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
2735 for (i
= 0; i
< pc
->param_nr
; ++i
)
2736 for (c
= 0; c
< 4; ++c
, ++rid
)
2737 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
2741 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
2745 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
2746 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -1, i
+ 1);
2752 nv50_fp_move_results(struct nv50_pc
*pc
)
2754 struct nv50_reg reg
;
2757 ctor_reg(®
, P_TEMP
, -1, -1);
2759 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2760 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2762 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2763 reg
.hw
= pc
->result
[i
].rhw
;
2764 emit_mov(pc
, ®
, &pc
->result
[i
]);
2770 nv50_program_fixup_insns(struct nv50_pc
*pc
)
2772 struct nv50_program_exec
*e
, *prev
= NULL
, **bra_list
;
2775 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
2777 /* Collect branch instructions, we need to adjust their offsets
2778 * when converting 32 bit instructions to 64 bit ones
2780 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
2781 if (e
->param
.index
>= 0 && !e
->param
.mask
)
2784 /* Make sure we don't have any single 32 bit instructions. */
2785 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
2786 pos
+= is_long(e
) ? 2 : 1;
2788 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
2789 for (i
= 0; i
< n
; ++i
)
2790 if (bra_list
[i
]->param
.index
>= pos
)
2791 bra_list
[i
]->param
.index
+= 1;
2792 convert_to_long(pc
, e
);
2799 assert(!is_immd(pc
->p
->exec_head
));
2800 assert(!is_immd(pc
->p
->exec_tail
));
2802 /* last instruction must be long so it can have the end bit set */
2803 if (!is_long(pc
->p
->exec_tail
)) {
2804 convert_to_long(pc
, pc
->p
->exec_tail
);
2806 convert_to_long(pc
, prev
);
2808 assert(!(pc
->p
->exec_tail
->inst
[1] & 2));
2809 /* set the end-bit */
2810 pc
->p
->exec_tail
->inst
[1] |= 1;
2816 nv50_program_tx(struct nv50_program
*p
)
2818 struct tgsi_parse_context parse
;
2822 pc
= CALLOC_STRUCT(nv50_pc
);
2826 ret
= ctor_nv50_pc(pc
, p
);
2830 ret
= nv50_program_tx_prep(pc
);
2834 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
2835 while (!tgsi_parse_end_of_tokens(&parse
)) {
2836 const union tgsi_full_token
*tok
= &parse
.FullToken
;
2838 /* don't allow half insn/immd on first and last instruction */
2840 if (pc
->insn_cur
== 0 || pc
->insn_cur
+ 2 == pc
->insn_nr
)
2841 pc
->allow32
= FALSE
;
2843 tgsi_parse_token(&parse
);
2845 switch (tok
->Token
.Type
) {
2846 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2848 ret
= nv50_tgsi_insn(pc
, tok
);
2857 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
2858 nv50_fp_move_results(pc
);
2860 nv50_program_fixup_insns(pc
);
2862 p
->param_nr
= pc
->param_nr
* 4;
2863 p
->immd_nr
= pc
->immd_nr
* 4;
2864 p
->immd
= pc
->immd_buf
;
2867 tgsi_parse_free(&parse
);
2875 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
2877 if (nv50_program_tx(p
) == FALSE
)
2879 p
->translated
= TRUE
;
2883 nv50_program_upload_data(struct nv50_context
*nv50
, float *map
,
2884 unsigned start
, unsigned count
, unsigned cbuf
)
2886 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
2887 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
2890 unsigned nr
= count
> 2047 ? 2047 : count
;
2892 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
2893 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
2894 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
2895 OUT_RINGp (chan
, map
, nr
);
2904 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
2906 struct pipe_screen
*pscreen
= nv50
->pipe
.screen
;
2908 if (!p
->data
[0] && p
->immd_nr
) {
2909 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
[0];
2911 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
2912 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
2913 struct nv50_program
*evict
= heap
->next
->priv
;
2914 nouveau_resource_free(&evict
->data
[0]);
2917 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
2922 /* immediates only need to be uploaded again when freed */
2923 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
2924 p
->immd_nr
, NV50_CB_PMISC
);
2927 assert(p
->param_nr
<= 512);
2931 float *map
= pipe_buffer_map(pscreen
, nv50
->constbuf
[p
->type
],
2932 PIPE_BUFFER_USAGE_CPU_READ
);
2934 if (p
->type
== PIPE_SHADER_VERTEX
)
2939 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
2940 pipe_buffer_unmap(pscreen
, nv50
->constbuf
[p
->type
]);
2945 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
2947 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
2948 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
2949 struct nv50_program_exec
*e
;
2950 struct nouveau_stateobj
*so
;
2951 const unsigned flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
;
2952 unsigned start
, count
, *up
, *ptr
;
2953 boolean upload
= FALSE
;
2956 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
2957 p
->exec_size
* 4, &p
->bo
);
2961 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
2967 for (e
= p
->exec_head
; e
; e
= e
->next
) {
2968 unsigned ei
, ci
, bs
;
2970 if (e
->param
.index
< 0)
2973 if (e
->param
.mask
== 0) {
2974 assert(!(e
->param
.index
& 1));
2975 /* seem to be 8 byte steps */
2976 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
2978 e
->inst
[0] &= 0xf0000fff;
2979 e
->inst
[0] |= ei
<< 12;
2983 bs
= (e
->inst
[1] >> 22) & 0x07;
2985 ei
= e
->param
.shift
>> 5;
2986 ci
= e
->param
.index
;
2988 ci
+= p
->data
[bs
]->start
;
2990 e
->inst
[ei
] &= ~e
->param
.mask
;
2991 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
2995 p
->data_start
[0] = p
->data
[0]->start
;
2997 #ifdef NV50_PROGRAM_DUMP
2998 NOUVEAU_ERR("-------\n");
2999 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3000 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
3002 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
3006 up
= ptr
= MALLOC(p
->exec_size
* 4);
3007 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3008 *(ptr
++) = e
->inst
[0];
3010 *(ptr
++) = e
->inst
[1];
3014 so_method(so
, nv50
->screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
3015 so_reloc (so
, p
->bo
, 0, flags
| NOUVEAU_BO_HIGH
, 0, 0);
3016 so_reloc (so
, p
->bo
, 0, flags
| NOUVEAU_BO_LOW
, 0, 0);
3017 so_data (so
, (NV50_CB_PUPLOAD
<< 16) | 0x0800); //(p->exec_size * 4));
3019 start
= 0; count
= p
->exec_size
;
3021 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3026 nr
= MIN2(count
, 2047);
3027 nr
= MIN2(chan
->pushbuf
->remaining
, nr
);
3028 if (chan
->pushbuf
->remaining
< (nr
+ 3)) {
3033 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
3034 OUT_RING (chan
, (start
<< 8) | NV50_CB_PUPLOAD
);
3035 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
3036 OUT_RINGp (chan
, up
+ start
, nr
);
3047 nv50_vertprog_validate(struct nv50_context
*nv50
)
3049 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3050 struct nv50_program
*p
= nv50
->vertprog
;
3051 struct nouveau_stateobj
*so
;
3053 if (!p
->translated
) {
3054 nv50_program_validate(nv50
, p
);
3059 nv50_program_validate_data(nv50
, p
);
3060 nv50_program_validate_code(nv50
, p
);
3063 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
3064 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3065 NOUVEAU_BO_HIGH
, 0, 0);
3066 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3067 NOUVEAU_BO_LOW
, 0, 0);
3068 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
3069 so_data (so
, p
->cfg
.attr
[0]);
3070 so_data (so
, p
->cfg
.attr
[1]);
3071 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
3072 so_data (so
, p
->cfg
.high_result
);
3073 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 2);
3074 so_data (so
, p
->cfg
.high_result
); //8);
3075 so_data (so
, p
->cfg
.high_temp
);
3076 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
3077 so_data (so
, 0); /* program start offset */
3078 so_ref(so
, &nv50
->state
.vertprog
);
3083 nv50_fragprog_validate(struct nv50_context
*nv50
)
3085 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3086 struct nv50_program
*p
= nv50
->fragprog
;
3087 struct nouveau_stateobj
*so
;
3089 if (!p
->translated
) {
3090 nv50_program_validate(nv50
, p
);
3095 nv50_program_validate_data(nv50
, p
);
3096 nv50_program_validate_code(nv50
, p
);
3099 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
3100 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3101 NOUVEAU_BO_HIGH
, 0, 0);
3102 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3103 NOUVEAU_BO_LOW
, 0, 0);
3104 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
3105 so_data (so
, p
->cfg
.high_temp
);
3106 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
3107 so_data (so
, p
->cfg
.high_result
);
3108 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK19A8
, 1);
3109 so_data (so
, p
->cfg
.regs
[2]);
3110 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
3111 so_data (so
, p
->cfg
.regs
[3]);
3112 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
3113 so_data (so
, 0); /* program start offset */
3114 so_ref(so
, &nv50
->state
.fragprog
);
3119 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
3121 struct nv50_program
*fp
= nv50
->fragprog
;
3122 struct nv50_program
*vp
= nv50
->vertprog
;
3123 unsigned i
, c
, m
= base
;
3125 /* XXX: This can't work correctly in all cases yet, we either
3126 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
3127 * to be per FP input instead of per VP output
3129 memset(pntc
, 0, 8 * sizeof(uint32_t));
3131 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
3133 uint8_t j
= fp
->cfg
.io
[i
].id_vp
, k
= fp
->cfg
.io
[i
].id_fp
;
3134 unsigned n
= popcnt4(fp
->cfg
.io
[i
].mask
);
3136 if (fp
->info
.input_semantic_name
[k
] != TGSI_SEMANTIC_GENERIC
) {
3141 sn
= vp
->info
.input_semantic_name
[j
];
3142 si
= vp
->info
.input_semantic_index
[j
];
3144 if (j
< fp
->cfg
.io_nr
&& sn
== TGSI_SEMANTIC_GENERIC
) {
3146 nv50
->rasterizer
->pipe
.sprite_coord_mode
[si
];
3148 if (mode
== PIPE_SPRITE_COORD_NONE
) {
3154 /* this is either PointCoord or replaced by sprite coords */
3155 for (c
= 0; c
< 4; c
++) {
3156 if (!(fp
->cfg
.io
[i
].mask
& (1 << c
)))
3158 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
3165 nv50_sreg4_map(uint32_t *p_map
, int mid
, uint32_t lin
[4],
3166 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
3169 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
3170 uint8_t *map
= (uint8_t *)p_map
;
3172 for (c
= 0; c
< 4; ++c
) {
3174 if (fpi
->linear
== TRUE
)
3175 lin
[mid
/ 32] |= 1 << (mid
% 32);
3176 map
[mid
++] = (mv
& 1) ? oid
: ((c
== 3) ? 0x41 : 0x40);
3188 nv50_linkage_validate(struct nv50_context
*nv50
)
3190 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3191 struct nv50_program
*vp
= nv50
->vertprog
;
3192 struct nv50_program
*fp
= nv50
->fragprog
;
3193 struct nouveau_stateobj
*so
;
3194 struct nv50_sreg4 dummy
, *vpo
;
3196 uint32_t map
[16], lin
[4], reg
[5], pcrd
[8];
3198 memset(map
, 0, sizeof(map
));
3199 memset(lin
, 0, sizeof(lin
));
3201 reg
[1] = 0x00000004; /* low and high clip distance map ids */
3202 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3203 reg
[3] = 0x00000000; /* point size map id & enable */
3204 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
3205 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
3207 dummy
.linear
= FALSE
;
3208 dummy
.mask
= 0xf; /* map all components of HPOS */
3209 m
= nv50_sreg4_map(map
, m
, lin
, &dummy
, &vp
->cfg
.io
[0]);
3213 if (vp
->cfg
.clpd
< 0x40) {
3214 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
)
3215 map
[m
++] = vp
->cfg
.clpd
+ c
;
3219 reg
[0] |= m
<< 8; /* adjust BFC0 id */
3221 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3222 if (nv50
->rasterizer
->pipe
.light_twoside
) {
3223 vpo
= &vp
->cfg
.two_side
[0];
3225 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[0], &vpo
[0]);
3226 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[1], &vpo
[1]);
3229 reg
[0] += m
- 4; /* adjust FFC0 id */
3230 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
3233 if (fp
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
)
3235 for (; i
< fp
->cfg
.io_nr
; i
++) {
3236 ubyte sn
= fp
->info
.input_semantic_name
[fp
->cfg
.io
[i
].id_fp
];
3237 ubyte si
= fp
->info
.input_semantic_index
[fp
->cfg
.io
[i
].id_fp
];
3239 n
= fp
->cfg
.io
[i
].id_vp
;
3240 if (n
>= vp
->cfg
.io_nr
||
3241 vp
->info
.output_semantic_name
[n
] != sn
||
3242 vp
->info
.output_semantic_index
[n
] != si
)
3245 vpo
= &vp
->cfg
.io
[n
];
3247 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.io
[i
], vpo
);
3250 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
3251 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
3252 reg
[3] = (m
++ << 4) | 1;
3255 /* now fill the stateobj */
3259 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
3261 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
3262 so_datap (so
, map
, n
);
3264 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
3265 so_datap (so
, reg
, 4);
3267 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
3268 so_data (so
, reg
[4]);
3270 so_method(so
, tesla
, 0x1540, 4);
3271 so_datap (so
, lin
, 4);
3273 if (nv50
->rasterizer
->pipe
.point_sprite
) {
3274 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff);
3276 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3277 so_datap (so
, pcrd
, 8);
3280 so_ref(so
, &nv50
->state
.programs
);
3285 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
3287 while (p
->exec_head
) {
3288 struct nv50_program_exec
*e
= p
->exec_head
;
3290 p
->exec_head
= e
->next
;
3293 p
->exec_tail
= NULL
;
3296 nouveau_bo_ref(NULL
, &p
->bo
);
3298 nouveau_resource_free(&p
->data
[0]);