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nv50: handle all and more system values
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95
96 int vtx; /* vertex index, for GP inputs (TGSI Dimension.Index) */
97 int indirect[2]; /* index into pc->addr, or -1 */
98 };
99
100 #define NV50_MOD_NEG 1
101 #define NV50_MOD_ABS 2
102 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
103 #define NV50_MOD_SAT 4
104 #define NV50_MOD_I32 8
105
106 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
107
108 /* STACK: Conditionals and loops have to use the (per warp) stack.
109 * Stack entries consist of an entry type (divergent path, join at),
110 * a mask indicating the active threads of the warp, and an address.
111 * MPs can store 12 stack entries internally, if we need more (and
112 * we probably do), we have to create a stack buffer in VRAM.
113 */
114 /* impose low limits for now */
115 #define NV50_MAX_COND_NESTING 4
116 #define NV50_MAX_LOOP_NESTING 3
117
118 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
119
120 struct nv50_pc {
121 struct nv50_program *p;
122
123 /* hw resources */
124 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
125 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
126
127 /* tgsi resources */
128 struct nv50_reg *temp;
129 int temp_nr;
130 struct nv50_reg *attr;
131 int attr_nr;
132 struct nv50_reg *result;
133 int result_nr;
134 struct nv50_reg *param;
135 int param_nr;
136 struct nv50_reg *immd;
137 uint32_t *immd_buf;
138 int immd_nr;
139 struct nv50_reg **addr;
140 int addr_nr;
141 struct nv50_reg *sysval;
142 int sysval_nr;
143
144 struct nv50_reg *temp_temp[16];
145 struct nv50_program_exec *temp_temp_exec[16];
146 unsigned temp_temp_nr;
147
148 /* broadcast and destination replacement regs */
149 struct nv50_reg *r_brdc;
150 struct nv50_reg *r_dst[4];
151
152 struct nv50_reg reg_instances[16];
153 unsigned reg_instance_nr;
154
155 unsigned interp_mode[32];
156 /* perspective interpolation registers */
157 struct nv50_reg *iv_p;
158 struct nv50_reg *iv_c;
159
160 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
161 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
162 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
163 int if_lvl, loop_lvl;
164 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
165
166 unsigned *insn_pos; /* actual program offset of each TGSI insn */
167 boolean in_subroutine;
168
169 /* current instruction and total number of insns */
170 unsigned insn_cur;
171 unsigned insn_nr;
172
173 boolean allow32;
174
175 uint8_t edgeflag_out;
176 };
177
178 static struct nv50_reg *get_address_reg(struct nv50_pc *, struct nv50_reg *);
179
180 static INLINE void
181 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
182 {
183 reg->type = type;
184 reg->index = index;
185 reg->hw = hw;
186 reg->mod = 0;
187 reg->rhw = -1;
188 reg->vtx = -1;
189 reg->acc = 0;
190 reg->indirect[0] = reg->indirect[1] = -1;
191 }
192
193 static INLINE unsigned
194 popcnt4(uint32_t val)
195 {
196 static const unsigned cnt[16]
197 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
198 return cnt[val & 0xf];
199 }
200
201 static void
202 terminate_mbb(struct nv50_pc *pc)
203 {
204 int i;
205
206 /* remove records of temporary address register values */
207 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
208 if (pc->r_addr[i].index < 0)
209 pc->r_addr[i].acc = 0;
210 }
211
212 static void
213 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
214 {
215 int i = 0;
216
217 if (reg->type == P_RESULT) {
218 if (pc->p->cfg.high_result < (reg->hw + 1))
219 pc->p->cfg.high_result = reg->hw + 1;
220 }
221
222 if (reg->type != P_TEMP)
223 return;
224
225 if (reg->hw >= 0) {
226 /*XXX: do this here too to catch FP temp-as-attr usage..
227 * not clean, but works */
228 if (pc->p->cfg.high_temp < (reg->hw + 1))
229 pc->p->cfg.high_temp = reg->hw + 1;
230 return;
231 }
232
233 if (reg->rhw != -1) {
234 /* try to allocate temporary with index rhw first */
235 if (!(pc->r_temp[reg->rhw])) {
236 pc->r_temp[reg->rhw] = reg;
237 reg->hw = reg->rhw;
238 if (pc->p->cfg.high_temp < (reg->rhw + 1))
239 pc->p->cfg.high_temp = reg->rhw + 1;
240 return;
241 }
242 /* make sure we don't get things like $r0 needs to go
243 * in $r1 and $r1 in $r0
244 */
245 i = pc->result_nr * 4;
246 }
247
248 for (; i < NV50_SU_MAX_TEMP; i++) {
249 if (!(pc->r_temp[i])) {
250 pc->r_temp[i] = reg;
251 reg->hw = i;
252 if (pc->p->cfg.high_temp < (i + 1))
253 pc->p->cfg.high_temp = i + 1;
254 return;
255 }
256 }
257
258 NOUVEAU_ERR("out of registers\n");
259 abort();
260 }
261
262 static INLINE struct nv50_reg *
263 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
264 {
265 struct nv50_reg *ri;
266
267 assert(pc->reg_instance_nr < 16);
268 ri = &pc->reg_instances[pc->reg_instance_nr++];
269 if (reg) {
270 alloc_reg(pc, reg);
271 *ri = *reg;
272 reg->indirect[0] = reg->indirect[1] = -1;
273 reg->mod = 0;
274 }
275 return ri;
276 }
277
278 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
279 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
280 * lest we risk temp_temps overwriting regs alloc'd "later".
281 */
282 static struct nv50_reg *
283 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
284 {
285 struct nv50_reg *r;
286 int i;
287
288 if (dst && dst->type == P_TEMP && dst->hw == -1)
289 return dst;
290
291 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
292 if (!pc->r_temp[i]) {
293 r = MALLOC_STRUCT(nv50_reg);
294 ctor_reg(r, P_TEMP, -1, i);
295 pc->r_temp[i] = r;
296 return r;
297 }
298 }
299
300 NOUVEAU_ERR("out of registers\n");
301 abort();
302 return NULL;
303 }
304
305 /* release the hardware resource held by r */
306 static void
307 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
308 {
309 assert(r->type == P_TEMP);
310 if (r->hw == -1)
311 return;
312
313 assert(pc->r_temp[r->hw] == r);
314 pc->r_temp[r->hw] = NULL;
315
316 r->acc = 0;
317 if (r->index == -1)
318 FREE(r);
319 }
320
321 static void
322 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
323 {
324 if (r->index == -1) {
325 unsigned hw = r->hw;
326
327 FREE(pc->r_temp[hw]);
328 pc->r_temp[hw] = NULL;
329 }
330 }
331
332 static int
333 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
334 {
335 int i;
336
337 if ((idx + 4) >= NV50_SU_MAX_TEMP)
338 return 1;
339
340 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
341 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
342 return alloc_temp4(pc, dst, idx + 4);
343
344 for (i = 0; i < 4; i++) {
345 dst[i] = MALLOC_STRUCT(nv50_reg);
346 ctor_reg(dst[i], P_TEMP, -1, idx + i);
347 pc->r_temp[idx + i] = dst[i];
348 }
349
350 return 0;
351 }
352
353 static void
354 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
355 {
356 int i;
357
358 for (i = 0; i < 4; i++)
359 free_temp(pc, reg[i]);
360 }
361
362 static struct nv50_reg *
363 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
364 {
365 if (pc->temp_temp_nr >= 16)
366 assert(0);
367
368 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
369 pc->temp_temp_exec[pc->temp_temp_nr] = e;
370 return pc->temp_temp[pc->temp_temp_nr++];
371 }
372
373 /* This *must* be called for all nv50_program_exec that have been
374 * given as argument to temp_temp, or the temps will be leaked !
375 */
376 static void
377 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
378 {
379 int i;
380
381 for (i = 0; i < pc->temp_temp_nr; i++)
382 if (pc->temp_temp_exec[i] == e)
383 free_temp(pc, pc->temp_temp[i]);
384 if (!e)
385 pc->temp_temp_nr = 0;
386 }
387
388 static int
389 ctor_immd_4u32(struct nv50_pc *pc,
390 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
391 {
392 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
393
394 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
395
396 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
397 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
398 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
399 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
400
401 return pc->immd_nr++;
402 }
403
404 static INLINE int
405 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
406 {
407 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
408 }
409
410 static struct nv50_reg *
411 alloc_immd(struct nv50_pc *pc, float f)
412 {
413 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
414 unsigned hw;
415
416 for (hw = 0; hw < pc->immd_nr * 4; hw++)
417 if (pc->immd_buf[hw] == fui(f))
418 break;
419
420 if (hw == pc->immd_nr * 4)
421 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
422
423 ctor_reg(r, P_IMMD, -1, hw);
424 return r;
425 }
426
427 static struct nv50_program_exec *
428 exec(struct nv50_pc *pc)
429 {
430 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
431
432 e->param.index = -1;
433 return e;
434 }
435
436 static void
437 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
438 {
439 struct nv50_program *p = pc->p;
440
441 if (p->exec_tail)
442 p->exec_tail->next = e;
443 if (!p->exec_head)
444 p->exec_head = e;
445 p->exec_tail = e;
446 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
447
448 kill_temp_temp(pc, e);
449 }
450
451 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
452
453 static boolean
454 is_long(struct nv50_program_exec *e)
455 {
456 if (e->inst[0] & 1)
457 return TRUE;
458 return FALSE;
459 }
460
461 static boolean
462 is_immd(struct nv50_program_exec *e)
463 {
464 if (is_long(e) && (e->inst[1] & 3) == 3)
465 return TRUE;
466 return FALSE;
467 }
468
469 static boolean
470 is_join(struct nv50_program_exec *e)
471 {
472 if (is_long(e) && (e->inst[1] & 3) == 2)
473 return TRUE;
474 return FALSE;
475 }
476
477 static INLINE void
478 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
479 struct nv50_program_exec *e)
480 {
481 assert(!is_immd(e));
482 set_long(pc, e);
483 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
484 e->inst[1] |= (pred << 7) | (idx << 12);
485 }
486
487 static INLINE void
488 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
489 struct nv50_program_exec *e)
490 {
491 set_long(pc, e);
492 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
493 e->inst[1] |= (idx << 4) | (on << 6);
494 }
495
496 static INLINE void
497 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
498 {
499 if (is_long(e))
500 return;
501
502 e->inst[0] |= 1;
503 set_pred(pc, 0xf, 0, e);
504 set_pred_wr(pc, 0, 0, e);
505 }
506
507 static INLINE void
508 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
509 {
510 if (dst->type == P_RESULT) {
511 set_long(pc, e);
512 e->inst[1] |= 0x00000008;
513 }
514
515 alloc_reg(pc, dst);
516 if (dst->hw > 63)
517 set_long(pc, e);
518 e->inst[0] |= (dst->hw << 2);
519 }
520
521 static INLINE void
522 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
523 {
524 set_long(pc, e);
525 /* XXX: can't be predicated - bits overlap; cases where both
526 * are required should be avoided by using pc->allow32 */
527 set_pred(pc, 0, 0, e);
528 set_pred_wr(pc, 0, 0, e);
529
530 e->inst[1] |= 0x00000002 | 0x00000001;
531 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
532 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
533 }
534
535 static INLINE void
536 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
537 {
538 assert(a->type == P_ADDR);
539
540 assert(!(e->inst[0] & 0x0c000000));
541 assert(!(e->inst[1] & 0x00000004));
542
543 e->inst[0] |= (a->hw & 3) << 26;
544 e->inst[1] |= a->hw & 4;
545 }
546
547 static void
548 emit_arl(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, uint8_t);
549
550 static void
551 emit_shl_imm(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, int);
552
553 static void
554 emit_mov_from_addr(struct nv50_pc *pc, struct nv50_reg *dst,
555 struct nv50_reg *src)
556 {
557 struct nv50_program_exec *e = exec(pc);
558
559 e->inst[1] = 0x40000000;
560 set_long(pc, e);
561 set_dst(pc, dst, e);
562 set_addr(e, src);
563
564 emit(pc, e);
565 }
566
567 static void
568 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
569 struct nv50_reg *src0, uint16_t src1_val)
570 {
571 struct nv50_program_exec *e = exec(pc);
572
573 e->inst[0] = 0xd0000000 | (src1_val << 9);
574 e->inst[1] = 0x20000000;
575 set_long(pc, e);
576 e->inst[0] |= dst->hw << 2;
577 if (src0) /* otherwise will add to $a0, which is always 0 */
578 set_addr(e, src0);
579
580 emit(pc, e);
581 }
582
583 #define INTERP_LINEAR 0
584 #define INTERP_FLAT 1
585 #define INTERP_PERSPECTIVE 2
586 #define INTERP_CENTROID 4
587
588 /* interpolant index has been stored in dst->rhw */
589 static void
590 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
591 unsigned mode)
592 {
593 assert(dst->rhw != -1);
594 struct nv50_program_exec *e = exec(pc);
595
596 e->inst[0] |= 0x80000000;
597 set_dst(pc, dst, e);
598 e->inst[0] |= (dst->rhw << 16);
599
600 if (mode & INTERP_FLAT) {
601 e->inst[0] |= (1 << 8);
602 } else {
603 if (mode & INTERP_PERSPECTIVE) {
604 e->inst[0] |= (1 << 25);
605 alloc_reg(pc, iv);
606 e->inst[0] |= (iv->hw << 9);
607 }
608
609 if (mode & INTERP_CENTROID)
610 e->inst[0] |= (1 << 24);
611 }
612
613 emit(pc, e);
614 }
615
616 static void
617 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
618 struct nv50_program_exec *e)
619 {
620 set_long(pc, e);
621
622 e->param.index = src->hw & 127;
623 e->param.shift = s;
624 e->param.mask = m << (s % 32);
625
626 if (src->hw < 0 || src->hw > 127) /* need (additional) address reg */
627 set_addr(e, get_address_reg(pc, src));
628 else
629 if (src->acc < 0) {
630 assert(src->type == P_CONST);
631 set_addr(e, pc->addr[src->indirect[0]]);
632 }
633
634 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
635 }
636
637 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
638 static void
639 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
640 {
641 struct nv50_program_exec *e = exec(pc);
642
643 e->inst[0] = 0x10000000;
644 if (!pc->allow32)
645 set_long(pc, e);
646
647 set_dst(pc, dst, e);
648
649 if (!is_long(e) && src->type == P_IMMD) {
650 set_immd(pc, src, e);
651 /*XXX: 32-bit, but steals part of "half" reg space - need to
652 * catch and handle this case if/when we do half-regs
653 */
654 } else
655 if (src->type == P_IMMD || src->type == P_CONST) {
656 set_long(pc, e);
657 set_data(pc, src, 0x7f, 9, e);
658 e->inst[1] |= 0x20000000; /* mov from c[] */
659 } else {
660 if (src->type == P_ATTR) {
661 set_long(pc, e);
662 e->inst[1] |= 0x00200000;
663
664 if (src->vtx >= 0) {
665 /* indirect (vertex base + c) load from p[] */
666 e->inst[0] |= 0x01800000;
667 set_addr(e, get_address_reg(pc, src));
668 }
669 }
670
671 alloc_reg(pc, src);
672 if (src->hw > 63)
673 set_long(pc, e);
674 e->inst[0] |= (src->hw << 9);
675 }
676
677 if (is_long(e) && !is_immd(e)) {
678 e->inst[1] |= 0x04000000; /* 32-bit */
679 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
680 if (!(e->inst[1] & 0x20000000))
681 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
682 } else
683 e->inst[0] |= 0x00008000;
684
685 emit(pc, e);
686 }
687
688 static INLINE void
689 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
690 {
691 struct nv50_reg *imm = alloc_immd(pc, f);
692 emit_mov(pc, dst, imm);
693 FREE(imm);
694 }
695
696 /* Assign the hw of the discarded temporary register src
697 * to the tgsi register dst and free src.
698 */
699 static void
700 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
701 {
702 assert(src->index == -1 && src->hw != -1);
703
704 if (pc->if_lvl || pc->loop_lvl ||
705 (dst->type != P_TEMP) ||
706 (src->hw < pc->result_nr * 4 &&
707 pc->p->type == PIPE_SHADER_FRAGMENT) ||
708 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
709 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
710
711 emit_mov(pc, dst, src);
712 free_temp(pc, src);
713 return;
714 }
715
716 if (dst->hw != -1)
717 pc->r_temp[dst->hw] = NULL;
718 pc->r_temp[src->hw] = dst;
719 dst->hw = src->hw;
720
721 FREE(src);
722 }
723
724 static void
725 emit_nop(struct nv50_pc *pc)
726 {
727 struct nv50_program_exec *e = exec(pc);
728
729 e->inst[0] = 0xf0000000;
730 set_long(pc, e);
731 e->inst[1] = 0xe0000000;
732 emit(pc, e);
733 }
734
735 static boolean
736 check_swap_src_0_1(struct nv50_pc *pc,
737 struct nv50_reg **s0, struct nv50_reg **s1)
738 {
739 struct nv50_reg *src0 = *s0, *src1 = *s1;
740
741 if (src0->type == P_CONST) {
742 if (src1->type != P_CONST) {
743 *s0 = src1;
744 *s1 = src0;
745 return TRUE;
746 }
747 } else
748 if (src1->type == P_ATTR) {
749 if (src0->type != P_ATTR) {
750 *s0 = src1;
751 *s1 = src0;
752 return TRUE;
753 }
754 }
755
756 return FALSE;
757 }
758
759 static void
760 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
761 struct nv50_program_exec *e)
762 {
763 struct nv50_reg *temp;
764
765 if (src->type != P_TEMP) {
766 temp = temp_temp(pc, e);
767 emit_mov(pc, temp, src);
768 src = temp;
769 }
770
771 alloc_reg(pc, src);
772 if (src->hw > 63)
773 set_long(pc, e);
774 e->inst[0] |= (src->hw << 9);
775 }
776
777 static void
778 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
779 {
780 if (src->type == P_ATTR) {
781 set_long(pc, e);
782 e->inst[1] |= 0x00200000;
783
784 if (src->vtx >= 0) {
785 e->inst[0] |= 0x01800000; /* src from p[] */
786 set_addr(e, get_address_reg(pc, src));
787 }
788 } else
789 if (src->type == P_CONST || src->type == P_IMMD) {
790 struct nv50_reg *temp = temp_temp(pc, e);
791
792 emit_mov(pc, temp, src);
793 src = temp;
794 }
795
796 alloc_reg(pc, src);
797 if (src->hw > 63)
798 set_long(pc, e);
799 e->inst[0] |= (src->hw << 9);
800 }
801
802 static void
803 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
804 {
805 if (src->type == P_ATTR) {
806 struct nv50_reg *temp = temp_temp(pc, e);
807
808 emit_mov(pc, temp, src);
809 src = temp;
810 } else
811 if (src->type == P_CONST || src->type == P_IMMD) {
812 if (e->inst[0] & 0x01800000) {
813 struct nv50_reg *temp = temp_temp(pc, e);
814
815 emit_mov(pc, temp, src);
816 src = temp;
817 } else {
818 assert(!(e->inst[0] & 0x00800000));
819 set_data(pc, src, 0x7f, 16, e);
820 e->inst[0] |= 0x00800000;
821 }
822 }
823
824 alloc_reg(pc, src);
825 if (src->hw > 63)
826 set_long(pc, e);
827 e->inst[0] |= ((src->hw & 127) << 16);
828 }
829
830 static void
831 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
832 {
833 set_long(pc, e);
834
835 if (src->type == P_ATTR) {
836 struct nv50_reg *temp = temp_temp(pc, e);
837
838 emit_mov(pc, temp, src);
839 src = temp;
840 } else
841 if (src->type == P_CONST || src->type == P_IMMD) {
842 if (e->inst[0] & 0x01800000) {
843 struct nv50_reg *temp = temp_temp(pc, e);
844
845 emit_mov(pc, temp, src);
846 src = temp;
847 } else {
848 assert(!(e->inst[0] & 0x01000000));
849 set_data(pc, src, 0x7f, 32+14, e);
850 e->inst[0] |= 0x01000000;
851 }
852 }
853
854 alloc_reg(pc, src);
855 e->inst[1] |= ((src->hw & 127) << 14);
856 }
857
858 static void
859 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
860 struct nv50_program_exec *e, int pos)
861 {
862 struct nv50_reg *r = src;
863
864 alloc_reg(pc, r);
865 if (r->type != P_TEMP) {
866 r = temp_temp(pc, e);
867 emit_mov(pc, r, src);
868 }
869
870 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
871 NOUVEAU_ERR("out of low GPRs\n");
872 abort();
873 }
874
875 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
876 }
877
878 static void
879 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
880 {
881 struct nv50_program_exec *e = exec(pc);
882
883 assert(dst->type == P_TEMP);
884 e->inst[1] = 0x20000000 | (pred << 12);
885 set_long(pc, e);
886 set_dst(pc, dst, e);
887
888 emit(pc, e);
889 }
890
891 static void
892 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
893 {
894 struct nv50_program_exec *e = exec(pc);
895
896 e->inst[0] = 0x000001fc;
897 e->inst[1] = 0xa0000008;
898 set_long(pc, e);
899 set_pred_wr(pc, 1, pred, e);
900 set_src_0_restricted(pc, src, e);
901
902 emit(pc, e);
903 }
904
905 static void
906 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
907 struct nv50_reg *src1)
908 {
909 struct nv50_program_exec *e = exec(pc);
910
911 e->inst[0] |= 0xc0000000;
912
913 if (!pc->allow32)
914 set_long(pc, e);
915
916 check_swap_src_0_1(pc, &src0, &src1);
917 set_dst(pc, dst, e);
918 set_src_0(pc, src0, e);
919 if (src1->type == P_IMMD && !is_long(e)) {
920 if (src0->mod ^ src1->mod)
921 e->inst[0] |= 0x00008000;
922 set_immd(pc, src1, e);
923 } else {
924 set_src_1(pc, src1, e);
925 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
926 if (is_long(e))
927 e->inst[1] |= 0x08000000;
928 else
929 e->inst[0] |= 0x00008000;
930 }
931 }
932
933 emit(pc, e);
934 }
935
936 static void
937 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
938 struct nv50_reg *src0, struct nv50_reg *src1)
939 {
940 struct nv50_program_exec *e = exec(pc);
941
942 e->inst[0] = 0xb0000000;
943
944 alloc_reg(pc, src1);
945 check_swap_src_0_1(pc, &src0, &src1);
946
947 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
948 set_long(pc, e);
949 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
950 ((src1->mod & NV50_MOD_NEG) << 27);
951 }
952
953 set_dst(pc, dst, e);
954 set_src_0(pc, src0, e);
955 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
956 set_src_2(pc, src1, e);
957 else
958 if (src1->type == P_IMMD)
959 set_immd(pc, src1, e);
960 else
961 set_src_1(pc, src1, e);
962
963 emit(pc, e);
964 }
965
966 static void
967 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
968 uint8_t s)
969 {
970 struct nv50_program_exec *e = exec(pc);
971
972 set_long(pc, e);
973 e->inst[1] |= 0xc0000000;
974
975 e->inst[0] |= dst->hw << 2;
976 e->inst[0] |= s << 16; /* shift left */
977 set_src_0(pc, src, e);
978
979 emit(pc, e);
980 }
981
982 static boolean
983 address_reg_suitable(struct nv50_reg *a, struct nv50_reg *r)
984 {
985 if (!r)
986 return FALSE;
987
988 if (r->vtx != a->vtx)
989 return FALSE;
990 if (r->vtx >= 0)
991 return (r->indirect[1] == a->indirect[1]);
992
993 if (r->hw < a->rhw || (r->hw - a->rhw) >= 128)
994 return FALSE;
995
996 if (a->index >= 0)
997 return (a->index == r->indirect[0]);
998 return (a->indirect[0] == r->indirect[0]);
999 }
1000
1001 static void
1002 load_vertex_base(struct nv50_pc *pc, struct nv50_reg *dst,
1003 struct nv50_reg *a, int shift)
1004 {
1005 struct nv50_reg mem, *temp;
1006
1007 ctor_reg(&mem, P_ATTR, -1, dst->vtx);
1008
1009 assert(dst->type == P_ADDR);
1010 if (!a) {
1011 emit_arl(pc, dst, &mem, 0);
1012 return;
1013 }
1014 temp = alloc_temp(pc, NULL);
1015
1016 if (shift) {
1017 emit_mov_from_addr(pc, temp, a);
1018 if (shift < 0)
1019 emit_shl_imm(pc, temp, temp, shift);
1020 emit_arl(pc, dst, temp, MAX2(shift, 0));
1021 }
1022 emit_mov(pc, temp, &mem);
1023 set_addr(pc->p->exec_tail, dst);
1024
1025 emit_arl(pc, dst, temp, 0);
1026 free_temp(pc, temp);
1027 }
1028
1029 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1030 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1031 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1032 * case (vtx < 0, acc >= 0): memory address too high to encode
1033 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1034 */
1035 static struct nv50_reg *
1036 get_address_reg(struct nv50_pc *pc, struct nv50_reg *ref)
1037 {
1038 int i;
1039 struct nv50_reg *a_ref, *a = NULL;
1040
1041 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
1042 if (pc->r_addr[i].acc == 0)
1043 a = &pc->r_addr[i]; /* an unused address reg */
1044 else
1045 if (address_reg_suitable(&pc->r_addr[i], ref)) {
1046 pc->r_addr[i].acc = pc->insn_cur;
1047 return &pc->r_addr[i];
1048 } else
1049 if (!a && pc->r_addr[i].index < 0 &&
1050 pc->r_addr[i].acc < pc->insn_cur)
1051 a = &pc->r_addr[i];
1052 }
1053 if (!a) {
1054 /* We'll be able to spill address regs when this
1055 * mess is replaced with a proper compiler ...
1056 */
1057 NOUVEAU_ERR("out of address regs\n");
1058 abort();
1059 return NULL;
1060 }
1061
1062 /* initialize and reserve for this TGSI instruction */
1063 a->rhw = 0;
1064 a->index = a->indirect[0] = a->indirect[1] = -1;
1065 a->acc = pc->insn_cur;
1066
1067 if (!ref) {
1068 a->vtx = -1;
1069 return a;
1070 }
1071 a->vtx = ref->vtx;
1072
1073 /* now put in the correct value ... */
1074
1075 if (ref->vtx >= 0) {
1076 a->indirect[1] = ref->indirect[1];
1077
1078 /* For an indirect vertex index, we need to shift address right
1079 * by 2, the address register will contain vtx * 16, we need to
1080 * load from a[vtx * 4].
1081 */
1082 load_vertex_base(pc, a, (ref->acc < 0) ?
1083 pc->addr[ref->indirect[1]] : NULL, -2);
1084 } else {
1085 assert(ref->acc < 0 || ref->indirect[0] < 0);
1086
1087 a->rhw = ref->hw & ~0x7f;
1088 a->indirect[0] = ref->indirect[0];
1089 a_ref = (ref->acc < 0) ? pc->addr[ref->indirect[0]] : NULL;
1090
1091 emit_add_addr_imm(pc, a, a_ref, a->rhw * 4);
1092 }
1093 return a;
1094 }
1095
1096 #define NV50_MAX_F32 0x880
1097 #define NV50_MAX_S32 0x08c
1098 #define NV50_MAX_U32 0x084
1099 #define NV50_MIN_F32 0x8a0
1100 #define NV50_MIN_S32 0x0ac
1101 #define NV50_MIN_U32 0x0a4
1102
1103 static void
1104 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1105 struct nv50_reg *src0, struct nv50_reg *src1)
1106 {
1107 struct nv50_program_exec *e = exec(pc);
1108
1109 set_long(pc, e);
1110 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1111 e->inst[1] |= (sub << 24);
1112
1113 check_swap_src_0_1(pc, &src0, &src1);
1114 set_dst(pc, dst, e);
1115 set_src_0(pc, src0, e);
1116 set_src_1(pc, src1, e);
1117
1118 if (src0->mod & NV50_MOD_ABS)
1119 e->inst[1] |= 0x00100000;
1120 if (src1->mod & NV50_MOD_ABS)
1121 e->inst[1] |= 0x00080000;
1122
1123 emit(pc, e);
1124 }
1125
1126 static INLINE void
1127 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1128 struct nv50_reg *src1)
1129 {
1130 src1->mod ^= NV50_MOD_NEG;
1131 emit_add(pc, dst, src0, src1);
1132 src1->mod ^= NV50_MOD_NEG;
1133 }
1134
1135 static void
1136 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1137 struct nv50_reg *src1, unsigned op)
1138 {
1139 struct nv50_program_exec *e = exec(pc);
1140
1141 e->inst[0] = 0xd0000000;
1142 set_long(pc, e);
1143
1144 check_swap_src_0_1(pc, &src0, &src1);
1145 set_dst(pc, dst, e);
1146 set_src_0(pc, src0, e);
1147
1148 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1149 op != TGSI_OPCODE_XOR)
1150 assert(!"invalid bit op");
1151
1152 assert(!(src0->mod | src1->mod));
1153
1154 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1155 set_immd(pc, src1, e);
1156 if (op == TGSI_OPCODE_OR)
1157 e->inst[0] |= 0x0100;
1158 else
1159 if (op == TGSI_OPCODE_XOR)
1160 e->inst[0] |= 0x8000;
1161 } else {
1162 set_src_1(pc, src1, e);
1163 e->inst[1] |= 0x04000000; /* 32 bit */
1164 if (op == TGSI_OPCODE_OR)
1165 e->inst[1] |= 0x4000;
1166 else
1167 if (op == TGSI_OPCODE_XOR)
1168 e->inst[1] |= 0x8000;
1169 }
1170
1171 emit(pc, e);
1172 }
1173
1174 static void
1175 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1176 {
1177 struct nv50_program_exec *e = exec(pc);
1178
1179 e->inst[0] = 0xd0000000;
1180 e->inst[1] = 0x0402c000;
1181 set_long(pc, e);
1182 set_dst(pc, dst, e);
1183 set_src_1(pc, src, e);
1184
1185 emit(pc, e);
1186 }
1187
1188 static void
1189 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1190 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1191 {
1192 struct nv50_program_exec *e = exec(pc);
1193
1194 e->inst[0] = 0x30000000;
1195 e->inst[1] = 0xc4000000;
1196
1197 set_long(pc, e);
1198 set_dst(pc, dst, e);
1199 set_src_0(pc, src0, e);
1200
1201 if (src1->type == P_IMMD) {
1202 e->inst[1] |= (1 << 20);
1203 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1204 } else
1205 set_src_1(pc, src1, e);
1206
1207 if (dir != TGSI_OPCODE_SHL)
1208 e->inst[1] |= (1 << 29);
1209
1210 if (dir == TGSI_OPCODE_ISHR)
1211 e->inst[1] |= (1 << 27);
1212
1213 emit(pc, e);
1214 }
1215
1216 static void
1217 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1218 struct nv50_reg *src, int s)
1219 {
1220 struct nv50_program_exec *e = exec(pc);
1221
1222 e->inst[0] = 0x30000000;
1223 e->inst[1] = 0xc4100000;
1224 if (s < 0) {
1225 e->inst[1] |= 1 << 29;
1226 s = -s;
1227 }
1228 e->inst[1] |= ((s & 0x7f) << 16);
1229
1230 set_long(pc, e);
1231 set_dst(pc, dst, e);
1232 set_src_0(pc, src, e);
1233
1234 emit(pc, e);
1235 }
1236
1237 static void
1238 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1239 struct nv50_reg *src1, struct nv50_reg *src2)
1240 {
1241 struct nv50_program_exec *e = exec(pc);
1242
1243 e->inst[0] |= 0xe0000000;
1244
1245 check_swap_src_0_1(pc, &src0, &src1);
1246 set_dst(pc, dst, e);
1247 set_src_0(pc, src0, e);
1248 set_src_1(pc, src1, e);
1249 set_src_2(pc, src2, e);
1250
1251 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1252 e->inst[1] |= 0x04000000;
1253 if (src2->mod & NV50_MOD_NEG)
1254 e->inst[1] |= 0x08000000;
1255
1256 emit(pc, e);
1257 }
1258
1259 static INLINE void
1260 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1261 struct nv50_reg *src1, struct nv50_reg *src2)
1262 {
1263 src2->mod ^= NV50_MOD_NEG;
1264 emit_mad(pc, dst, src0, src1, src2);
1265 src2->mod ^= NV50_MOD_NEG;
1266 }
1267
1268 #define NV50_FLOP_RCP 0
1269 #define NV50_FLOP_RSQ 2
1270 #define NV50_FLOP_LG2 3
1271 #define NV50_FLOP_SIN 4
1272 #define NV50_FLOP_COS 5
1273 #define NV50_FLOP_EX2 6
1274
1275 /* rcp, rsqrt, lg2 support neg and abs */
1276 static void
1277 emit_flop(struct nv50_pc *pc, unsigned sub,
1278 struct nv50_reg *dst, struct nv50_reg *src)
1279 {
1280 struct nv50_program_exec *e = exec(pc);
1281
1282 e->inst[0] |= 0x90000000;
1283 if (sub || src->mod) {
1284 set_long(pc, e);
1285 e->inst[1] |= (sub << 29);
1286 }
1287
1288 set_dst(pc, dst, e);
1289 set_src_0_restricted(pc, src, e);
1290
1291 assert(!src->mod || sub < 4);
1292
1293 if (src->mod & NV50_MOD_NEG)
1294 e->inst[1] |= 0x04000000;
1295 if (src->mod & NV50_MOD_ABS)
1296 e->inst[1] |= 0x00100000;
1297
1298 emit(pc, e);
1299 }
1300
1301 static void
1302 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1303 {
1304 struct nv50_program_exec *e = exec(pc);
1305
1306 e->inst[0] |= 0xb0000000;
1307
1308 set_dst(pc, dst, e);
1309 set_src_0(pc, src, e);
1310 set_long(pc, e);
1311 e->inst[1] |= (6 << 29) | 0x00004000;
1312
1313 if (src->mod & NV50_MOD_NEG)
1314 e->inst[1] |= 0x04000000;
1315 if (src->mod & NV50_MOD_ABS)
1316 e->inst[1] |= 0x00100000;
1317
1318 emit(pc, e);
1319 }
1320
1321 static void
1322 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1323 {
1324 struct nv50_program_exec *e = exec(pc);
1325
1326 e->inst[0] |= 0xb0000000;
1327
1328 set_dst(pc, dst, e);
1329 set_src_0(pc, src, e);
1330 set_long(pc, e);
1331 e->inst[1] |= (6 << 29);
1332
1333 if (src->mod & NV50_MOD_NEG)
1334 e->inst[1] |= 0x04000000;
1335 if (src->mod & NV50_MOD_ABS)
1336 e->inst[1] |= 0x00100000;
1337
1338 emit(pc, e);
1339 }
1340
1341 #define CVT_RN (0x00 << 16)
1342 #define CVT_FLOOR (0x02 << 16)
1343 #define CVT_CEIL (0x04 << 16)
1344 #define CVT_TRUNC (0x06 << 16)
1345 #define CVT_SAT (0x08 << 16)
1346 #define CVT_ABS (0x10 << 16)
1347
1348 #define CVT_X32_X32 0x04004000
1349 #define CVT_X32_S32 0x04014000
1350 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1351 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1352 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1353 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1354 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1355 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1356 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1357 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1358
1359 #define CVT_NEG 0x20000000
1360 #define CVT_RI 0x08000000
1361
1362 static void
1363 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1364 int wp, uint32_t cvn)
1365 {
1366 struct nv50_program_exec *e;
1367
1368 e = exec(pc);
1369
1370 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1371 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1372
1373 e->inst[0] = 0xa0000000;
1374 e->inst[1] = cvn;
1375 set_long(pc, e);
1376 set_src_0(pc, src, e);
1377
1378 if (wp >= 0)
1379 set_pred_wr(pc, 1, wp, e);
1380
1381 if (dst)
1382 set_dst(pc, dst, e);
1383 else {
1384 e->inst[0] |= 0x000001fc;
1385 e->inst[1] |= 0x00000008;
1386 }
1387
1388 emit(pc, e);
1389 }
1390
1391 /* nv50 Condition codes:
1392 * 0x1 = LT
1393 * 0x2 = EQ
1394 * 0x3 = LE
1395 * 0x4 = GT
1396 * 0x5 = NE
1397 * 0x6 = GE
1398 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1399 * 0x8 = unordered bit (allows NaN)
1400 *
1401 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1402 */
1403 static void
1404 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1405 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1406 {
1407 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1408
1409 struct nv50_program_exec *e = exec(pc);
1410 struct nv50_reg *rdst;
1411
1412 assert(ccode < 16);
1413 if (check_swap_src_0_1(pc, &src0, &src1))
1414 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1415
1416 rdst = dst;
1417 if (dst && dst->type != P_TEMP)
1418 dst = alloc_temp(pc, NULL);
1419
1420 set_long(pc, e);
1421 e->inst[0] |= 0x30000000 | (mode << 24);
1422 e->inst[1] |= 0x60000000 | (ccode << 14);
1423
1424 if (wp >= 0)
1425 set_pred_wr(pc, 1, wp, e);
1426 if (dst)
1427 set_dst(pc, dst, e);
1428 else {
1429 e->inst[0] |= 0x000001fc;
1430 e->inst[1] |= 0x00000008;
1431 }
1432
1433 set_src_0(pc, src0, e);
1434 set_src_1(pc, src1, e);
1435
1436 emit(pc, e);
1437
1438 if (rdst && mode == 0x80) /* convert to float ? */
1439 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1440 if (rdst && rdst != dst)
1441 free_temp(pc, dst);
1442 }
1443
1444 static INLINE void
1445 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1446 {
1447 switch (op) {
1448 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1449 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1450 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1451 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1452 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1453 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1454
1455 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1456 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1457 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1458 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1459 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1460 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1461 default:
1462 assert(0);
1463 return;
1464 }
1465 }
1466
1467 static void
1468 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1469 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1470 {
1471 struct nv50_program_exec *e = exec(pc);
1472 struct nv50_reg *src1;
1473
1474 e->inst[0] = 0x20000000;
1475
1476 alloc_reg(pc, rsrc1);
1477 check_swap_src_0_1(pc, &src0, &rsrc1);
1478
1479 src1 = rsrc1;
1480 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1481 src1 = temp_temp(pc, e);
1482 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1483 }
1484
1485 if (!pc->allow32 || src1->hw > 63 ||
1486 (src1->type != P_TEMP && src1->type != P_IMMD))
1487 set_long(pc, e);
1488
1489 set_dst(pc, dst, e);
1490 set_src_0(pc, src0, e);
1491
1492 if (is_long(e)) {
1493 e->inst[1] |= 1 << 26;
1494 set_src_2(pc, src1, e);
1495 } else {
1496 e->inst[0] |= 0x8000;
1497 if (src1->type == P_IMMD)
1498 set_immd(pc, src1, e);
1499 else
1500 set_src_1(pc, src1, e);
1501 }
1502
1503 if (src0->mod & NV50_MOD_NEG)
1504 e->inst[0] |= 1 << 28;
1505 else
1506 if (src1->mod & NV50_MOD_NEG)
1507 e->inst[0] |= 1 << 22;
1508
1509 emit(pc, e);
1510 }
1511
1512 static void
1513 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1514 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1515 struct nv50_reg *src2)
1516 {
1517 struct nv50_program_exec *e = exec(pc);
1518
1519 e->inst[0] = 0x60000000;
1520 if (!pc->allow32)
1521 set_long(pc, e);
1522 set_dst(pc, dst, e);
1523
1524 set_half_src(pc, src0, lh_0, e, 9);
1525 set_half_src(pc, src1, lh_1, e, 16);
1526 alloc_reg(pc, src2);
1527 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1528 set_src_2(pc, src2, e);
1529
1530 emit(pc, e);
1531 }
1532
1533 static void
1534 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1535 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1536 {
1537 struct nv50_program_exec *e = exec(pc);
1538
1539 e->inst[0] = 0x40000000;
1540 set_long(pc, e);
1541 set_dst(pc, dst, e);
1542
1543 set_half_src(pc, src0, lh_0, e, 9);
1544 set_half_src(pc, src1, lh_1, e, 16);
1545
1546 emit(pc, e);
1547 }
1548
1549 static void
1550 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1551 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1552 {
1553 struct nv50_program_exec *e = exec(pc);
1554
1555 e->inst[0] = 0x50000000;
1556 if (!pc->allow32)
1557 set_long(pc, e);
1558 check_swap_src_0_1(pc, &src0, &src1);
1559 set_dst(pc, dst, e);
1560 set_src_0(pc, src0, e);
1561 set_src_1(pc, src1, e);
1562 alloc_reg(pc, src2);
1563 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1564 set_src_2(pc, src2, e);
1565
1566 if (is_long(e))
1567 e->inst[1] |= 0x0c << 24;
1568 else
1569 e->inst[0] |= 0x81 << 8;
1570
1571 emit(pc, e);
1572 }
1573
1574 static INLINE void
1575 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1576 {
1577 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1578 }
1579
1580 static void
1581 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1582 struct nv50_reg *v, struct nv50_reg *e)
1583 {
1584 struct nv50_reg *temp = alloc_temp(pc, NULL);
1585
1586 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1587 emit_mul(pc, temp, temp, e);
1588 emit_preex2(pc, temp, temp);
1589 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1590
1591 free_temp(pc, temp);
1592 }
1593
1594 static INLINE void
1595 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1596 {
1597 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1598 }
1599
1600 static void
1601 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1602 struct nv50_reg **src)
1603 {
1604 struct nv50_reg *one = alloc_immd(pc, 1.0);
1605 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1606 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1607 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1608 struct nv50_reg *tmp[4];
1609 boolean allow32 = pc->allow32;
1610
1611 pc->allow32 = FALSE;
1612
1613 if (mask & (3 << 1)) {
1614 tmp[0] = alloc_temp(pc, NULL);
1615 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1616 }
1617
1618 if (mask & (1 << 2)) {
1619 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1620
1621 tmp[1] = temp_temp(pc, NULL);
1622 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1623
1624 tmp[3] = temp_temp(pc, NULL);
1625 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1626 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1627
1628 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1629 emit_mov(pc, dst[2], zero);
1630 set_pred(pc, 3, 0, pc->p->exec_tail);
1631 }
1632
1633 if (mask & (1 << 1))
1634 assimilate_temp(pc, dst[1], tmp[0]);
1635 else
1636 if (mask & (1 << 2))
1637 free_temp(pc, tmp[0]);
1638
1639 pc->allow32 = allow32;
1640
1641 /* do this last, in case src[i,j] == dst[0,3] */
1642 if (mask & (1 << 0))
1643 emit_mov(pc, dst[0], one);
1644
1645 if (mask & (1 << 3))
1646 emit_mov(pc, dst[3], one);
1647
1648 FREE(pos128);
1649 FREE(neg128);
1650 FREE(zero);
1651 FREE(one);
1652 }
1653
1654 static void
1655 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1656 {
1657 struct nv50_program_exec *e;
1658 const int r_pred = 1;
1659
1660 e = exec(pc);
1661 e->inst[0] = 0x00000002; /* discard */
1662 set_long(pc, e); /* sets cond code to ALWAYS */
1663
1664 if (src) {
1665 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1666 /* write to predicate reg */
1667 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1668 }
1669
1670 emit(pc, e);
1671 }
1672
1673 static struct nv50_program_exec *
1674 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1675 {
1676 struct nv50_program_exec *e = exec(pc);
1677
1678 e->inst[0] = (op << 28) | 2;
1679 set_long(pc, e);
1680 if (pred >= 0)
1681 set_pred(pc, cc, pred, e);
1682
1683 emit(pc, e);
1684 return e;
1685 }
1686
1687 static INLINE struct nv50_program_exec *
1688 emit_breakaddr(struct nv50_pc *pc)
1689 {
1690 return emit_control_flow(pc, 0x4, -1, 0);
1691 }
1692
1693 static INLINE void
1694 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1695 {
1696 emit_control_flow(pc, 0x5, pred, cc);
1697 }
1698
1699 static INLINE struct nv50_program_exec *
1700 emit_joinat(struct nv50_pc *pc)
1701 {
1702 return emit_control_flow(pc, 0xa, -1, 0);
1703 }
1704
1705 static INLINE struct nv50_program_exec *
1706 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1707 {
1708 return emit_control_flow(pc, 0x1, pred, cc);
1709 }
1710
1711 static INLINE struct nv50_program_exec *
1712 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1713 {
1714 return emit_control_flow(pc, 0x2, pred, cc);
1715 }
1716
1717 static INLINE void
1718 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1719 {
1720 emit_control_flow(pc, 0x3, pred, cc);
1721 }
1722
1723 static void
1724 emit_prim_cmd(struct nv50_pc *pc, unsigned cmd)
1725 {
1726 struct nv50_program_exec *e = exec(pc);
1727
1728 e->inst[0] = 0xf0000000 | (cmd << 9);
1729 e->inst[1] = 0xc0000000;
1730 set_long(pc, e);
1731
1732 emit(pc, e);
1733 }
1734
1735 #define QOP_ADD 0
1736 #define QOP_SUBR 1
1737 #define QOP_SUB 2
1738 #define QOP_MOV_SRC1 3
1739
1740 /* For a quad of threads / top left, top right, bottom left, bottom right
1741 * pixels, do a different operation, and take src0 from a specific thread.
1742 */
1743 static void
1744 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1745 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1746 {
1747 struct nv50_program_exec *e = exec(pc);
1748
1749 e->inst[0] = 0xc0000000;
1750 e->inst[1] = 0x80000000;
1751 set_long(pc, e);
1752 e->inst[0] |= lane_src0 << 16;
1753 set_src_0(pc, src0, e);
1754 set_src_2(pc, src1, e);
1755
1756 if (wp >= 0)
1757 set_pred_wr(pc, 1, wp, e);
1758
1759 if (dst)
1760 set_dst(pc, dst, e);
1761 else {
1762 e->inst[0] |= 0x000001fc;
1763 e->inst[1] |= 0x00000008;
1764 }
1765
1766 e->inst[0] |= (qop & 3) << 20;
1767 e->inst[1] |= (qop >> 2) << 22;
1768
1769 emit(pc, e);
1770 }
1771
1772 static void
1773 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1774 struct nv50_reg **src, unsigned arg, boolean proj)
1775 {
1776 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1777
1778 src[0]->mod |= NV50_MOD_ABS;
1779 src[1]->mod |= NV50_MOD_ABS;
1780 src[2]->mod |= NV50_MOD_ABS;
1781
1782 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1783 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1784
1785 src[0]->mod = mod[0];
1786 src[1]->mod = mod[1];
1787 src[2]->mod = mod[2];
1788
1789 if (proj && 0 /* looks more correct without this */)
1790 emit_mul(pc, t[2], t[2], src[3]);
1791 else
1792 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1793 emit_mov(pc, t[3], src[3]);
1794
1795 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1796
1797 emit_mul(pc, t[0], src[0], t[2]);
1798 emit_mul(pc, t[1], src[1], t[2]);
1799 emit_mul(pc, t[2], src[2], t[2]);
1800 }
1801
1802 static void
1803 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1804 struct nv50_reg **src, unsigned dim, unsigned arg)
1805 {
1806 unsigned c, mode;
1807
1808 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1809 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1810
1811 t[3]->rhw = src[3]->rhw;
1812 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1813 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1814
1815 for (c = 0; c < dim; ++c) {
1816 t[c]->rhw = src[c]->rhw;
1817 emit_interp(pc, t[c], t[3], mode);
1818 }
1819 if (arg != dim) { /* depth reference value */
1820 t[dim]->rhw = src[2]->rhw;
1821 emit_interp(pc, t[dim], t[3], mode);
1822 }
1823 } else {
1824 /* XXX: for some reason the blob sometimes uses MAD
1825 * (mad f32 $rX $rY $rZ neg $r63)
1826 */
1827 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1828 for (c = 0; c < dim; ++c)
1829 emit_mul(pc, t[c], src[c], t[3]);
1830 if (arg != dim) /* depth reference value */
1831 emit_mul(pc, t[dim], src[2], t[3]);
1832 }
1833 }
1834
1835 static INLINE void
1836 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1837 {
1838 switch (type) {
1839 case TGSI_TEXTURE_1D:
1840 *arg = *dim = 1;
1841 break;
1842 case TGSI_TEXTURE_SHADOW1D:
1843 *dim = 1;
1844 *arg = 2;
1845 break;
1846 case TGSI_TEXTURE_UNKNOWN:
1847 case TGSI_TEXTURE_2D:
1848 case TGSI_TEXTURE_RECT:
1849 *arg = *dim = 2;
1850 break;
1851 case TGSI_TEXTURE_SHADOW2D:
1852 case TGSI_TEXTURE_SHADOWRECT:
1853 *dim = 2;
1854 *arg = 3;
1855 break;
1856 case TGSI_TEXTURE_3D:
1857 case TGSI_TEXTURE_CUBE:
1858 *dim = *arg = 3;
1859 break;
1860 default:
1861 assert(0);
1862 break;
1863 }
1864 }
1865
1866 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1867 * different LOD values, so branch off groups of equal LOD.
1868 */
1869 static void
1870 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1871 struct nv50_reg *src, struct nv50_program_exec *tex)
1872 {
1873 struct nv50_program_exec *join_at;
1874 unsigned i, target = pc->p->exec_size + 9 * 2;
1875
1876 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1877 emit(pc, tex);
1878 return;
1879 }
1880 pc->allow32 = FALSE;
1881
1882 /* Subtract lod of each pixel from lod of top left pixel, jump
1883 * texlod insn if result is 0, then repeat for 2 other pixels.
1884 */
1885 join_at = emit_joinat(pc);
1886 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1887 emit_branch(pc, 0, 2)->param.index = target;
1888
1889 for (i = 1; i < 4; ++i) {
1890 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1891 emit_branch(pc, 0, 2)->param.index = target;
1892 }
1893
1894 emit_mov(pc, tlod, src); /* target */
1895 emit(pc, tex); /* texlod */
1896
1897 join_at->param.index = target + 2 * 2;
1898 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1899 }
1900
1901 static void
1902 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1903 struct nv50_program_exec *tex)
1904 {
1905 struct nv50_program_exec *e;
1906 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1907 int r_pred = 0;
1908 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1909
1910 pc->allow32 = FALSE;
1911 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1912
1913 /* Subtract bias value of thread i from bias values of each thread,
1914 * store result in r_pred, and set bit i in r_bits if result was 0.
1915 */
1916 assert(arg < 4);
1917 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1918 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1919 emit_mov(pc, r_bits, &imm_1248);
1920 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1921 }
1922 emit_mov_to_pred(pc, r_pred, r_bits);
1923
1924 /* The lanes of a quad are now grouped by the bit in r_pred they have
1925 * set. Put the input values for TEX into a new register set for each
1926 * group and execute TEX only for a specific group.
1927 * We cannot use the same register set for each group because we need
1928 * the derivatives, which are implicitly calculated, to be correct.
1929 */
1930 for (i = 1; i < 4; ++i) {
1931 alloc_temp4(pc, t123[i], 0);
1932
1933 for (c = 0; c <= arg; ++c)
1934 emit_mov(pc, t123[i][c], t[c]);
1935
1936 *(e = exec(pc)) = *(tex);
1937 e->inst[0] &= ~0x01fc;
1938 set_dst(pc, t123[i][0], e);
1939 set_pred(pc, cc[i], r_pred, e);
1940 emit(pc, e);
1941 }
1942 /* finally TEX on the original regs (where we kept the input) */
1943 set_pred(pc, cc[0], r_pred, tex);
1944 emit(pc, tex);
1945
1946 /* put the 3 * n other results into regs for lane 0 */
1947 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1948 for (i = 1; i < 4; ++i) {
1949 for (c = 0; c < n; ++c) {
1950 emit_mov(pc, t[c], t123[i][c]);
1951 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1952 }
1953 free_temp4(pc, t123[i]);
1954 }
1955
1956 emit_nop(pc);
1957 free_temp(pc, r_bits);
1958 }
1959
1960 static void
1961 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1962 struct nv50_reg **src, unsigned unit, unsigned type,
1963 boolean proj, int bias_lod)
1964 {
1965 struct nv50_reg *t[4];
1966 struct nv50_program_exec *e;
1967 unsigned c, dim, arg;
1968
1969 /* t[i] must be within a single 128 bit super-reg */
1970 alloc_temp4(pc, t, 0);
1971
1972 e = exec(pc);
1973 e->inst[0] = 0xf0000000;
1974 set_long(pc, e);
1975 set_dst(pc, t[0], e);
1976
1977 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1978 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1979
1980 /* live flag (don't set if TEX results affect input to another TEX): */
1981 /* e->inst[0] |= 0x00000004; */
1982
1983 get_tex_dim(type, &dim, &arg);
1984
1985 if (type == TGSI_TEXTURE_CUBE) {
1986 e->inst[0] |= 0x08000000;
1987 load_cube_tex_coords(pc, t, src, arg, proj);
1988 } else
1989 if (proj)
1990 load_proj_tex_coords(pc, t, src, dim, arg);
1991 else {
1992 for (c = 0; c < dim; c++)
1993 emit_mov(pc, t[c], src[c]);
1994 if (arg != dim) /* depth reference value (always src.z here) */
1995 emit_mov(pc, t[dim], src[2]);
1996 }
1997
1998 e->inst[0] |= (mask & 0x3) << 25;
1999 e->inst[1] |= (mask & 0xc) << 12;
2000
2001 if (!bias_lod) {
2002 e->inst[0] |= (arg - 1) << 22;
2003 emit(pc, e);
2004 } else
2005 if (bias_lod < 0) {
2006 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
2007 e->inst[0] |= arg << 22;
2008 e->inst[1] |= 0x20000000; /* texbias */
2009 emit_mov(pc, t[arg], src[3]);
2010 emit_texbias_sequence(pc, t, arg, e);
2011 } else {
2012 e->inst[0] |= arg << 22;
2013 e->inst[1] |= 0x40000000; /* texlod */
2014 emit_mov(pc, t[arg], src[3]);
2015 emit_texlod_sequence(pc, t[arg], src[3], e);
2016 }
2017
2018 #if 1
2019 c = 0;
2020 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
2021 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
2022 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
2023 if (mask & 8) emit_mov(pc, dst[3], t[c]);
2024
2025 free_temp4(pc, t);
2026 #else
2027 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2028 * the texture coordinates, not the fetched values: latency ? */
2029
2030 for (c = 0; c < 4; c++) {
2031 if (mask & (1 << c))
2032 assimilate_temp(pc, dst[c], t[c]);
2033 else
2034 free_temp(pc, t[c]);
2035 }
2036 #endif
2037 }
2038
2039 static void
2040 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2041 {
2042 struct nv50_program_exec *e = exec(pc);
2043
2044 assert(src->type == P_TEMP);
2045
2046 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
2047 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
2048 set_long(pc, e);
2049 set_dst(pc, dst, e);
2050 set_src_0(pc, src, e);
2051 set_src_2(pc, src, e);
2052
2053 emit(pc, e);
2054 }
2055
2056 static void
2057 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2058 {
2059 struct nv50_program_exec *e = exec(pc);
2060
2061 assert(src->type == P_TEMP);
2062
2063 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
2064 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
2065 set_long(pc, e);
2066 set_dst(pc, dst, e);
2067 set_src_0(pc, src, e);
2068 set_src_2(pc, src, e);
2069
2070 emit(pc, e);
2071 }
2072
2073 static void
2074 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
2075 {
2076 unsigned q = 0, m = ~0;
2077
2078 assert(!is_long(e));
2079
2080 switch (e->inst[0] >> 28) {
2081 case 0x1:
2082 /* MOV */
2083 q = 0x0403c000;
2084 m = 0xffff7fff;
2085 break;
2086 case 0x2:
2087 case 0x3:
2088 /* ADD, SUB, SUBR b32 */
2089 m = ~(0x8000 | (127 << 16));
2090 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
2091 break;
2092 case 0x5:
2093 /* SAD */
2094 m = ~(0x81 << 8);
2095 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
2096 break;
2097 case 0x6:
2098 /* MAD u16 */
2099 q = (e->inst[0] & (0x7f << 2)) << 12;
2100 break;
2101 case 0x8:
2102 /* INTERP (move centroid, perspective and flat bits) */
2103 m = ~0x03000100;
2104 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2105 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2106 break;
2107 case 0x9:
2108 /* RCP */
2109 break;
2110 case 0xB:
2111 /* ADD */
2112 m = ~(127 << 16);
2113 q = ((e->inst[0] & (~m)) >> 2);
2114 break;
2115 case 0xC:
2116 /* MUL */
2117 m = ~0x00008000;
2118 q = ((e->inst[0] & (~m)) << 12);
2119 break;
2120 case 0xE:
2121 /* MAD (if src2 == dst) */
2122 q = ((e->inst[0] & 0x1fc) << 12);
2123 break;
2124 default:
2125 assert(0);
2126 break;
2127 }
2128
2129 set_long(pc, e);
2130 pc->p->exec_size++;
2131
2132 e->inst[0] &= m;
2133 e->inst[1] |= q;
2134 }
2135
2136 /* Some operations support an optional negation flag. */
2137 static int
2138 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2139 {
2140 switch (insn->Instruction.Opcode) {
2141 case TGSI_OPCODE_ADD:
2142 case TGSI_OPCODE_COS:
2143 case TGSI_OPCODE_DDX:
2144 case TGSI_OPCODE_DDY:
2145 case TGSI_OPCODE_DP3:
2146 case TGSI_OPCODE_DP4:
2147 case TGSI_OPCODE_EX2:
2148 case TGSI_OPCODE_KIL:
2149 case TGSI_OPCODE_LG2:
2150 case TGSI_OPCODE_MAD:
2151 case TGSI_OPCODE_MUL:
2152 case TGSI_OPCODE_POW:
2153 case TGSI_OPCODE_RCP:
2154 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2155 case TGSI_OPCODE_SCS:
2156 case TGSI_OPCODE_SIN:
2157 case TGSI_OPCODE_SUB:
2158 return NV50_MOD_NEG;
2159 case TGSI_OPCODE_MAX:
2160 case TGSI_OPCODE_MIN:
2161 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2162 return NV50_MOD_ABS;
2163 case TGSI_OPCODE_CEIL:
2164 case TGSI_OPCODE_FLR:
2165 case TGSI_OPCODE_TRUNC:
2166 return NV50_MOD_NEG | NV50_MOD_ABS;
2167 case TGSI_OPCODE_F2I:
2168 case TGSI_OPCODE_F2U:
2169 case TGSI_OPCODE_I2F:
2170 case TGSI_OPCODE_U2F:
2171 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2172 case TGSI_OPCODE_UADD:
2173 return NV50_MOD_NEG | NV50_MOD_I32;
2174 case TGSI_OPCODE_SAD:
2175 case TGSI_OPCODE_SHL:
2176 case TGSI_OPCODE_IMAX:
2177 case TGSI_OPCODE_IMIN:
2178 case TGSI_OPCODE_ISHR:
2179 case TGSI_OPCODE_NOT:
2180 case TGSI_OPCODE_UMAD:
2181 case TGSI_OPCODE_UMAX:
2182 case TGSI_OPCODE_UMIN:
2183 case TGSI_OPCODE_UMUL:
2184 case TGSI_OPCODE_USHR:
2185 return NV50_MOD_I32;
2186 default:
2187 return 0;
2188 }
2189 }
2190
2191 /* Return a read mask for source registers deduced from opcode & write mask. */
2192 static unsigned
2193 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2194 {
2195 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2196
2197 switch (insn->Instruction.Opcode) {
2198 case TGSI_OPCODE_COS:
2199 case TGSI_OPCODE_SIN:
2200 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2201 case TGSI_OPCODE_DP3:
2202 return 0x7;
2203 case TGSI_OPCODE_DP4:
2204 case TGSI_OPCODE_DPH:
2205 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2206 return 0xf;
2207 case TGSI_OPCODE_DST:
2208 return mask & (c ? 0xa : 0x6);
2209 case TGSI_OPCODE_EX2:
2210 case TGSI_OPCODE_EXP:
2211 case TGSI_OPCODE_LG2:
2212 case TGSI_OPCODE_LOG:
2213 case TGSI_OPCODE_POW:
2214 case TGSI_OPCODE_RCP:
2215 case TGSI_OPCODE_RSQ:
2216 case TGSI_OPCODE_SCS:
2217 return 0x1;
2218 case TGSI_OPCODE_IF:
2219 return 0x1;
2220 case TGSI_OPCODE_LIT:
2221 return 0xb;
2222 case TGSI_OPCODE_TEX:
2223 case TGSI_OPCODE_TXB:
2224 case TGSI_OPCODE_TXL:
2225 case TGSI_OPCODE_TXP:
2226 {
2227 const struct tgsi_instruction_texture *tex;
2228
2229 assert(insn->Instruction.Texture);
2230 tex = &insn->Texture;
2231
2232 mask = 0x7;
2233 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2234 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2235 mask |= 0x8; /* bias, lod or proj */
2236
2237 switch (tex->Texture) {
2238 case TGSI_TEXTURE_1D:
2239 mask &= 0x9;
2240 break;
2241 case TGSI_TEXTURE_SHADOW1D:
2242 mask &= 0x5;
2243 break;
2244 case TGSI_TEXTURE_2D:
2245 mask &= 0xb;
2246 break;
2247 default:
2248 break;
2249 }
2250 }
2251 return mask;
2252 case TGSI_OPCODE_XPD:
2253 x = 0;
2254 if (mask & 1) x |= 0x6;
2255 if (mask & 2) x |= 0x5;
2256 if (mask & 4) x |= 0x3;
2257 return x;
2258 default:
2259 break;
2260 }
2261
2262 return mask;
2263 }
2264
2265 static struct nv50_reg *
2266 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2267 {
2268 switch (dst->Register.File) {
2269 case TGSI_FILE_TEMPORARY:
2270 return &pc->temp[dst->Register.Index * 4 + c];
2271 case TGSI_FILE_OUTPUT:
2272 return &pc->result[dst->Register.Index * 4 + c];
2273 case TGSI_FILE_ADDRESS:
2274 {
2275 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2276 if (!r) {
2277 r = get_address_reg(pc, NULL);
2278 r->index = dst->Register.Index * 4 + c;
2279 pc->addr[r->index] = r;
2280 }
2281 assert(r);
2282 return r;
2283 }
2284 case TGSI_FILE_NULL:
2285 return NULL;
2286 case TGSI_FILE_SYSTEM_VALUE:
2287 assert(pc->sysval[dst->Register.Index].type == P_RESULT);
2288 assert(c == 0);
2289 return &pc->sysval[dst->Register.Index];
2290 default:
2291 break;
2292 }
2293
2294 return NULL;
2295 }
2296
2297 static struct nv50_reg *
2298 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2299 int mod)
2300 {
2301 struct nv50_reg *r = NULL;
2302 struct nv50_reg *temp = NULL;
2303 unsigned sgn, c, swz, cvn;
2304
2305 if (src->Register.File != TGSI_FILE_CONSTANT)
2306 assert(!src->Register.Indirect);
2307
2308 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2309
2310 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2311 switch (c) {
2312 case TGSI_SWIZZLE_X:
2313 case TGSI_SWIZZLE_Y:
2314 case TGSI_SWIZZLE_Z:
2315 case TGSI_SWIZZLE_W:
2316 switch (src->Register.File) {
2317 case TGSI_FILE_INPUT:
2318 r = &pc->attr[src->Register.Index * 4 + c];
2319
2320 if (!src->Dimension.Dimension)
2321 break;
2322 r = reg_instance(pc, r);
2323 r->vtx = src->Dimension.Index;
2324
2325 if (!src->Dimension.Indirect)
2326 break;
2327 swz = tgsi_util_get_src_register_swizzle(
2328 &src->DimIndirect, 0);
2329 r->acc = -1;
2330 r->indirect[1] = src->DimIndirect.Index * 4 + swz;
2331 break;
2332 case TGSI_FILE_TEMPORARY:
2333 r = &pc->temp[src->Register.Index * 4 + c];
2334 break;
2335 case TGSI_FILE_CONSTANT:
2336 if (!src->Register.Indirect) {
2337 r = &pc->param[src->Register.Index * 4 + c];
2338 break;
2339 }
2340 /* Indicate indirection by setting r->acc < 0 and
2341 * use the index field to select the address reg.
2342 */
2343 r = reg_instance(pc, NULL);
2344 ctor_reg(r, P_CONST, -1, src->Register.Index * 4 + c);
2345
2346 swz = tgsi_util_get_src_register_swizzle(
2347 &src->Indirect, 0);
2348 r->acc = -1;
2349 r->indirect[0] = src->Indirect.Index * 4 + swz;
2350 break;
2351 case TGSI_FILE_IMMEDIATE:
2352 r = &pc->immd[src->Register.Index * 4 + c];
2353 break;
2354 case TGSI_FILE_SAMPLER:
2355 return NULL;
2356 case TGSI_FILE_ADDRESS:
2357 r = pc->addr[src->Register.Index * 4 + c];
2358 assert(r);
2359 break;
2360 case TGSI_FILE_SYSTEM_VALUE:
2361 assert(c == 0);
2362 r = &pc->sysval[src->Register.Index];
2363 break;
2364 default:
2365 assert(0);
2366 break;
2367 }
2368 break;
2369 default:
2370 assert(0);
2371 break;
2372 }
2373
2374 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2375
2376 switch (sgn) {
2377 case TGSI_UTIL_SIGN_CLEAR:
2378 r->mod = NV50_MOD_ABS;
2379 break;
2380 case TGSI_UTIL_SIGN_SET:
2381 r->mod = NV50_MOD_NEG_ABS;
2382 break;
2383 case TGSI_UTIL_SIGN_TOGGLE:
2384 r->mod = NV50_MOD_NEG;
2385 break;
2386 default:
2387 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2388 break;
2389 }
2390
2391 if ((r->mod & mod) != r->mod) {
2392 temp = temp_temp(pc, NULL);
2393 emit_cvt(pc, temp, r, -1, cvn);
2394 r->mod = 0;
2395 r = temp;
2396 } else
2397 r->mod |= mod & NV50_MOD_I32;
2398
2399 assert(r);
2400 if (r->acc >= 0 && r->vtx < 0 && r != temp)
2401 return reg_instance(pc, r); /* will clear r->mod */
2402 return r;
2403 }
2404
2405 /* return TRUE for ops that produce only a single result */
2406 static boolean
2407 is_scalar_op(unsigned op)
2408 {
2409 switch (op) {
2410 case TGSI_OPCODE_COS:
2411 case TGSI_OPCODE_DP2:
2412 case TGSI_OPCODE_DP3:
2413 case TGSI_OPCODE_DP4:
2414 case TGSI_OPCODE_DPH:
2415 case TGSI_OPCODE_EX2:
2416 case TGSI_OPCODE_LG2:
2417 case TGSI_OPCODE_POW:
2418 case TGSI_OPCODE_RCP:
2419 case TGSI_OPCODE_RSQ:
2420 case TGSI_OPCODE_SIN:
2421 /*
2422 case TGSI_OPCODE_KIL:
2423 case TGSI_OPCODE_LIT:
2424 case TGSI_OPCODE_SCS:
2425 */
2426 return TRUE;
2427 default:
2428 return FALSE;
2429 }
2430 }
2431
2432 /* Returns a bitmask indicating which dst components depend
2433 * on source s, component c (reverse of nv50_tgsi_src_mask).
2434 */
2435 static unsigned
2436 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2437 {
2438 if (is_scalar_op(op))
2439 return 0x1;
2440
2441 switch (op) {
2442 case TGSI_OPCODE_DST:
2443 return (1 << c) & (s ? 0xa : 0x6);
2444 case TGSI_OPCODE_XPD:
2445 switch (c) {
2446 case 0: return 0x6;
2447 case 1: return 0x5;
2448 case 2: return 0x3;
2449 case 3: return 0x0;
2450 default:
2451 assert(0);
2452 return 0x0;
2453 }
2454 case TGSI_OPCODE_EXP:
2455 case TGSI_OPCODE_LOG:
2456 case TGSI_OPCODE_LIT:
2457 case TGSI_OPCODE_SCS:
2458 case TGSI_OPCODE_TEX:
2459 case TGSI_OPCODE_TXB:
2460 case TGSI_OPCODE_TXL:
2461 case TGSI_OPCODE_TXP:
2462 /* these take care of dangerous swizzles themselves */
2463 return 0x0;
2464 case TGSI_OPCODE_IF:
2465 case TGSI_OPCODE_KIL:
2466 /* don't call this function for these ops */
2467 assert(0);
2468 return 0;
2469 default:
2470 /* linear vector instruction */
2471 return (1 << c);
2472 }
2473 }
2474
2475 static INLINE boolean
2476 has_pred(struct nv50_program_exec *e, unsigned cc)
2477 {
2478 if (!is_long(e) || is_immd(e))
2479 return FALSE;
2480 return ((e->inst[1] & 0x780) == (cc << 7));
2481 }
2482
2483 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2484 * join_at ENDIF
2485 * @p0.eq bra ENDIF
2486 * single_op
2487 * ENDIF: nop.join
2488 */
2489 static boolean
2490 nv50_kill_branch(struct nv50_pc *pc)
2491 {
2492 int lvl = pc->if_lvl;
2493
2494 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2495 return FALSE;
2496 if (is_immd(pc->p->exec_tail))
2497 return FALSE;
2498
2499 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2500 * reg may no longer be valid, since we currently always use $p0
2501 */
2502 if (has_pred(pc->if_insn[lvl], 0xf))
2503 return FALSE;
2504 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2505
2506 /* We'll use the exec allocated for JOIN_AT (we can't easily
2507 * access nv50_program_exec's prev).
2508 */
2509 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2510
2511 *pc->if_join[lvl] = *pc->p->exec_tail;
2512
2513 FREE(pc->if_insn[lvl]);
2514 FREE(pc->p->exec_tail);
2515
2516 pc->p->exec_tail = pc->if_join[lvl];
2517 pc->p->exec_tail->next = NULL;
2518 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2519
2520 return TRUE;
2521 }
2522
2523 static void
2524 nv50_fp_move_results(struct nv50_pc *pc)
2525 {
2526 struct nv50_reg reg;
2527 unsigned i;
2528
2529 ctor_reg(&reg, P_TEMP, -1, -1);
2530
2531 for (i = 0; i < pc->result_nr * 4; ++i) {
2532 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2533 continue;
2534 if (pc->result[i].rhw != pc->result[i].hw) {
2535 reg.hw = pc->result[i].rhw;
2536 emit_mov(pc, &reg, &pc->result[i]);
2537 }
2538 }
2539 }
2540
2541 static boolean
2542 nv50_program_tx_insn(struct nv50_pc *pc,
2543 const struct tgsi_full_instruction *inst)
2544 {
2545 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2546 unsigned mask, sat, unit;
2547 int i, c;
2548
2549 mask = inst->Dst[0].Register.WriteMask;
2550 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2551
2552 memset(src, 0, sizeof(src));
2553
2554 for (c = 0; c < 4; c++) {
2555 if ((mask & (1 << c)) && !pc->r_dst[c])
2556 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2557 else
2558 dst[c] = pc->r_dst[c];
2559 rdst[c] = dst[c];
2560 }
2561
2562 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2563 const struct tgsi_full_src_register *fs = &inst->Src[i];
2564 unsigned src_mask;
2565 int mod_supp;
2566
2567 src_mask = nv50_tgsi_src_mask(inst, i);
2568 mod_supp = get_supported_mods(inst, i);
2569
2570 if (fs->Register.File == TGSI_FILE_SAMPLER)
2571 unit = fs->Register.Index;
2572
2573 for (c = 0; c < 4; c++)
2574 if (src_mask & (1 << c))
2575 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2576 }
2577
2578 brdc = temp = pc->r_brdc;
2579 if (brdc && brdc->type != P_TEMP) {
2580 temp = temp_temp(pc, NULL);
2581 if (sat)
2582 brdc = temp;
2583 } else
2584 if (sat) {
2585 for (c = 0; c < 4; c++) {
2586 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2587 continue;
2588 /* rdst[c] = dst[c]; */ /* done above */
2589 dst[c] = temp_temp(pc, NULL);
2590 }
2591 }
2592
2593 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2594
2595 switch (inst->Instruction.Opcode) {
2596 case TGSI_OPCODE_ABS:
2597 for (c = 0; c < 4; c++) {
2598 if (!(mask & (1 << c)))
2599 continue;
2600 emit_cvt(pc, dst[c], src[0][c], -1,
2601 CVT_ABS | CVT_F32_F32);
2602 }
2603 break;
2604 case TGSI_OPCODE_ADD:
2605 for (c = 0; c < 4; c++) {
2606 if (!(mask & (1 << c)))
2607 continue;
2608 emit_add(pc, dst[c], src[0][c], src[1][c]);
2609 }
2610 break;
2611 case TGSI_OPCODE_AND:
2612 case TGSI_OPCODE_XOR:
2613 case TGSI_OPCODE_OR:
2614 for (c = 0; c < 4; c++) {
2615 if (!(mask & (1 << c)))
2616 continue;
2617 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2618 inst->Instruction.Opcode);
2619 }
2620 break;
2621 case TGSI_OPCODE_ARL:
2622 temp = temp_temp(pc, NULL);
2623 for (c = 0; c < 4; c++) {
2624 if (!(mask & (1 << c)))
2625 continue;
2626 emit_cvt(pc, temp, src[0][c], -1,
2627 CVT_FLOOR | CVT_S32_F32);
2628 emit_arl(pc, dst[c], temp, 4);
2629 }
2630 break;
2631 case TGSI_OPCODE_BGNLOOP:
2632 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2633 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2634 terminate_mbb(pc);
2635 break;
2636 case TGSI_OPCODE_BGNSUB:
2637 assert(!pc->in_subroutine);
2638 pc->in_subroutine = TRUE;
2639 /* probably not necessary, but align to 8 byte boundary */
2640 if (!is_long(pc->p->exec_tail))
2641 convert_to_long(pc, pc->p->exec_tail);
2642 break;
2643 case TGSI_OPCODE_BRK:
2644 assert(pc->loop_lvl > 0);
2645 emit_break(pc, -1, 0);
2646 break;
2647 case TGSI_OPCODE_CAL:
2648 assert(inst->Label.Label < pc->insn_nr);
2649 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2650 /* replaced by actual offset in nv50_program_fixup_insns */
2651 break;
2652 case TGSI_OPCODE_CEIL:
2653 for (c = 0; c < 4; c++) {
2654 if (!(mask & (1 << c)))
2655 continue;
2656 emit_cvt(pc, dst[c], src[0][c], -1,
2657 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2658 }
2659 break;
2660 case TGSI_OPCODE_CMP:
2661 pc->allow32 = FALSE;
2662 for (c = 0; c < 4; c++) {
2663 if (!(mask & (1 << c)))
2664 continue;
2665 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2666 emit_mov(pc, dst[c], src[1][c]);
2667 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2668 emit_mov(pc, dst[c], src[2][c]);
2669 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2670 }
2671 break;
2672 case TGSI_OPCODE_CONT:
2673 assert(pc->loop_lvl > 0);
2674 emit_branch(pc, -1, 0)->param.index =
2675 pc->loop_pos[pc->loop_lvl - 1];
2676 break;
2677 case TGSI_OPCODE_COS:
2678 if (mask & 8) {
2679 emit_precossin(pc, temp, src[0][3]);
2680 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2681 if (!(mask &= 7))
2682 break;
2683 if (temp == dst[3])
2684 temp = brdc = temp_temp(pc, NULL);
2685 }
2686 emit_precossin(pc, temp, src[0][0]);
2687 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2688 break;
2689 case TGSI_OPCODE_DDX:
2690 for (c = 0; c < 4; c++) {
2691 if (!(mask & (1 << c)))
2692 continue;
2693 emit_ddx(pc, dst[c], src[0][c]);
2694 }
2695 break;
2696 case TGSI_OPCODE_DDY:
2697 for (c = 0; c < 4; c++) {
2698 if (!(mask & (1 << c)))
2699 continue;
2700 emit_ddy(pc, dst[c], src[0][c]);
2701 }
2702 break;
2703 case TGSI_OPCODE_DP3:
2704 emit_mul(pc, temp, src[0][0], src[1][0]);
2705 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2706 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2707 break;
2708 case TGSI_OPCODE_DP4:
2709 emit_mul(pc, temp, src[0][0], src[1][0]);
2710 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2711 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2712 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2713 break;
2714 case TGSI_OPCODE_DPH:
2715 emit_mul(pc, temp, src[0][0], src[1][0]);
2716 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2717 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2718 emit_add(pc, brdc, src[1][3], temp);
2719 break;
2720 case TGSI_OPCODE_DST:
2721 if (mask & (1 << 1))
2722 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2723 if (mask & (1 << 2))
2724 emit_mov(pc, dst[2], src[0][2]);
2725 if (mask & (1 << 3))
2726 emit_mov(pc, dst[3], src[1][3]);
2727 if (mask & (1 << 0))
2728 emit_mov_immdval(pc, dst[0], 1.0f);
2729 break;
2730 case TGSI_OPCODE_ELSE:
2731 emit_branch(pc, -1, 0);
2732 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2733 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2734 terminate_mbb(pc);
2735 break;
2736 case TGSI_OPCODE_EMIT:
2737 emit_prim_cmd(pc, 1);
2738 break;
2739 case TGSI_OPCODE_ENDIF:
2740 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2741
2742 /* try to replace branch over 1 insn with a predicated insn */
2743 if (nv50_kill_branch(pc) == TRUE)
2744 break;
2745
2746 if (pc->if_join[pc->if_lvl]) {
2747 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2748 pc->if_join[pc->if_lvl] = NULL;
2749 }
2750 terminate_mbb(pc);
2751 /* emit a NOP as join point, we could set it on the next
2752 * one, but would have to make sure it is long and !immd
2753 */
2754 JOIN_ON(emit_nop(pc));
2755 break;
2756 case TGSI_OPCODE_ENDLOOP:
2757 emit_branch(pc, -1, 0)->param.index =
2758 pc->loop_pos[--pc->loop_lvl];
2759 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2760 terminate_mbb(pc);
2761 break;
2762 case TGSI_OPCODE_ENDPRIM:
2763 emit_prim_cmd(pc, 2);
2764 break;
2765 case TGSI_OPCODE_ENDSUB:
2766 assert(pc->in_subroutine);
2767 terminate_mbb(pc);
2768 pc->in_subroutine = FALSE;
2769 break;
2770 case TGSI_OPCODE_EX2:
2771 emit_preex2(pc, temp, src[0][0]);
2772 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2773 break;
2774 case TGSI_OPCODE_EXP:
2775 {
2776 struct nv50_reg *t[2];
2777
2778 assert(!temp);
2779 t[0] = temp_temp(pc, NULL);
2780 t[1] = temp_temp(pc, NULL);
2781
2782 if (mask & 0x6)
2783 emit_mov(pc, t[0], src[0][0]);
2784 if (mask & 0x3)
2785 emit_flr(pc, t[1], src[0][0]);
2786
2787 if (mask & (1 << 1))
2788 emit_sub(pc, dst[1], t[0], t[1]);
2789 if (mask & (1 << 0)) {
2790 emit_preex2(pc, t[1], t[1]);
2791 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2792 }
2793 if (mask & (1 << 2)) {
2794 emit_preex2(pc, t[0], t[0]);
2795 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2796 }
2797 if (mask & (1 << 3))
2798 emit_mov_immdval(pc, dst[3], 1.0f);
2799 }
2800 break;
2801 case TGSI_OPCODE_F2I:
2802 for (c = 0; c < 4; c++) {
2803 if (!(mask & (1 << c)))
2804 continue;
2805 emit_cvt(pc, dst[c], src[0][c], -1,
2806 CVT_TRUNC | CVT_S32_F32);
2807 }
2808 break;
2809 case TGSI_OPCODE_F2U:
2810 for (c = 0; c < 4; c++) {
2811 if (!(mask & (1 << c)))
2812 continue;
2813 emit_cvt(pc, dst[c], src[0][c], -1,
2814 CVT_TRUNC | CVT_U32_F32);
2815 }
2816 break;
2817 case TGSI_OPCODE_FLR:
2818 for (c = 0; c < 4; c++) {
2819 if (!(mask & (1 << c)))
2820 continue;
2821 emit_flr(pc, dst[c], src[0][c]);
2822 }
2823 break;
2824 case TGSI_OPCODE_FRC:
2825 temp = temp_temp(pc, NULL);
2826 for (c = 0; c < 4; c++) {
2827 if (!(mask & (1 << c)))
2828 continue;
2829 emit_flr(pc, temp, src[0][c]);
2830 emit_sub(pc, dst[c], src[0][c], temp);
2831 }
2832 break;
2833 case TGSI_OPCODE_I2F:
2834 for (c = 0; c < 4; c++) {
2835 if (!(mask & (1 << c)))
2836 continue;
2837 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2838 }
2839 break;
2840 case TGSI_OPCODE_IF:
2841 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2842 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2843 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2844 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2845 terminate_mbb(pc);
2846 break;
2847 case TGSI_OPCODE_IMAX:
2848 for (c = 0; c < 4; c++) {
2849 if (!(mask & (1 << c)))
2850 continue;
2851 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2852 }
2853 break;
2854 case TGSI_OPCODE_IMIN:
2855 for (c = 0; c < 4; c++) {
2856 if (!(mask & (1 << c)))
2857 continue;
2858 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2859 }
2860 break;
2861 case TGSI_OPCODE_INEG:
2862 for (c = 0; c < 4; c++) {
2863 if (!(mask & (1 << c)))
2864 continue;
2865 emit_cvt(pc, dst[c], src[0][c], -1,
2866 CVT_S32_S32 | CVT_NEG);
2867 }
2868 break;
2869 case TGSI_OPCODE_KIL:
2870 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2871 emit_kil(pc, src[0][0]);
2872 emit_kil(pc, src[0][1]);
2873 emit_kil(pc, src[0][2]);
2874 emit_kil(pc, src[0][3]);
2875 break;
2876 case TGSI_OPCODE_KILP:
2877 emit_kil(pc, NULL);
2878 break;
2879 case TGSI_OPCODE_LIT:
2880 emit_lit(pc, &dst[0], mask, &src[0][0]);
2881 break;
2882 case TGSI_OPCODE_LG2:
2883 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2884 break;
2885 case TGSI_OPCODE_LOG:
2886 {
2887 struct nv50_reg *t[2];
2888
2889 t[0] = temp_temp(pc, NULL);
2890 if (mask & (1 << 1))
2891 t[1] = temp_temp(pc, NULL);
2892 else
2893 t[1] = t[0];
2894
2895 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2896 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2897 if (mask & (1 << 2))
2898 emit_mov(pc, dst[2], t[1]);
2899 emit_flr(pc, t[1], t[1]);
2900 if (mask & (1 << 0))
2901 emit_mov(pc, dst[0], t[1]);
2902 if (mask & (1 << 1)) {
2903 t[1]->mod = NV50_MOD_NEG;
2904 emit_preex2(pc, t[1], t[1]);
2905 t[1]->mod = 0;
2906 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2907 emit_mul(pc, dst[1], t[0], t[1]);
2908 }
2909 if (mask & (1 << 3))
2910 emit_mov_immdval(pc, dst[3], 1.0f);
2911 }
2912 break;
2913 case TGSI_OPCODE_LRP:
2914 temp = temp_temp(pc, NULL);
2915 for (c = 0; c < 4; c++) {
2916 if (!(mask & (1 << c)))
2917 continue;
2918 emit_sub(pc, temp, src[1][c], src[2][c]);
2919 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2920 }
2921 break;
2922 case TGSI_OPCODE_MAD:
2923 for (c = 0; c < 4; c++) {
2924 if (!(mask & (1 << c)))
2925 continue;
2926 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2927 }
2928 break;
2929 case TGSI_OPCODE_MAX:
2930 for (c = 0; c < 4; c++) {
2931 if (!(mask & (1 << c)))
2932 continue;
2933 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2934 }
2935 break;
2936 case TGSI_OPCODE_MIN:
2937 for (c = 0; c < 4; c++) {
2938 if (!(mask & (1 << c)))
2939 continue;
2940 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2941 }
2942 break;
2943 case TGSI_OPCODE_MOV:
2944 for (c = 0; c < 4; c++) {
2945 if (!(mask & (1 << c)))
2946 continue;
2947 emit_mov(pc, dst[c], src[0][c]);
2948 }
2949 break;
2950 case TGSI_OPCODE_MUL:
2951 for (c = 0; c < 4; c++) {
2952 if (!(mask & (1 << c)))
2953 continue;
2954 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2955 }
2956 break;
2957 case TGSI_OPCODE_NOT:
2958 for (c = 0; c < 4; c++) {
2959 if (!(mask & (1 << c)))
2960 continue;
2961 emit_not(pc, dst[c], src[0][c]);
2962 }
2963 break;
2964 case TGSI_OPCODE_POW:
2965 emit_pow(pc, brdc, src[0][0], src[1][0]);
2966 break;
2967 case TGSI_OPCODE_RCP:
2968 if (!sat && popcnt4(mask) == 1)
2969 brdc = dst[ffs(mask) - 1];
2970 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2971 break;
2972 case TGSI_OPCODE_RET:
2973 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2974 nv50_fp_move_results(pc);
2975 emit_ret(pc, -1, 0);
2976 break;
2977 case TGSI_OPCODE_RSQ:
2978 if (!sat && popcnt4(mask) == 1)
2979 brdc = dst[ffs(mask) - 1];
2980 src[0][0]->mod |= NV50_MOD_ABS;
2981 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2982 break;
2983 case TGSI_OPCODE_SAD:
2984 for (c = 0; c < 4; c++) {
2985 if (!(mask & (1 << c)))
2986 continue;
2987 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2988 }
2989 break;
2990 case TGSI_OPCODE_SCS:
2991 temp = temp_temp(pc, NULL);
2992 if (mask & 3)
2993 emit_precossin(pc, temp, src[0][0]);
2994 if (mask & (1 << 0))
2995 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2996 if (mask & (1 << 1))
2997 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2998 if (mask & (1 << 2))
2999 emit_mov_immdval(pc, dst[2], 0.0);
3000 if (mask & (1 << 3))
3001 emit_mov_immdval(pc, dst[3], 1.0);
3002 break;
3003 case TGSI_OPCODE_SHL:
3004 case TGSI_OPCODE_ISHR:
3005 case TGSI_OPCODE_USHR:
3006 for (c = 0; c < 4; c++) {
3007 if (!(mask & (1 << c)))
3008 continue;
3009 emit_shift(pc, dst[c], src[0][c], src[1][c],
3010 inst->Instruction.Opcode);
3011 }
3012 break;
3013 case TGSI_OPCODE_SIN:
3014 if (mask & 8) {
3015 emit_precossin(pc, temp, src[0][3]);
3016 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
3017 if (!(mask &= 7))
3018 break;
3019 if (temp == dst[3])
3020 temp = brdc = temp_temp(pc, NULL);
3021 }
3022 emit_precossin(pc, temp, src[0][0]);
3023 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
3024 break;
3025 case TGSI_OPCODE_SLT:
3026 case TGSI_OPCODE_SGE:
3027 case TGSI_OPCODE_SEQ:
3028 case TGSI_OPCODE_SGT:
3029 case TGSI_OPCODE_SLE:
3030 case TGSI_OPCODE_SNE:
3031 case TGSI_OPCODE_ISLT:
3032 case TGSI_OPCODE_ISGE:
3033 case TGSI_OPCODE_USEQ:
3034 case TGSI_OPCODE_USGE:
3035 case TGSI_OPCODE_USLT:
3036 case TGSI_OPCODE_USNE:
3037 {
3038 uint8_t cc, ty;
3039
3040 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
3041
3042 for (c = 0; c < 4; c++) {
3043 if (!(mask & (1 << c)))
3044 continue;
3045 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
3046 }
3047 }
3048 break;
3049 case TGSI_OPCODE_SUB:
3050 for (c = 0; c < 4; c++) {
3051 if (!(mask & (1 << c)))
3052 continue;
3053 emit_sub(pc, dst[c], src[0][c], src[1][c]);
3054 }
3055 break;
3056 case TGSI_OPCODE_TEX:
3057 emit_tex(pc, dst, mask, src[0], unit,
3058 inst->Texture.Texture, FALSE, 0);
3059 break;
3060 case TGSI_OPCODE_TXB:
3061 emit_tex(pc, dst, mask, src[0], unit,
3062 inst->Texture.Texture, FALSE, -1);
3063 break;
3064 case TGSI_OPCODE_TXL:
3065 emit_tex(pc, dst, mask, src[0], unit,
3066 inst->Texture.Texture, FALSE, 1);
3067 break;
3068 case TGSI_OPCODE_TXP:
3069 emit_tex(pc, dst, mask, src[0], unit,
3070 inst->Texture.Texture, TRUE, 0);
3071 break;
3072 case TGSI_OPCODE_TRUNC:
3073 for (c = 0; c < 4; c++) {
3074 if (!(mask & (1 << c)))
3075 continue;
3076 emit_cvt(pc, dst[c], src[0][c], -1,
3077 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
3078 }
3079 break;
3080 case TGSI_OPCODE_U2F:
3081 for (c = 0; c < 4; c++) {
3082 if (!(mask & (1 << c)))
3083 continue;
3084 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
3085 }
3086 break;
3087 case TGSI_OPCODE_UADD:
3088 for (c = 0; c < 4; c++) {
3089 if (!(mask & (1 << c)))
3090 continue;
3091 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
3092 }
3093 break;
3094 case TGSI_OPCODE_UMAX:
3095 for (c = 0; c < 4; c++) {
3096 if (!(mask & (1 << c)))
3097 continue;
3098 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
3099 }
3100 break;
3101 case TGSI_OPCODE_UMIN:
3102 for (c = 0; c < 4; c++) {
3103 if (!(mask & (1 << c)))
3104 continue;
3105 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
3106 }
3107 break;
3108 case TGSI_OPCODE_UMAD:
3109 {
3110 assert(!temp);
3111 temp = temp_temp(pc, NULL);
3112 for (c = 0; c < 4; c++) {
3113 if (!(mask & (1 << c)))
3114 continue;
3115 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3116 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3117 temp);
3118 emit_shl_imm(pc, temp, temp, 16);
3119 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
3120 temp);
3121 emit_add_b32(pc, dst[c], temp, src[2][c]);
3122 }
3123 }
3124 break;
3125 case TGSI_OPCODE_UMUL:
3126 {
3127 assert(!temp);
3128 temp = temp_temp(pc, NULL);
3129 for (c = 0; c < 4; c++) {
3130 if (!(mask & (1 << c)))
3131 continue;
3132 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3133 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3134 temp);
3135 emit_shl_imm(pc, temp, temp, 16);
3136 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3137 temp);
3138 }
3139 }
3140 break;
3141 case TGSI_OPCODE_XPD:
3142 temp = temp_temp(pc, NULL);
3143 if (mask & (1 << 0)) {
3144 emit_mul(pc, temp, src[0][2], src[1][1]);
3145 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3146 }
3147 if (mask & (1 << 1)) {
3148 emit_mul(pc, temp, src[0][0], src[1][2]);
3149 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3150 }
3151 if (mask & (1 << 2)) {
3152 emit_mul(pc, temp, src[0][1], src[1][0]);
3153 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3154 }
3155 if (mask & (1 << 3))
3156 emit_mov_immdval(pc, dst[3], 1.0);
3157 break;
3158 case TGSI_OPCODE_END:
3159 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3160 nv50_fp_move_results(pc);
3161
3162 /* last insn must be long so it can have the exit bit set */
3163 if (!is_long(pc->p->exec_tail))
3164 convert_to_long(pc, pc->p->exec_tail);
3165 else
3166 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
3167 emit_nop(pc);
3168
3169 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3170
3171 terminate_mbb(pc);
3172 break;
3173 default:
3174 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3175 return FALSE;
3176 }
3177
3178 if (brdc) {
3179 if (sat)
3180 emit_sat(pc, brdc, brdc);
3181 for (c = 0; c < 4; c++)
3182 if ((mask & (1 << c)) && dst[c] != brdc)
3183 emit_mov(pc, dst[c], brdc);
3184 } else
3185 if (sat) {
3186 for (c = 0; c < 4; c++) {
3187 if (!(mask & (1 << c)))
3188 continue;
3189 /* In this case we saturate later, and dst[c] won't
3190 * be another temp_temp (and thus lost), since rdst
3191 * already is TEMP (see above). */
3192 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3193 continue;
3194 emit_sat(pc, rdst[c], dst[c]);
3195 }
3196 }
3197
3198 kill_temp_temp(pc, NULL);
3199 pc->reg_instance_nr = 0;
3200
3201 return TRUE;
3202 }
3203
3204 static void
3205 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3206 {
3207 struct nv50_reg *r, *reg = NULL;
3208 const struct tgsi_full_src_register *src;
3209 const struct tgsi_dst_register *dst;
3210 unsigned i, c, k, mask;
3211
3212 dst = &insn->Dst[0].Register;
3213 mask = dst->WriteMask;
3214
3215 if (dst->File == TGSI_FILE_TEMPORARY)
3216 reg = pc->temp;
3217 else
3218 if (dst->File == TGSI_FILE_OUTPUT) {
3219 reg = pc->result;
3220
3221 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3222 dst->Index == pc->edgeflag_out &&
3223 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3224 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3225 }
3226
3227 if (reg) {
3228 for (c = 0; c < 4; c++) {
3229 if (!(mask & (1 << c)))
3230 continue;
3231 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3232 }
3233 }
3234
3235 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3236 src = &insn->Src[i];
3237
3238 if (src->Register.File == TGSI_FILE_TEMPORARY)
3239 reg = pc->temp;
3240 else
3241 if (src->Register.File == TGSI_FILE_INPUT)
3242 reg = pc->attr;
3243 else
3244 continue;
3245
3246 mask = nv50_tgsi_src_mask(insn, i);
3247
3248 for (c = 0; c < 4; c++) {
3249 if (!(mask & (1 << c)))
3250 continue;
3251 k = tgsi_util_get_full_src_register_swizzle(src, c);
3252
3253 r = &reg[src->Register.Index * 4 + k];
3254
3255 /* If used before written, pre-allocate the reg,
3256 * lest we overwrite results from a subroutine.
3257 */
3258 if (!r->acc && r->type == P_TEMP)
3259 alloc_reg(pc, r);
3260
3261 r->acc = pc->insn_nr;
3262 }
3263 }
3264 }
3265
3266 /* Returns a bitmask indicating which dst components need to be
3267 * written to temporaries first to avoid 'corrupting' sources.
3268 *
3269 * m[i] (out) indicate component to write in the i-th position
3270 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3271 */
3272 static unsigned
3273 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3274 {
3275 unsigned i, c, x, unsafe;
3276
3277 for (c = 0; c < 4; c++)
3278 m[c] = c;
3279
3280 /* Swap as long as a dst component written earlier is depended on
3281 * by one written later, but the next one isn't depended on by it.
3282 */
3283 for (c = 0; c < 3; c++) {
3284 if (rdep[m[c + 1]] & (1 << m[c]))
3285 continue; /* if next one is depended on by us */
3286 for (i = c + 1; i < 4; i++)
3287 /* if we are depended on by a later one */
3288 if (rdep[m[c]] & (1 << m[i]))
3289 break;
3290 if (i == 4)
3291 continue;
3292 /* now, swap */
3293 x = m[c];
3294 m[c] = m[c + 1];
3295 m[c + 1] = x;
3296
3297 /* restart */
3298 c = 0;
3299 }
3300
3301 /* mark dependencies that could not be resolved by reordering */
3302 for (i = 0; i < 3; ++i)
3303 for (c = i + 1; c < 4; ++c)
3304 if (rdep[m[i]] & (1 << m[c]))
3305 unsafe |= (1 << i);
3306
3307 /* NOTE: $unsafe is with respect to order, not component */
3308 return unsafe;
3309 }
3310
3311 /* Select a suitable dst register for broadcasting scalar results,
3312 * or return NULL if we have to allocate an extra TEMP.
3313 *
3314 * If e.g. only 1 component is written, we may also emit the final
3315 * result to a write-only register.
3316 */
3317 static struct nv50_reg *
3318 tgsi_broadcast_dst(struct nv50_pc *pc,
3319 const struct tgsi_full_dst_register *fd, unsigned mask)
3320 {
3321 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3322 int c = ffs(~mask & fd->Register.WriteMask);
3323 if (c)
3324 return tgsi_dst(pc, c - 1, fd);
3325 } else {
3326 int c = ffs(fd->Register.WriteMask) - 1;
3327 if ((1 << c) == fd->Register.WriteMask)
3328 return tgsi_dst(pc, c, fd);
3329 }
3330
3331 return NULL;
3332 }
3333
3334 /* Scan source swizzles and return a bitmask indicating dst regs that
3335 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3336 */
3337 static unsigned
3338 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3339 unsigned rdep[4])
3340 {
3341 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3342 const struct tgsi_full_src_register *fs;
3343 unsigned i, deqs = 0;
3344
3345 for (i = 0; i < 4; ++i)
3346 rdep[i] = 0;
3347
3348 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3349 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3350 int ms = get_supported_mods(insn, i);
3351
3352 fs = &insn->Src[i];
3353 if (fs->Register.File != fd->Register.File ||
3354 fs->Register.Index != fd->Register.Index)
3355 continue;
3356
3357 for (chn = 0; chn < 4; ++chn) {
3358 unsigned s, c;
3359
3360 if (!(mask & (1 << chn))) /* src is not read */
3361 continue;
3362 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3363 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3364
3365 if (!(fd->Register.WriteMask & (1 << c)))
3366 continue;
3367
3368 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3369 continue;
3370 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3371 continue;
3372 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3373 continue;
3374
3375 rdep[c] |= nv50_tgsi_dst_revdep(
3376 insn->Instruction.Opcode, i, chn);
3377 deqs |= (1 << c);
3378 }
3379 }
3380
3381 return deqs;
3382 }
3383
3384 static boolean
3385 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3386 {
3387 struct tgsi_full_instruction insn = tok->FullInstruction;
3388 const struct tgsi_full_dst_register *fd;
3389 unsigned i, deqs, rdep[4], m[4];
3390
3391 fd = &tok->FullInstruction.Dst[0];
3392 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3393
3394 if (is_scalar_op(insn.Instruction.Opcode)) {
3395 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3396 if (!pc->r_brdc)
3397 pc->r_brdc = temp_temp(pc, NULL);
3398 return nv50_program_tx_insn(pc, &insn);
3399 }
3400 pc->r_brdc = NULL;
3401
3402 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3403 return nv50_program_tx_insn(pc, &insn);
3404
3405 deqs = nv50_revdep_reorder(m, rdep);
3406
3407 for (i = 0; i < 4; ++i) {
3408 assert(pc->r_dst[m[i]] == NULL);
3409
3410 insn.Dst[0].Register.WriteMask =
3411 fd->Register.WriteMask & (1 << m[i]);
3412
3413 if (!insn.Dst[0].Register.WriteMask)
3414 continue;
3415
3416 if (deqs & (1 << i))
3417 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3418
3419 if (!nv50_program_tx_insn(pc, &insn))
3420 return FALSE;
3421 }
3422
3423 for (i = 0; i < 4; i++) {
3424 struct nv50_reg *reg = pc->r_dst[i];
3425 if (!reg)
3426 continue;
3427 pc->r_dst[i] = NULL;
3428
3429 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3430 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3431 else
3432 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3433 free_temp(pc, reg);
3434 }
3435
3436 return TRUE;
3437 }
3438
3439 static void
3440 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3441 {
3442 struct nv50_reg *iv, **ppiv;
3443 unsigned mode = pc->interp_mode[reg->index];
3444
3445 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3446 iv = *ppiv;
3447
3448 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3449 iv = *ppiv = alloc_temp(pc, NULL);
3450 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3451
3452 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3453 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3454
3455 /* XXX: when loading interpolants dynamically, move these
3456 * to the program head, or make sure it can't be skipped.
3457 */
3458 }
3459
3460 emit_interp(pc, reg, iv, mode);
3461 }
3462
3463 /* The face input is always at v[255] (varying space), with a
3464 * value of 0 for back-facing, and 0xffffffff for front-facing.
3465 */
3466 static void
3467 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *sv)
3468 {
3469 struct nv50_reg *temp = alloc_temp(pc, NULL);
3470 int r_pred = 0;
3471
3472 temp->rhw = 255;
3473 emit_interp(pc, temp, NULL, INTERP_FLAT);
3474
3475 emit_cvt(pc, sv, temp, r_pred, CVT_ABS | CVT_F32_S32);
3476
3477 emit_not(pc, temp, temp);
3478 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3479 emit_cvt(pc, sv, temp, -1, CVT_F32_S32);
3480 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3481
3482 free_temp(pc, temp);
3483 }
3484
3485 static void
3486 copy_semantic_info(struct nv50_program *p)
3487 {
3488 unsigned i, id;
3489
3490 for (i = 0; i < p->cfg.in_nr; ++i) {
3491 id = p->cfg.in[i].id;
3492 p->cfg.in[i].sn = p->info.input_semantic_name[id];
3493 p->cfg.in[i].si = p->info.input_semantic_index[id];
3494 }
3495
3496 for (i = 0; i < p->cfg.out_nr; ++i) {
3497 id = p->cfg.out[i].id;
3498 p->cfg.out[i].sn = p->info.output_semantic_name[id];
3499 p->cfg.out[i].si = p->info.output_semantic_index[id];
3500 }
3501 }
3502
3503 static boolean
3504 nv50_program_tx_prep(struct nv50_pc *pc)
3505 {
3506 struct tgsi_parse_context tp;
3507 struct nv50_program *p = pc->p;
3508 boolean ret = FALSE;
3509 unsigned i, c, instance_id, vertex_id, flat_nr = 0;
3510
3511 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3512 while (!tgsi_parse_end_of_tokens(&tp)) {
3513 const union tgsi_full_token *tok = &tp.FullToken;
3514
3515 tgsi_parse_token(&tp);
3516 switch (tok->Token.Type) {
3517 case TGSI_TOKEN_TYPE_IMMEDIATE:
3518 {
3519 const struct tgsi_full_immediate *imm =
3520 &tp.FullToken.FullImmediate;
3521
3522 ctor_immd_4f32(pc, imm->u[0].Float,
3523 imm->u[1].Float,
3524 imm->u[2].Float,
3525 imm->u[3].Float);
3526 }
3527 break;
3528 case TGSI_TOKEN_TYPE_DECLARATION:
3529 {
3530 const struct tgsi_full_declaration *d;
3531 unsigned si, last, first, mode;
3532
3533 d = &tp.FullToken.FullDeclaration;
3534 first = d->Range.First;
3535 last = d->Range.Last;
3536
3537 switch (d->Declaration.File) {
3538 case TGSI_FILE_TEMPORARY:
3539 break;
3540 case TGSI_FILE_OUTPUT:
3541 if (!d->Declaration.Semantic ||
3542 p->type == PIPE_SHADER_FRAGMENT)
3543 break;
3544
3545 si = d->Semantic.Index;
3546 switch (d->Semantic.Name) {
3547 case TGSI_SEMANTIC_BCOLOR:
3548 p->cfg.two_side[si].hw = first;
3549 if (p->cfg.out_nr > first)
3550 p->cfg.out_nr = first;
3551 break;
3552 case TGSI_SEMANTIC_PSIZE:
3553 p->cfg.psiz = first;
3554 if (p->cfg.out_nr > first)
3555 p->cfg.out_nr = first;
3556 break;
3557 case TGSI_SEMANTIC_EDGEFLAG:
3558 pc->edgeflag_out = first;
3559 break;
3560 /*
3561 case TGSI_SEMANTIC_CLIP_DISTANCE:
3562 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3563 break;
3564 */
3565 default:
3566 break;
3567 }
3568 break;
3569 case TGSI_FILE_INPUT:
3570 {
3571 if (p->type != PIPE_SHADER_FRAGMENT)
3572 break;
3573
3574 switch (d->Declaration.Interpolate) {
3575 case TGSI_INTERPOLATE_CONSTANT:
3576 mode = INTERP_FLAT;
3577 flat_nr++;
3578 break;
3579 case TGSI_INTERPOLATE_PERSPECTIVE:
3580 mode = INTERP_PERSPECTIVE;
3581 p->cfg.regs[1] |= 0x08 << 24;
3582 break;
3583 default:
3584 mode = INTERP_LINEAR;
3585 break;
3586 }
3587 if (d->Declaration.Centroid)
3588 mode |= INTERP_CENTROID;
3589
3590 assert(last < 32);
3591 for (i = first; i <= last; i++)
3592 pc->interp_mode[i] = mode;
3593 }
3594 break;
3595 case TGSI_FILE_SYSTEM_VALUE:
3596 assert(d->Declaration.Semantic);
3597 switch (d->Semantic.Name) {
3598 case TGSI_SEMANTIC_FACE:
3599 assert(p->type == PIPE_SHADER_FRAGMENT);
3600 load_frontfacing(pc,
3601 &pc->sysval[first]);
3602 break;
3603 case TGSI_SEMANTIC_INSTANCEID:
3604 assert(p->type == PIPE_SHADER_VERTEX);
3605 instance_id = first;
3606 p->cfg.regs[0] |= (1 << 4);
3607 break;
3608 case TGSI_SEMANTIC_PRIMID:
3609 assert(p->type != PIPE_SHADER_VERTEX);
3610 p->cfg.prim_id = first;
3611 break;
3612 /*
3613 case TGSI_SEMANTIC_PRIMIDIN:
3614 assert(p->type == PIPE_SHADER_GEOMETRY);
3615 pc->sysval[first].hw = 6;
3616 p->cfg.regs[0] |= (1 << 8);
3617 break;
3618 case TGSI_SEMANTIC_VERTEXID:
3619 assert(p->type == PIPE_SHADER_VERTEX);
3620 vertex_id = first;
3621 p->cfg.regs[0] |= (1 << 12) | (1 << 0);
3622 break;
3623 */
3624 }
3625 break;
3626 case TGSI_FILE_ADDRESS:
3627 case TGSI_FILE_CONSTANT:
3628 case TGSI_FILE_SAMPLER:
3629 break;
3630 default:
3631 NOUVEAU_ERR("bad decl file %d\n",
3632 d->Declaration.File);
3633 goto out_err;
3634 }
3635 }
3636 break;
3637 case TGSI_TOKEN_TYPE_INSTRUCTION:
3638 pc->insn_nr++;
3639 prep_inspect_insn(pc, &tok->FullInstruction);
3640 break;
3641 default:
3642 break;
3643 }
3644 }
3645
3646 if (p->type == PIPE_SHADER_VERTEX || p->type == PIPE_SHADER_GEOMETRY) {
3647 int rid = 0;
3648
3649 if (p->type == PIPE_SHADER_GEOMETRY) {
3650 for (i = 0; i < pc->attr_nr; ++i) {
3651 p->cfg.in[i].hw = rid;
3652 p->cfg.in[i].id = i;
3653
3654 for (c = 0; c < 4; ++c) {
3655 int n = i * 4 + c;
3656 if (!pc->attr[n].acc)
3657 continue;
3658 pc->attr[n].hw = rid++;
3659 p->cfg.in[i].mask |= 1 << c;
3660 }
3661 }
3662 } else {
3663 for (i = 0; i < pc->attr_nr * 4; ++i) {
3664 if (pc->attr[i].acc) {
3665 pc->attr[i].hw = rid++;
3666 p->cfg.attr[i / 32] |= 1 << (i % 32);
3667 }
3668 }
3669 if (p->cfg.regs[0] & (1 << 0))
3670 pc->sysval[vertex_id].hw = rid++;
3671 if (p->cfg.regs[0] & (1 << 4))
3672 pc->sysval[instance_id].hw = rid++;
3673 }
3674
3675 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3676 p->cfg.out[i].hw = rid;
3677 p->cfg.out[i].id = i;
3678
3679 for (c = 0; c < 4; ++c) {
3680 int n = i * 4 + c;
3681 if (!pc->result[n].acc)
3682 continue;
3683 pc->result[n].hw = rid++;
3684 p->cfg.out[i].mask |= 1 << c;
3685 }
3686 }
3687 if (p->cfg.prim_id < 0x40) {
3688 /* GP has to write to PrimitiveID */
3689 ctor_reg(&pc->sysval[p->cfg.prim_id],
3690 P_RESULT, p->cfg.prim_id, rid);
3691 p->cfg.prim_id = rid++;
3692 }
3693
3694 for (c = 0; c < 2; ++c)
3695 if (p->cfg.two_side[c].hw < 0x40)
3696 p->cfg.two_side[c] = p->cfg.out[
3697 p->cfg.two_side[c].hw];
3698
3699 if (p->cfg.psiz < 0x40)
3700 p->cfg.psiz = p->cfg.out[p->cfg.psiz].hw;
3701
3702 copy_semantic_info(p);
3703 } else
3704 if (p->type == PIPE_SHADER_FRAGMENT) {
3705 int rid, aid, base;
3706 unsigned n = 0, m = pc->attr_nr - flat_nr;
3707
3708 pc->allow32 = TRUE;
3709
3710 base = (TGSI_SEMANTIC_POSITION ==
3711 p->info.input_semantic_name[0]) ? 0 : 1;
3712
3713 /* non-flat interpolants have to be mapped to
3714 * the lower hardware IDs, so sort them:
3715 */
3716 for (i = 0; i < pc->attr_nr; i++) {
3717 if (pc->interp_mode[i] == INTERP_FLAT)
3718 p->cfg.in[m++].id = i;
3719 else {
3720 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3721 p->cfg.in[n].linear = TRUE;
3722 p->cfg.in[n++].id = i;
3723 }
3724 }
3725 copy_semantic_info(p);
3726
3727 if (!base) /* set w-coordinate mask from perspective interp */
3728 p->cfg.in[0].mask |= p->cfg.regs[1] >> 24;
3729
3730 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3731 base ? (p->cfg.regs[1] >> 24) : p->cfg.in[0].mask);
3732
3733 for (n = 0; n < pc->attr_nr; ++n) {
3734 p->cfg.in[n].hw = rid = aid;
3735 i = p->cfg.in[n].id;
3736
3737 if (p->info.input_semantic_name[n] ==
3738 TGSI_SEMANTIC_FACE) {
3739 load_frontfacing(pc, &pc->attr[i * 4]);
3740 continue;
3741 }
3742
3743 for (c = 0; c < 4; ++c) {
3744 if (!pc->attr[i * 4 + c].acc)
3745 continue;
3746 pc->attr[i * 4 + c].rhw = rid++;
3747 p->cfg.in[n].mask |= 1 << c;
3748
3749 load_interpolant(pc, &pc->attr[i * 4 + c]);
3750 }
3751 aid += popcnt4(p->cfg.in[n].mask);
3752 }
3753
3754 if (!base)
3755 p->cfg.regs[1] |= p->cfg.in[0].mask << 24;
3756
3757 m = popcnt4(p->cfg.regs[1] >> 24);
3758
3759 /* set count of non-position inputs and of non-flat
3760 * non-position inputs for FP_INTERPOLANT_CTRL
3761 */
3762 p->cfg.regs[1] |= aid - m;
3763
3764 if (flat_nr) {
3765 i = p->cfg.in[pc->attr_nr - flat_nr].hw;
3766 p->cfg.regs[1] |= (i - m) << 16;
3767 } else
3768 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3769
3770 /* mark color semantic for light-twoside */
3771 n = 0x80;
3772 for (i = 0; i < p->cfg.in_nr; i++) {
3773 if (p->cfg.in[i].sn == TGSI_SEMANTIC_COLOR) {
3774 n = MIN2(n, p->cfg.in[i].hw - m);
3775 p->cfg.two_side[p->cfg.in[i].si] = p->cfg.in[i];
3776
3777 p->cfg.regs[0] += /* increase colour count */
3778 popcnt4(p->cfg.in[i].mask) << 16;
3779 }
3780 }
3781 if (n < 0x80)
3782 p->cfg.regs[0] += n;
3783
3784 if (p->cfg.prim_id < 0x40) {
3785 pc->sysval[p->cfg.prim_id].rhw = rid++;
3786 emit_interp(pc, &pc->sysval[p->cfg.prim_id], NULL,
3787 INTERP_FLAT);
3788 /* increase FP_INTERPOLANT_CTRL_COUNT */
3789 p->cfg.regs[1] += 1;
3790 }
3791
3792 /* Initialize FP results:
3793 * FragDepth is always first TGSI and last hw output
3794 */
3795 i = p->info.writes_z ? 4 : 0;
3796 for (rid = 0; i < pc->result_nr * 4; i++)
3797 pc->result[i].rhw = rid++;
3798 if (p->info.writes_z)
3799 pc->result[2].rhw = rid;
3800
3801 p->cfg.high_result = rid;
3802
3803 /* separate/different colour results for MRTs ? */
3804 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3805 p->cfg.regs[2] |= 1;
3806 }
3807
3808 if (pc->immd_nr) {
3809 int rid = 0;
3810
3811 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3812 if (!pc->immd)
3813 goto out_err;
3814
3815 for (i = 0; i < pc->immd_nr; i++) {
3816 for (c = 0; c < 4; c++, rid++)
3817 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3818 }
3819 }
3820
3821 ret = TRUE;
3822 out_err:
3823 if (pc->iv_p)
3824 free_temp(pc, pc->iv_p);
3825 if (pc->iv_c)
3826 free_temp(pc, pc->iv_c);
3827
3828 tgsi_parse_free(&tp);
3829 return ret;
3830 }
3831
3832 static void
3833 free_nv50_pc(struct nv50_pc *pc)
3834 {
3835 if (pc->immd)
3836 FREE(pc->immd);
3837 if (pc->param)
3838 FREE(pc->param);
3839 if (pc->result)
3840 FREE(pc->result);
3841 if (pc->attr)
3842 FREE(pc->attr);
3843 if (pc->temp)
3844 FREE(pc->temp);
3845 if (pc->sysval)
3846 FREE(pc->sysval);
3847 if (pc->insn_pos)
3848 FREE(pc->insn_pos);
3849
3850 FREE(pc);
3851 }
3852
3853 static INLINE uint32_t
3854 nv50_map_gs_output_prim(unsigned pprim)
3855 {
3856 switch (pprim) {
3857 case PIPE_PRIM_POINTS:
3858 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
3859 case PIPE_PRIM_LINE_STRIP:
3860 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
3861 case PIPE_PRIM_TRIANGLE_STRIP:
3862 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
3863 default:
3864 NOUVEAU_ERR("invalid GS_OUTPUT_PRIMITIVE: %u\n", pprim);
3865 abort();
3866 return 0;
3867 }
3868 }
3869
3870 static boolean
3871 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3872 {
3873 int i, c;
3874 unsigned rtype[2] = { P_ATTR, P_RESULT };
3875
3876 pc->p = p;
3877 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3878 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3879 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3880 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3881 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3882 assert(pc->addr_nr <= 2);
3883 pc->sysval_nr = p->info.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
3884
3885 p->cfg.high_temp = 4;
3886
3887 p->cfg.two_side[0].hw = 0x40;
3888 p->cfg.two_side[1].hw = 0x40;
3889 p->cfg.prim_id = 0x40;
3890
3891 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3892
3893 for (i = 0; i < p->info.num_properties; ++i) {
3894 unsigned *data = &p->info.properties[i].data[0];
3895
3896 switch (p->info.properties[i].name) {
3897 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
3898 p->cfg.prim_type = nv50_map_gs_output_prim(data[0]);
3899 break;
3900 case TGSI_PROPERTY_GS_MAX_VERTICES:
3901 p->cfg.vert_count = data[0];
3902 break;
3903 default:
3904 break;
3905 }
3906 }
3907
3908 switch (p->type) {
3909 case PIPE_SHADER_VERTEX:
3910 p->cfg.psiz = 0x40;
3911 p->cfg.clpd = 0x40;
3912 p->cfg.out_nr = pc->result_nr;
3913 break;
3914 case PIPE_SHADER_GEOMETRY:
3915 assert(p->cfg.prim_type);
3916 assert(p->cfg.vert_count);
3917
3918 p->cfg.psiz = 0x80;
3919 p->cfg.clpd = 0x80;
3920 p->cfg.prim_id = 0x80;
3921 p->cfg.out_nr = pc->result_nr;
3922 p->cfg.in_nr = pc->attr_nr;
3923
3924 p->cfg.two_side[0].hw = 0x80;
3925 p->cfg.two_side[1].hw = 0x80;
3926 break;
3927 case PIPE_SHADER_FRAGMENT:
3928 rtype[0] = rtype[1] = P_TEMP;
3929
3930 p->cfg.regs[0] = 0x01000004;
3931 p->cfg.in_nr = pc->attr_nr;
3932
3933 if (p->info.writes_z) {
3934 p->cfg.regs[2] |= 0x00000100;
3935 p->cfg.regs[3] |= 0x00000011;
3936 }
3937 if (p->info.uses_kill)
3938 p->cfg.regs[2] |= 0x00100000;
3939 break;
3940 }
3941
3942 if (pc->temp_nr) {
3943 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3944 if (!pc->temp)
3945 return FALSE;
3946
3947 for (i = 0; i < pc->temp_nr * 4; ++i)
3948 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3949 }
3950
3951 if (pc->attr_nr) {
3952 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3953 if (!pc->attr)
3954 return FALSE;
3955
3956 for (i = 0; i < pc->attr_nr * 4; ++i)
3957 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3958 }
3959
3960 if (pc->result_nr) {
3961 unsigned nr = pc->result_nr * 4;
3962
3963 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3964 if (!pc->result)
3965 return FALSE;
3966
3967 for (i = 0; i < nr; ++i)
3968 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3969 }
3970
3971 if (pc->param_nr) {
3972 int rid = 0;
3973
3974 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3975 if (!pc->param)
3976 return FALSE;
3977
3978 for (i = 0; i < pc->param_nr; ++i)
3979 for (c = 0; c < 4; ++c, ++rid)
3980 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3981 }
3982
3983 if (pc->addr_nr) {
3984 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3985 if (!pc->addr)
3986 return FALSE;
3987 }
3988 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3989 ctor_reg(&pc->r_addr[i], P_ADDR, -1, i + 1);
3990
3991 if (pc->sysval_nr) {
3992 pc->sysval = CALLOC(pc->sysval_nr, sizeof(struct nv50_reg *));
3993 if (!pc->sysval)
3994 return FALSE;
3995 /* will only ever use SYSTEM_VALUE[i].x (hopefully) */
3996 for (i = 0; i < pc->sysval_nr; ++i)
3997 ctor_reg(&pc->sysval[i], rtype[0], i, -1);
3998 }
3999
4000 return TRUE;
4001 }
4002
4003 static void
4004 nv50_program_fixup_insns(struct nv50_pc *pc)
4005 {
4006 struct nv50_program_exec *e, **bra_list;
4007 unsigned i, n, pos;
4008
4009 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
4010
4011 /* Collect branch instructions, we need to adjust their offsets
4012 * when converting 32 bit instructions to 64 bit ones
4013 */
4014 for (n = 0, e = pc->p->exec_head; e; e = e->next)
4015 if (e->param.index >= 0 && !e->param.mask)
4016 bra_list[n++] = e;
4017
4018 /* Make sure we don't have any single 32 bit instructions. */
4019 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
4020 pos += is_long(e) ? 2 : 1;
4021
4022 if ((pos & 1) && (!e->next || is_long(e->next))) {
4023 for (i = 0; i < n; ++i)
4024 if (bra_list[i]->param.index >= pos)
4025 bra_list[i]->param.index += 1;
4026 for (i = 0; i < pc->insn_nr; ++i)
4027 if (pc->insn_pos[i] >= pos)
4028 pc->insn_pos[i] += 1;
4029 convert_to_long(pc, e);
4030 ++pos;
4031 }
4032 }
4033
4034 FREE(bra_list);
4035
4036 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
4037 return;
4038
4039 /* fill in CALL offsets */
4040 for (e = pc->p->exec_head; e; e = e->next) {
4041 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
4042 e->param.index = pc->insn_pos[e->param.index];
4043 }
4044 }
4045
4046 static boolean
4047 nv50_program_tx(struct nv50_program *p)
4048 {
4049 struct tgsi_parse_context parse;
4050 struct nv50_pc *pc;
4051 boolean ret;
4052
4053 pc = CALLOC_STRUCT(nv50_pc);
4054 if (!pc)
4055 return FALSE;
4056
4057 ret = ctor_nv50_pc(pc, p);
4058 if (ret == FALSE)
4059 goto out_cleanup;
4060
4061 ret = nv50_program_tx_prep(pc);
4062 if (ret == FALSE)
4063 goto out_cleanup;
4064
4065 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
4066
4067 tgsi_parse_init(&parse, pc->p->pipe.tokens);
4068 while (!tgsi_parse_end_of_tokens(&parse)) {
4069 const union tgsi_full_token *tok = &parse.FullToken;
4070
4071 /* previously allow32 was FALSE for first & last instruction */
4072 pc->allow32 = TRUE;
4073
4074 tgsi_parse_token(&parse);
4075
4076 switch (tok->Token.Type) {
4077 case TGSI_TOKEN_TYPE_INSTRUCTION:
4078 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
4079 ++pc->insn_cur;
4080 ret = nv50_tgsi_insn(pc, tok);
4081 if (ret == FALSE)
4082 goto out_err;
4083 break;
4084 default:
4085 break;
4086 }
4087 }
4088
4089 nv50_program_fixup_insns(pc);
4090
4091 p->param_nr = pc->param_nr * 4;
4092 p->immd_nr = pc->immd_nr * 4;
4093 p->immd = pc->immd_buf;
4094
4095 out_err:
4096 tgsi_parse_free(&parse);
4097
4098 out_cleanup:
4099 free_nv50_pc(pc);
4100 return ret;
4101 }
4102
4103 static void
4104 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
4105 {
4106 if (nv50_program_tx(p) == FALSE)
4107 assert(0);
4108 p->translated = TRUE;
4109 }
4110
4111 static void
4112 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
4113 unsigned start, unsigned count, unsigned cbuf)
4114 {
4115 struct nouveau_channel *chan = nv50->screen->base.channel;
4116 struct nouveau_grobj *tesla = nv50->screen->tesla;
4117
4118 while (count) {
4119 unsigned nr = count > 2047 ? 2047 : count;
4120
4121 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
4122 OUT_RING (chan, (cbuf << 0) | (start << 8));
4123 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
4124 OUT_RINGp (chan, map, nr);
4125
4126 map += nr;
4127 start += nr;
4128 count -= nr;
4129 }
4130 }
4131
4132 static void
4133 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
4134 {
4135 struct pipe_screen *pscreen = nv50->pipe.screen;
4136
4137 if (!p->data[0] && p->immd_nr) {
4138 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
4139
4140 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
4141 while (heap->next && heap->size < p->immd_nr) {
4142 struct nv50_program *evict = heap->next->priv;
4143 nouveau_resource_free(&evict->data[0]);
4144 }
4145
4146 if (nouveau_resource_alloc(heap, p->immd_nr, p,
4147 &p->data[0]))
4148 assert(0);
4149 }
4150
4151 /* immediates only need to be uploaded again when freed */
4152 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
4153 p->immd_nr, NV50_CB_PMISC);
4154 }
4155
4156 assert(p->param_nr <= 512);
4157
4158 if (p->param_nr) {
4159 unsigned cb;
4160 uint32_t *map = pipe_buffer_map(pscreen,
4161 nv50->constbuf[p->type],
4162 PIPE_BUFFER_USAGE_CPU_READ);
4163 switch (p->type) {
4164 case PIPE_SHADER_GEOMETRY: cb = NV50_CB_PGP; break;
4165 case PIPE_SHADER_FRAGMENT: cb = NV50_CB_PFP; break;
4166 default:
4167 cb = NV50_CB_PVP;
4168 assert(p->type == PIPE_SHADER_VERTEX);
4169 break;
4170 }
4171
4172 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
4173 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
4174 }
4175 }
4176
4177 static void
4178 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
4179 {
4180 struct nouveau_channel *chan = nv50->screen->base.channel;
4181 struct nv50_program_exec *e;
4182 uint32_t *up, i;
4183 boolean upload = FALSE;
4184
4185 if (!p->bo) {
4186 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
4187 p->exec_size * 4, &p->bo);
4188 upload = TRUE;
4189 }
4190
4191 if (p->data[0] && p->data[0]->start != p->data_start[0])
4192 upload = TRUE;
4193
4194 if (!upload)
4195 return;
4196
4197 up = MALLOC(p->exec_size * 4);
4198
4199 for (i = 0, e = p->exec_head; e; e = e->next) {
4200 unsigned ei, ci, bs;
4201
4202 if (e->param.index >= 0 && e->param.mask) {
4203 bs = (e->inst[1] >> 22) & 0x07;
4204 assert(bs < 2);
4205 ei = e->param.shift >> 5;
4206 ci = e->param.index;
4207 if (bs == 0)
4208 ci += p->data[bs]->start;
4209
4210 e->inst[ei] &= ~e->param.mask;
4211 e->inst[ei] |= (ci << e->param.shift);
4212 } else
4213 if (e->param.index >= 0) {
4214 /* zero mask means param is a jump/branch offset */
4215 assert(!(e->param.index & 1));
4216 /* seem to be 8 byte steps */
4217 ei = (e->param.index >> 1) + 0 /* START_ID */;
4218
4219 e->inst[0] &= 0xf0000fff;
4220 e->inst[0] |= ei << 12;
4221 }
4222
4223 up[i++] = e->inst[0];
4224 if (is_long(e))
4225 up[i++] = e->inst[1];
4226 }
4227 assert(i == p->exec_size);
4228
4229 if (p->data[0])
4230 p->data_start[0] = p->data[0]->start;
4231
4232 #ifdef NV50_PROGRAM_DUMP
4233 NOUVEAU_ERR("-------\n");
4234 for (e = p->exec_head; e; e = e->next) {
4235 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
4236 if (is_long(e))
4237 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
4238 }
4239 #endif
4240 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
4241 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
4242 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
4243 0, 0, p->exec_size * 4, 1, 1);
4244
4245 FREE(up);
4246 }
4247
4248 void
4249 nv50_vertprog_validate(struct nv50_context *nv50)
4250 {
4251 struct nouveau_grobj *tesla = nv50->screen->tesla;
4252 struct nv50_program *p = nv50->vertprog;
4253 struct nouveau_stateobj *so;
4254
4255 if (!p->translated) {
4256 nv50_program_validate(nv50, p);
4257 if (!p->translated)
4258 assert(0);
4259 }
4260
4261 nv50_program_validate_data(nv50, p);
4262 nv50_program_validate_code(nv50, p);
4263
4264 so = so_new(5, 7, 2);
4265 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
4266 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4267 NOUVEAU_BO_HIGH, 0, 0);
4268 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4269 NOUVEAU_BO_LOW, 0, 0);
4270 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
4271 so_data (so, p->cfg.attr[0]);
4272 so_data (so, p->cfg.attr[1]);
4273 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
4274 so_data (so, p->cfg.high_result);
4275 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_TEMP, 1);
4276 so_data (so, p->cfg.high_temp);
4277 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
4278 so_data (so, 0); /* program start offset */
4279 so_ref(so, &nv50->state.vertprog);
4280 so_ref(NULL, &so);
4281 }
4282
4283 void
4284 nv50_fragprog_validate(struct nv50_context *nv50)
4285 {
4286 struct nouveau_grobj *tesla = nv50->screen->tesla;
4287 struct nv50_program *p = nv50->fragprog;
4288 struct nouveau_stateobj *so;
4289
4290 if (!p->translated) {
4291 nv50_program_validate(nv50, p);
4292 if (!p->translated)
4293 assert(0);
4294 }
4295
4296 nv50_program_validate_data(nv50, p);
4297 nv50_program_validate_code(nv50, p);
4298
4299 so = so_new(6, 7, 2);
4300 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4301 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4302 NOUVEAU_BO_HIGH, 0, 0);
4303 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4304 NOUVEAU_BO_LOW, 0, 0);
4305 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4306 so_data (so, p->cfg.high_temp);
4307 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4308 so_data (so, p->cfg.high_result);
4309 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4310 so_data (so, p->cfg.regs[2]);
4311 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4312 so_data (so, p->cfg.regs[3]);
4313 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4314 so_data (so, 0); /* program start offset */
4315 so_ref(so, &nv50->state.fragprog);
4316 so_ref(NULL, &so);
4317 }
4318
4319 void
4320 nv50_geomprog_validate(struct nv50_context *nv50)
4321 {
4322 struct nouveau_grobj *tesla = nv50->screen->tesla;
4323 struct nv50_program *p = nv50->geomprog;
4324 struct nouveau_stateobj *so;
4325
4326 if (!p->translated) {
4327 nv50_program_validate(nv50, p);
4328 if (!p->translated)
4329 assert(0);
4330 }
4331
4332 nv50_program_validate_data(nv50, p);
4333 nv50_program_validate_code(nv50, p);
4334
4335 so = so_new(6, 7, 2);
4336 so_method(so, tesla, NV50TCL_GP_ADDRESS_HIGH, 2);
4337 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4338 NOUVEAU_BO_HIGH, 0, 0);
4339 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4340 NOUVEAU_BO_LOW, 0, 0);
4341 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_TEMP, 1);
4342 so_data (so, p->cfg.high_temp);
4343 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_RESULT, 1);
4344 so_data (so, p->cfg.high_result);
4345 so_method(so, tesla, NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE, 1);
4346 so_data (so, p->cfg.prim_type);
4347 so_method(so, tesla, NV50TCL_GP_VERTEX_OUTPUT_COUNT, 1);
4348 so_data (so, p->cfg.vert_count);
4349 so_method(so, tesla, NV50TCL_GP_START_ID, 1);
4350 so_data (so, 0);
4351 so_ref(so, &nv50->state.geomprog);
4352 so_ref(NULL, &so);
4353 }
4354
4355 static uint32_t
4356 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4357 {
4358 struct nv50_program *vp;
4359 struct nv50_program *fp = nv50->fragprog;
4360 unsigned i, c, m = base;
4361 uint32_t origin = 0x00000010;
4362
4363 vp = nv50->geomprog ? nv50->geomprog : nv50->vertprog;
4364
4365 /* XXX: this might not work correctly in all cases yet - we'll
4366 * just assume that an FP generic input that is not written in
4367 * the VP is PointCoord.
4368 */
4369 memset(pntc, 0, 8 * sizeof(uint32_t));
4370
4371 for (i = 0; i < fp->cfg.in_nr; i++) {
4372 unsigned j, n = popcnt4(fp->cfg.in[i].mask);
4373
4374 if (fp->cfg.in[i].sn != TGSI_SEMANTIC_GENERIC) {
4375 m += n;
4376 continue;
4377 }
4378
4379 for (j = 0; j < vp->cfg.out_nr; ++j)
4380 if (vp->cfg.out[j].sn == fp->cfg.in[i].sn &&
4381 vp->cfg.out[j].si == fp->cfg.in[i].si)
4382 break;
4383
4384 if (j < vp->cfg.out_nr) {
4385 ubyte mode = nv50->rasterizer->pipe.sprite_coord_mode[
4386 vp->cfg.out[j].si];
4387
4388 if (mode == PIPE_SPRITE_COORD_NONE) {
4389 m += n;
4390 continue;
4391 } else
4392 if (mode == PIPE_SPRITE_COORD_LOWER_LEFT)
4393 origin = 0;
4394 }
4395
4396 /* this is either PointCoord or replaced by sprite coords */
4397 for (c = 0; c < 4; c++) {
4398 if (!(fp->cfg.in[i].mask & (1 << c)))
4399 continue;
4400 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4401 ++m;
4402 }
4403 }
4404 return origin;
4405 }
4406
4407 static int
4408 nv50_vec4_map(uint32_t *map32, int mid, uint8_t zval, uint32_t lin[4],
4409 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4410 {
4411 int c;
4412 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4413 uint8_t *map = (uint8_t *)map32;
4414
4415 for (c = 0; c < 4; ++c) {
4416 if (mf & 1) {
4417 if (fpi->linear == TRUE)
4418 lin[mid / 32] |= 1 << (mid % 32);
4419 if (mv & 1)
4420 map[mid] = oid;
4421 else
4422 map[mid] = (c == 3) ? (zval + 1) : zval;
4423 ++mid;
4424 }
4425
4426 oid += mv & 1;
4427 mf >>= 1;
4428 mv >>= 1;
4429 }
4430
4431 return mid;
4432 }
4433
4434 void
4435 nv50_fp_linkage_validate(struct nv50_context *nv50)
4436 {
4437 struct nouveau_grobj *tesla = nv50->screen->tesla;
4438 struct nv50_program *vp = nv50->vertprog;
4439 struct nv50_program *fp = nv50->fragprog;
4440 struct nouveau_stateobj *so;
4441 struct nv50_sreg4 dummy;
4442 int i, n, c, m = 0;
4443 uint32_t map[16], lin[4], reg[6], pcrd[8];
4444 uint8_t zval = 0x40;
4445
4446 if (nv50->geomprog) {
4447 vp = nv50->geomprog;
4448 zval = 0x80;
4449 }
4450 memset(map, 0, sizeof(map));
4451 memset(lin, 0, sizeof(lin));
4452
4453 reg[1] = 0x00000004; /* low and high clip distance map ids */
4454 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4455 reg[3] = 0x00000000; /* point size map id & enable */
4456 reg[5] = 0x00000000; /* primitive ID map slot */
4457 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4458 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4459
4460 dummy.linear = FALSE;
4461 dummy.mask = 0xf; /* map all components of HPOS */
4462 m = nv50_vec4_map(map, m, zval, lin, &dummy, &vp->cfg.out[0]);
4463
4464 dummy.mask = 0x0;
4465
4466 if (vp->cfg.clpd < 0x40) {
4467 for (c = 0; c < vp->cfg.clpd_nr; ++c) {
4468 map[m / 4] |= (vp->cfg.clpd + c) << ((m % 4) * 8);
4469 ++m;
4470 }
4471 reg[1] = (m << 8);
4472 }
4473
4474 reg[0] |= m << 8; /* adjust BFC0 id */
4475
4476 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4477 if (nv50->rasterizer->pipe.light_twoside) {
4478 struct nv50_sreg4 *vpo = &vp->cfg.two_side[0];
4479 struct nv50_sreg4 *fpi = &fp->cfg.two_side[0];
4480
4481 m = nv50_vec4_map(map, m, zval, lin, &fpi[0], &vpo[0]);
4482 m = nv50_vec4_map(map, m, zval, lin, &fpi[1], &vpo[1]);
4483 }
4484
4485 reg[0] += m - 4; /* adjust FFC0 id */
4486 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4487
4488 for (i = 0; i < fp->cfg.in_nr; i++) {
4489 /* maybe even remove these from cfg.io */
4490 if (fp->cfg.in[i].sn == TGSI_SEMANTIC_POSITION ||
4491 fp->cfg.in[i].sn == TGSI_SEMANTIC_FACE)
4492 continue;
4493
4494 for (n = 0; n < vp->cfg.out_nr; ++n)
4495 if (vp->cfg.out[n].sn == fp->cfg.in[i].sn &&
4496 vp->cfg.out[n].si == fp->cfg.in[i].si)
4497 break;
4498
4499 m = nv50_vec4_map(map, m, zval, lin, &fp->cfg.in[i],
4500 (n < vp->cfg.out_nr) ?
4501 &vp->cfg.out[n] : &dummy);
4502 }
4503 /* PrimitiveID either is replaced by the system value, or
4504 * written by the geometry shader into an output register
4505 */
4506 if (fp->cfg.prim_id < 0x40) {
4507 map[m / 4] |= vp->cfg.prim_id << ((m % 4) * 8);
4508 reg[5] = m++;
4509 }
4510
4511 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4512 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4513 reg[3] = (m++ << 4) | 1;
4514 }
4515
4516 /* now fill the stateobj (at most 28 so_data) */
4517 so = so_new(10, 54, 0);
4518
4519 n = (m + 3) / 4;
4520 assert(m <= 32);
4521 if (vp->type == PIPE_SHADER_GEOMETRY) {
4522 so_method(so, tesla, NV50TCL_GP_RESULT_MAP_SIZE, 1);
4523 so_data (so, m);
4524 so_method(so, tesla, NV50TCL_GP_RESULT_MAP(0), n);
4525 so_datap (so, map, n);
4526 } else {
4527 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4528 so_data (so, vp->cfg.regs[0]);
4529
4530 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_4, 1);
4531 so_data (so, reg[5]);
4532
4533 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4534 so_data (so, m);
4535 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4536 so_datap (so, map, n);
4537 }
4538
4539 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4540 so_datap (so, reg, 4);
4541
4542 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4543 so_data (so, reg[4]);
4544
4545 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4546 so_datap (so, lin, 4);
4547
4548 if (nv50->rasterizer->pipe.point_sprite) {
4549 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4550 so_data (so,
4551 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4552
4553 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4554 so_datap (so, pcrd, 8);
4555 }
4556
4557 so_method(so, tesla, NV50TCL_GP_ENABLE, 1);
4558 so_data (so, (vp->type == PIPE_SHADER_GEOMETRY) ? 1 : 0);
4559
4560 so_ref(so, &nv50->state.fp_linkage);
4561 so_ref(NULL, &so);
4562 }
4563
4564 static int
4565 construct_vp_gp_mapping(uint32_t *map32, int m,
4566 struct nv50_program *vp, struct nv50_program *gp)
4567 {
4568 uint8_t *map = (uint8_t *)map32;
4569 int i, j, c;
4570
4571 for (i = 0; i < gp->cfg.in_nr; ++i) {
4572 uint8_t oid, mv = 0, mg = gp->cfg.in[i].mask;
4573
4574 for (j = 0; j < vp->cfg.out_nr; ++j) {
4575 if (vp->cfg.out[j].sn == gp->cfg.in[i].sn &&
4576 vp->cfg.out[j].si == gp->cfg.in[i].si) {
4577 mv = vp->cfg.out[j].mask;
4578 oid = vp->cfg.out[j].hw;
4579 break;
4580 }
4581 }
4582
4583 for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
4584 if (mg & mv & 1)
4585 map[m++] = oid;
4586 else
4587 if (mg & 1)
4588 map[m++] = (c == 3) ? 0x41 : 0x40;
4589 oid += mv & 1;
4590 }
4591 }
4592 return m;
4593 }
4594
4595 void
4596 nv50_gp_linkage_validate(struct nv50_context *nv50)
4597 {
4598 struct nouveau_grobj *tesla = nv50->screen->tesla;
4599 struct nouveau_stateobj *so;
4600 struct nv50_program *vp = nv50->vertprog;
4601 struct nv50_program *gp = nv50->geomprog;
4602 uint32_t map[16];
4603 int m = 0;
4604
4605 if (!gp) {
4606 so_ref(NULL, &nv50->state.gp_linkage);
4607 return;
4608 }
4609 memset(map, 0, sizeof(map));
4610
4611 m = construct_vp_gp_mapping(map, m, vp, gp);
4612
4613 so = so_new(3, 24 - 3, 0);
4614
4615 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4616 so_data (so, vp->cfg.regs[0] | gp->cfg.regs[0]);
4617
4618 assert(m <= 32);
4619 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4620 so_data (so, m);
4621
4622 m = (m + 3) / 4;
4623 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), m);
4624 so_datap (so, map, m);
4625
4626 so_ref(so, &nv50->state.gp_linkage);
4627 so_ref(NULL, &so);
4628 }
4629
4630 void
4631 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4632 {
4633 while (p->exec_head) {
4634 struct nv50_program_exec *e = p->exec_head;
4635
4636 p->exec_head = e->next;
4637 FREE(e);
4638 }
4639 p->exec_tail = NULL;
4640 p->exec_size = 0;
4641
4642 nouveau_bo_ref(NULL, &p->bo);
4643
4644 nouveau_resource_free(&p->data[0]);
4645
4646 p->translated = 0;
4647 }