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nv50: cleanup emit_kil
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 64
35 //#define NV50_PROGRAM_DUMP
36
37 /* ARL - gallium craps itself on progs/vp/arl.txt
38 *
39 * MSB - Like MAD, but MUL+SUB
40 * - Fuck it off, introduce a way to negate args for ops that
41 * support it.
42 *
43 * Look into inlining IMMD for ops other than MOV (make it general?)
44 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
45 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
46 *
47 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
48 * case, if the emit_src() causes the inst to suddenly become long.
49 *
50 * Verify half-insns work where expected - and force disable them where they
51 * don't work - MUL has it forcibly disabled atm as it fixes POW..
52 *
53 * FUCK! watch dst==src vectors, can overwrite components that are needed.
54 * ie. SUB R0, R0.yzxw, R0
55 *
56 * Things to check with renouveau:
57 * FP attr/result assignment - how?
58 * attrib
59 * - 0x16bc maps vp output onto fp hpos
60 * - 0x16c0 maps vp output onto fp col0
61 * result
62 * - colr always 0-3
63 * - depr always 4
64 * 0x16bc->0x16e8 --> some binding between vp/fp regs
65 * 0x16b8 --> VP output count
66 *
67 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
68 * "MOV rcol.x, fcol.y" = 0x00000004
69 * 0x19a8 --> as above but 0x00000100 and 0x00000000
70 * - 0x00100000 used when KIL used
71 * 0x196c --> as above but 0x00000011 and 0x00000000
72 *
73 * 0x1988 --> 0xXXNNNNNN
74 * - XX == FP high something
75 */
76 struct nv50_reg {
77 enum {
78 P_TEMP,
79 P_ATTR,
80 P_RESULT,
81 P_CONST,
82 P_IMMD
83 } type;
84 int index;
85
86 int hw;
87 int neg;
88
89 int rhw; /* result hw for FP outputs, or interpolant index */
90 int acc; /* instruction where this reg is last read (first insn == 1) */
91 };
92
93 /* arbitrary limits */
94 #define MAX_IF_DEPTH 4
95 #define MAX_LOOP_DEPTH 4
96
97 struct nv50_pc {
98 struct nv50_program *p;
99
100 /* hw resources */
101 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
102
103 /* tgsi resources */
104 struct nv50_reg *temp;
105 int temp_nr;
106 struct nv50_reg *attr;
107 int attr_nr;
108 struct nv50_reg *result;
109 int result_nr;
110 struct nv50_reg *param;
111 int param_nr;
112 struct nv50_reg *immd;
113 float *immd_buf;
114 int immd_nr;
115
116 struct nv50_reg *temp_temp[16];
117 unsigned temp_temp_nr;
118
119 /* broadcast and destination replacement regs */
120 struct nv50_reg *r_brdc;
121 struct nv50_reg *r_dst[4];
122
123 unsigned interp_mode[32];
124 /* perspective interpolation registers */
125 struct nv50_reg *iv_p;
126 struct nv50_reg *iv_c;
127
128 struct nv50_program_exec *if_cond;
129 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
130 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
131 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
132 int if_lvl, loop_lvl;
133 unsigned loop_pos[MAX_LOOP_DEPTH];
134
135 /* current instruction and total number of insns */
136 unsigned insn_cur;
137 unsigned insn_nr;
138
139 boolean allow32;
140 };
141
142 static INLINE void
143 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
144 {
145 reg->type = type;
146 reg->index = index;
147 reg->hw = hw;
148 reg->neg = 0;
149 reg->rhw = -1;
150 reg->acc = 0;
151 }
152
153 static INLINE unsigned
154 popcnt4(uint32_t val)
155 {
156 static const unsigned cnt[16]
157 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
158 return cnt[val & 0xf];
159 }
160
161 static void
162 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
163 {
164 int i = 0;
165
166 if (reg->type == P_RESULT) {
167 if (pc->p->cfg.high_result < (reg->hw + 1))
168 pc->p->cfg.high_result = reg->hw + 1;
169 }
170
171 if (reg->type != P_TEMP)
172 return;
173
174 if (reg->hw >= 0) {
175 /*XXX: do this here too to catch FP temp-as-attr usage..
176 * not clean, but works */
177 if (pc->p->cfg.high_temp < (reg->hw + 1))
178 pc->p->cfg.high_temp = reg->hw + 1;
179 return;
180 }
181
182 if (reg->rhw != -1) {
183 /* try to allocate temporary with index rhw first */
184 if (!(pc->r_temp[reg->rhw])) {
185 pc->r_temp[reg->rhw] = reg;
186 reg->hw = reg->rhw;
187 if (pc->p->cfg.high_temp < (reg->rhw + 1))
188 pc->p->cfg.high_temp = reg->rhw + 1;
189 return;
190 }
191 /* make sure we don't get things like $r0 needs to go
192 * in $r1 and $r1 in $r0
193 */
194 i = pc->result_nr * 4;
195 }
196
197 for (; i < NV50_SU_MAX_TEMP; i++) {
198 if (!(pc->r_temp[i])) {
199 pc->r_temp[i] = reg;
200 reg->hw = i;
201 if (pc->p->cfg.high_temp < (i + 1))
202 pc->p->cfg.high_temp = i + 1;
203 return;
204 }
205 }
206
207 assert(0);
208 }
209
210 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
211 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
212 * lest we risk temp_temps overwriting regs alloc'd "later".
213 */
214 static struct nv50_reg *
215 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
216 {
217 struct nv50_reg *r;
218 int i;
219
220 if (dst && dst->type == P_TEMP && dst->hw == -1)
221 return dst;
222
223 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
224 if (!pc->r_temp[i]) {
225 r = MALLOC_STRUCT(nv50_reg);
226 ctor_reg(r, P_TEMP, -1, i);
227 pc->r_temp[i] = r;
228 return r;
229 }
230 }
231
232 assert(0);
233 return NULL;
234 }
235
236 /* Assign the hw of the discarded temporary register src
237 * to the tgsi register dst and free src.
238 */
239 static void
240 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
241 {
242 assert(src->index == -1 && src->hw != -1);
243
244 if (dst->hw != -1)
245 pc->r_temp[dst->hw] = NULL;
246 pc->r_temp[src->hw] = dst;
247 dst->hw = src->hw;
248
249 FREE(src);
250 }
251
252 /* release the hardware resource held by r */
253 static void
254 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
255 {
256 assert(r->type == P_TEMP);
257 if (r->hw == -1)
258 return;
259
260 assert(pc->r_temp[r->hw] == r);
261 pc->r_temp[r->hw] = NULL;
262
263 r->acc = 0;
264 if (r->index == -1)
265 FREE(r);
266 }
267
268 static void
269 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
270 {
271 if (r->index == -1) {
272 unsigned hw = r->hw;
273
274 FREE(pc->r_temp[hw]);
275 pc->r_temp[hw] = NULL;
276 }
277 }
278
279 static int
280 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
281 {
282 int i;
283
284 if ((idx + 4) >= NV50_SU_MAX_TEMP)
285 return 1;
286
287 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
288 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
289 return alloc_temp4(pc, dst, idx + 4);
290
291 for (i = 0; i < 4; i++) {
292 dst[i] = MALLOC_STRUCT(nv50_reg);
293 ctor_reg(dst[i], P_TEMP, -1, idx + i);
294 pc->r_temp[idx + i] = dst[i];
295 }
296
297 return 0;
298 }
299
300 static void
301 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
302 {
303 int i;
304
305 for (i = 0; i < 4; i++)
306 free_temp(pc, reg[i]);
307 }
308
309 static struct nv50_reg *
310 temp_temp(struct nv50_pc *pc)
311 {
312 if (pc->temp_temp_nr >= 16)
313 assert(0);
314
315 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
316 return pc->temp_temp[pc->temp_temp_nr++];
317 }
318
319 static void
320 kill_temp_temp(struct nv50_pc *pc)
321 {
322 int i;
323
324 for (i = 0; i < pc->temp_temp_nr; i++)
325 free_temp(pc, pc->temp_temp[i]);
326 pc->temp_temp_nr = 0;
327 }
328
329 static int
330 ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w)
331 {
332 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)),
333 (pc->immd_nr + 1) * 4 * sizeof(float));
334 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
335 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
336 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
337 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
338
339 return pc->immd_nr++;
340 }
341
342 static struct nv50_reg *
343 alloc_immd(struct nv50_pc *pc, float f)
344 {
345 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
346 unsigned hw;
347
348 for (hw = 0; hw < pc->immd_nr * 4; hw++)
349 if (pc->immd_buf[hw] == f)
350 break;
351
352 if (hw == pc->immd_nr * 4)
353 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4;
354
355 ctor_reg(r, P_IMMD, -1, hw);
356 return r;
357 }
358
359 static struct nv50_program_exec *
360 exec(struct nv50_pc *pc)
361 {
362 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
363
364 e->param.index = -1;
365 return e;
366 }
367
368 static void
369 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
370 {
371 struct nv50_program *p = pc->p;
372
373 if (p->exec_tail)
374 p->exec_tail->next = e;
375 if (!p->exec_head)
376 p->exec_head = e;
377 p->exec_tail = e;
378 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
379 }
380
381 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
382
383 static boolean
384 is_long(struct nv50_program_exec *e)
385 {
386 if (e->inst[0] & 1)
387 return TRUE;
388 return FALSE;
389 }
390
391 static boolean
392 is_immd(struct nv50_program_exec *e)
393 {
394 if (is_long(e) && (e->inst[1] & 3) == 3)
395 return TRUE;
396 return FALSE;
397 }
398
399 static INLINE void
400 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
401 struct nv50_program_exec *e)
402 {
403 set_long(pc, e);
404 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
405 e->inst[1] |= (pred << 7) | (idx << 12);
406 }
407
408 static INLINE void
409 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
410 struct nv50_program_exec *e)
411 {
412 set_long(pc, e);
413 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
414 e->inst[1] |= (idx << 4) | (on << 6);
415 }
416
417 static INLINE void
418 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
419 {
420 if (is_long(e))
421 return;
422
423 e->inst[0] |= 1;
424 set_pred(pc, 0xf, 0, e);
425 set_pred_wr(pc, 0, 0, e);
426 }
427
428 static INLINE void
429 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
430 {
431 if (dst->type == P_RESULT) {
432 set_long(pc, e);
433 e->inst[1] |= 0x00000008;
434 }
435
436 alloc_reg(pc, dst);
437 e->inst[0] |= (dst->hw << 2);
438 }
439
440 static INLINE void
441 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
442 {
443 float f = pc->immd_buf[imm->hw];
444 unsigned val = fui(imm->neg ? -f : f);
445
446 set_long(pc, e);
447 /*XXX: can't be predicated - bits overlap.. catch cases where both
448 * are required and avoid them. */
449 set_pred(pc, 0, 0, e);
450 set_pred_wr(pc, 0, 0, e);
451
452 e->inst[1] |= 0x00000002 | 0x00000001;
453 e->inst[0] |= (val & 0x3f) << 16;
454 e->inst[1] |= (val >> 6) << 2;
455 }
456
457
458 #define INTERP_LINEAR 0
459 #define INTERP_FLAT 1
460 #define INTERP_PERSPECTIVE 2
461 #define INTERP_CENTROID 4
462
463 /* interpolant index has been stored in dst->rhw */
464 static void
465 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
466 unsigned mode)
467 {
468 assert(dst->rhw != -1);
469 struct nv50_program_exec *e = exec(pc);
470
471 e->inst[0] |= 0x80000000;
472 set_dst(pc, dst, e);
473 e->inst[0] |= (dst->rhw << 16);
474
475 if (mode & INTERP_FLAT) {
476 e->inst[0] |= (1 << 8);
477 } else {
478 if (mode & INTERP_PERSPECTIVE) {
479 e->inst[0] |= (1 << 25);
480 alloc_reg(pc, iv);
481 e->inst[0] |= (iv->hw << 9);
482 }
483
484 if (mode & INTERP_CENTROID)
485 e->inst[0] |= (1 << 24);
486 }
487
488 emit(pc, e);
489 }
490
491 static void
492 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
493 struct nv50_program_exec *e)
494 {
495 set_long(pc, e);
496
497 e->param.index = src->hw;
498 e->param.shift = s;
499 e->param.mask = m << (s % 32);
500
501 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
502 }
503
504 static void
505 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
506 {
507 struct nv50_program_exec *e = exec(pc);
508
509 e->inst[0] = 0x10000000;
510 if (!pc->allow32)
511 set_long(pc, e);
512
513 set_dst(pc, dst, e);
514
515 if (!is_long(e) && src->type == P_IMMD) {
516 set_immd(pc, src, e);
517 /*XXX: 32-bit, but steals part of "half" reg space - need to
518 * catch and handle this case if/when we do half-regs
519 */
520 } else
521 if (src->type == P_IMMD || src->type == P_CONST) {
522 set_long(pc, e);
523 set_data(pc, src, 0x7f, 9, e);
524 e->inst[1] |= 0x20000000; /* src0 const? */
525 } else {
526 if (src->type == P_ATTR) {
527 set_long(pc, e);
528 e->inst[1] |= 0x00200000;
529 }
530
531 alloc_reg(pc, src);
532 e->inst[0] |= (src->hw << 9);
533 }
534
535 if (is_long(e) && !is_immd(e)) {
536 e->inst[1] |= 0x04000000; /* 32-bit */
537 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */
538 if (!(e->inst[1] & 0x20000000))
539 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */
540 } else
541 e->inst[0] |= 0x00008000;
542
543 emit(pc, e);
544 }
545
546 static INLINE void
547 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
548 {
549 struct nv50_reg *imm = alloc_immd(pc, f);
550 emit_mov(pc, dst, imm);
551 FREE(imm);
552 }
553
554 static boolean
555 check_swap_src_0_1(struct nv50_pc *pc,
556 struct nv50_reg **s0, struct nv50_reg **s1)
557 {
558 struct nv50_reg *src0 = *s0, *src1 = *s1;
559
560 if (src0->type == P_CONST) {
561 if (src1->type != P_CONST) {
562 *s0 = src1;
563 *s1 = src0;
564 return TRUE;
565 }
566 } else
567 if (src1->type == P_ATTR) {
568 if (src0->type != P_ATTR) {
569 *s0 = src1;
570 *s1 = src0;
571 return TRUE;
572 }
573 }
574
575 return FALSE;
576 }
577
578 static void
579 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
580 struct nv50_program_exec *e)
581 {
582 struct nv50_reg *temp;
583
584 if (src->type != P_TEMP) {
585 temp = temp_temp(pc);
586 emit_mov(pc, temp, src);
587 src = temp;
588 }
589
590 alloc_reg(pc, src);
591 e->inst[0] |= (src->hw << 9);
592 }
593
594 static void
595 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
596 {
597 if (src->type == P_ATTR) {
598 set_long(pc, e);
599 e->inst[1] |= 0x00200000;
600 } else
601 if (src->type == P_CONST || src->type == P_IMMD) {
602 struct nv50_reg *temp = temp_temp(pc);
603
604 emit_mov(pc, temp, src);
605 src = temp;
606 }
607
608 alloc_reg(pc, src);
609 e->inst[0] |= (src->hw << 9);
610 }
611
612 static void
613 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
614 {
615 if (src->type == P_ATTR) {
616 struct nv50_reg *temp = temp_temp(pc);
617
618 emit_mov(pc, temp, src);
619 src = temp;
620 } else
621 if (src->type == P_CONST || src->type == P_IMMD) {
622 assert(!(e->inst[0] & 0x00800000));
623 if (e->inst[0] & 0x01000000) {
624 struct nv50_reg *temp = temp_temp(pc);
625
626 emit_mov(pc, temp, src);
627 src = temp;
628 } else {
629 set_data(pc, src, 0x7f, 16, e);
630 e->inst[0] |= 0x00800000;
631 }
632 }
633
634 alloc_reg(pc, src);
635 e->inst[0] |= (src->hw << 16);
636 }
637
638 static void
639 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
640 {
641 set_long(pc, e);
642
643 if (src->type == P_ATTR) {
644 struct nv50_reg *temp = temp_temp(pc);
645
646 emit_mov(pc, temp, src);
647 src = temp;
648 } else
649 if (src->type == P_CONST || src->type == P_IMMD) {
650 assert(!(e->inst[0] & 0x01000000));
651 if (e->inst[0] & 0x00800000) {
652 struct nv50_reg *temp = temp_temp(pc);
653
654 emit_mov(pc, temp, src);
655 src = temp;
656 } else {
657 set_data(pc, src, 0x7f, 32+14, e);
658 e->inst[0] |= 0x01000000;
659 }
660 }
661
662 alloc_reg(pc, src);
663 e->inst[1] |= (src->hw << 14);
664 }
665
666 static void
667 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
668 struct nv50_reg *src1)
669 {
670 struct nv50_program_exec *e = exec(pc);
671
672 e->inst[0] |= 0xc0000000;
673
674 if (!pc->allow32)
675 set_long(pc, e);
676
677 check_swap_src_0_1(pc, &src0, &src1);
678 set_dst(pc, dst, e);
679 set_src_0(pc, src0, e);
680 if (src1->type == P_IMMD && !is_long(e)) {
681 if (src0->neg)
682 e->inst[0] |= 0x00008000;
683 set_immd(pc, src1, e);
684 } else {
685 set_src_1(pc, src1, e);
686 if (src0->neg ^ src1->neg) {
687 if (is_long(e))
688 e->inst[1] |= 0x08000000;
689 else
690 e->inst[0] |= 0x00008000;
691 }
692 }
693
694 emit(pc, e);
695 }
696
697 static void
698 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
699 struct nv50_reg *src0, struct nv50_reg *src1)
700 {
701 struct nv50_program_exec *e = exec(pc);
702
703 e->inst[0] |= 0xb0000000;
704
705 check_swap_src_0_1(pc, &src0, &src1);
706
707 if (!pc->allow32 || src0->neg || src1->neg) {
708 set_long(pc, e);
709 e->inst[1] |= (src0->neg << 26) | (src1->neg << 27);
710 }
711
712 set_dst(pc, dst, e);
713 set_src_0(pc, src0, e);
714 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
715 set_src_2(pc, src1, e);
716 else
717 if (src1->type == P_IMMD)
718 set_immd(pc, src1, e);
719 else
720 set_src_1(pc, src1, e);
721
722 emit(pc, e);
723 }
724
725 static void
726 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
727 struct nv50_reg *src0, struct nv50_reg *src1)
728 {
729 struct nv50_program_exec *e = exec(pc);
730
731 set_long(pc, e);
732 e->inst[0] |= 0xb0000000;
733 e->inst[1] |= (sub << 29);
734
735 check_swap_src_0_1(pc, &src0, &src1);
736 set_dst(pc, dst, e);
737 set_src_0(pc, src0, e);
738 set_src_1(pc, src1, e);
739
740 emit(pc, e);
741 }
742
743 static INLINE void
744 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
745 struct nv50_reg *src1)
746 {
747 src1->neg ^= 1;
748 emit_add(pc, dst, src0, src1);
749 src1->neg ^= 1;
750 }
751
752 static void
753 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
754 struct nv50_reg *src1, struct nv50_reg *src2)
755 {
756 struct nv50_program_exec *e = exec(pc);
757
758 e->inst[0] |= 0xe0000000;
759
760 check_swap_src_0_1(pc, &src0, &src1);
761 set_dst(pc, dst, e);
762 set_src_0(pc, src0, e);
763 set_src_1(pc, src1, e);
764 set_src_2(pc, src2, e);
765
766 if (src0->neg ^ src1->neg)
767 e->inst[1] |= 0x04000000;
768 if (src2->neg)
769 e->inst[1] |= 0x08000000;
770
771 emit(pc, e);
772 }
773
774 static INLINE void
775 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
776 struct nv50_reg *src1, struct nv50_reg *src2)
777 {
778 src2->neg ^= 1;
779 emit_mad(pc, dst, src0, src1, src2);
780 src2->neg ^= 1;
781 }
782
783 static void
784 emit_flop(struct nv50_pc *pc, unsigned sub,
785 struct nv50_reg *dst, struct nv50_reg *src)
786 {
787 struct nv50_program_exec *e = exec(pc);
788
789 e->inst[0] |= 0x90000000;
790 if (sub) {
791 set_long(pc, e);
792 e->inst[1] |= (sub << 29);
793 }
794
795 set_dst(pc, dst, e);
796
797 if (sub == 0 || sub == 2)
798 set_src_0_restricted(pc, src, e);
799 else
800 set_src_0(pc, src, e);
801
802 emit(pc, e);
803 }
804
805 static void
806 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
807 {
808 struct nv50_program_exec *e = exec(pc);
809
810 e->inst[0] |= 0xb0000000;
811
812 set_dst(pc, dst, e);
813 set_src_0(pc, src, e);
814 set_long(pc, e);
815 e->inst[1] |= (6 << 29) | 0x00004000;
816
817 emit(pc, e);
818 }
819
820 static void
821 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
822 {
823 struct nv50_program_exec *e = exec(pc);
824
825 e->inst[0] |= 0xb0000000;
826
827 set_dst(pc, dst, e);
828 set_src_0(pc, src, e);
829 set_long(pc, e);
830 e->inst[1] |= (6 << 29);
831
832 emit(pc, e);
833 }
834
835 #define CVTOP_RN 0x01
836 #define CVTOP_FLOOR 0x03
837 #define CVTOP_CEIL 0x05
838 #define CVTOP_TRUNC 0x07
839 #define CVTOP_SAT 0x08
840 #define CVTOP_ABS 0x10
841
842 /* 0x04 == 32 bit dst */
843 /* 0x40 == dst is float */
844 /* 0x80 == src is float */
845 #define CVT_F32_F32 0xc4
846 #define CVT_F32_S32 0x44
847 #define CVT_F32_U32 0x64
848 #define CVT_S32_F32 0x8c
849 #define CVT_S32_S32 0x0c
850 #define CVT_NEG 0x20
851 #define CVT_RI 0x08
852
853 static void
854 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
855 int wp, unsigned cvn, unsigned fmt)
856 {
857 struct nv50_program_exec *e;
858
859 e = exec(pc);
860 set_long(pc, e);
861
862 e->inst[0] |= 0xa0000000;
863 e->inst[1] |= 0x00004000; /* 32 bit src */
864 e->inst[1] |= (cvn << 16);
865 e->inst[1] |= (fmt << 24);
866 set_src_0(pc, src, e);
867
868 if (wp >= 0)
869 set_pred_wr(pc, 1, wp, e);
870
871 if (dst)
872 set_dst(pc, dst, e);
873 else {
874 e->inst[0] |= 0x000001fc;
875 e->inst[1] |= 0x00000008;
876 }
877
878 emit(pc, e);
879 }
880
881 /* nv50 Condition codes:
882 * 0x1 = LT
883 * 0x2 = EQ
884 * 0x3 = LE
885 * 0x4 = GT
886 * 0x5 = NE
887 * 0x6 = GE
888 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
889 * 0x8 = unordered bit (allows NaN)
890 */
891 static void
892 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
893 struct nv50_reg *src0, struct nv50_reg *src1)
894 {
895 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
896
897 struct nv50_program_exec *e = exec(pc);
898 struct nv50_reg *rdst;
899
900 assert(ccode < 16);
901 if (check_swap_src_0_1(pc, &src0, &src1))
902 ccode = cc_swapped[ccode & 7] | (ccode & 8);
903
904 rdst = dst;
905 if (dst && dst->type != P_TEMP)
906 dst = alloc_temp(pc, NULL);
907
908 /* set.u32 */
909 set_long(pc, e);
910 e->inst[0] |= 0xb0000000;
911 e->inst[1] |= 0x60000000 | (ccode << 14);
912
913 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
914 * that doesn't seem to match what the hw actually does
915 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
916 */
917
918 if (wp >= 0)
919 set_pred_wr(pc, 1, wp, e);
920 if (dst)
921 set_dst(pc, dst, e);
922 else {
923 e->inst[0] |= 0x000001fc;
924 e->inst[1] |= 0x00000008;
925 }
926
927 set_src_0(pc, src0, e);
928 set_src_1(pc, src1, e);
929
930 emit(pc, e);
931 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
932
933 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
934 if (rdst)
935 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
936 if (rdst && rdst != dst)
937 free_temp(pc, dst);
938 }
939
940 static INLINE unsigned
941 map_tgsi_setop_cc(unsigned op)
942 {
943 switch (op) {
944 case TGSI_OPCODE_SLT: return 0x1;
945 case TGSI_OPCODE_SGE: return 0x6;
946 case TGSI_OPCODE_SEQ: return 0x2;
947 case TGSI_OPCODE_SGT: return 0x4;
948 case TGSI_OPCODE_SLE: return 0x3;
949 case TGSI_OPCODE_SNE: return 0xd;
950 default:
951 assert(0);
952 return 0;
953 }
954 }
955
956 static INLINE void
957 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
958 {
959 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
960 }
961
962 static void
963 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
964 struct nv50_reg *v, struct nv50_reg *e)
965 {
966 struct nv50_reg *temp = alloc_temp(pc, NULL);
967
968 emit_flop(pc, 3, temp, v);
969 emit_mul(pc, temp, temp, e);
970 emit_preex2(pc, temp, temp);
971 emit_flop(pc, 6, dst, temp);
972
973 free_temp(pc, temp);
974 }
975
976 static INLINE void
977 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
978 {
979 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
980 }
981
982 static INLINE void
983 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
984 {
985 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
986 }
987
988 static void
989 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
990 struct nv50_reg **src)
991 {
992 struct nv50_reg *one = alloc_immd(pc, 1.0);
993 struct nv50_reg *zero = alloc_immd(pc, 0.0);
994 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
995 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
996 struct nv50_reg *tmp[4];
997 boolean allow32 = pc->allow32;
998
999 pc->allow32 = FALSE;
1000
1001 if (mask & (3 << 1)) {
1002 tmp[0] = alloc_temp(pc, NULL);
1003 emit_minmax(pc, 4, tmp[0], src[0], zero);
1004 }
1005
1006 if (mask & (1 << 2)) {
1007 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1008
1009 tmp[1] = temp_temp(pc);
1010 emit_minmax(pc, 4, tmp[1], src[1], zero);
1011
1012 tmp[3] = temp_temp(pc);
1013 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1014 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1015
1016 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1017 emit_mov(pc, dst[2], zero);
1018 set_pred(pc, 3, 0, pc->p->exec_tail);
1019 }
1020
1021 if (mask & (1 << 1))
1022 assimilate_temp(pc, dst[1], tmp[0]);
1023 else
1024 if (mask & (1 << 2))
1025 free_temp(pc, tmp[0]);
1026
1027 pc->allow32 = allow32;
1028
1029 /* do this last, in case src[i,j] == dst[0,3] */
1030 if (mask & (1 << 0))
1031 emit_mov(pc, dst[0], one);
1032
1033 if (mask & (1 << 3))
1034 emit_mov(pc, dst[3], one);
1035
1036 FREE(pos128);
1037 FREE(neg128);
1038 FREE(zero);
1039 FREE(one);
1040 }
1041
1042 static INLINE void
1043 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1044 {
1045 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1046 }
1047
1048 static void
1049 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1050 {
1051 struct nv50_program_exec *e;
1052 const int r_pred = 1;
1053 unsigned cvn = CVT_F32_F32;
1054
1055 if (src->neg)
1056 cvn |= CVT_NEG;
1057 /* write predicate reg */
1058 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1059
1060 /* conditional discard */
1061 e = exec(pc);
1062 e->inst[0] = 0x00000002;
1063 set_long(pc, e);
1064 set_pred(pc, 0x1 /* LT */, r_pred, e);
1065 emit(pc, e);
1066 }
1067
1068 static void
1069 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1070 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj)
1071 {
1072 struct nv50_reg *temp, *t[4];
1073 struct nv50_program_exec *e;
1074
1075 unsigned c, mode, dim;
1076
1077 switch (type) {
1078 case TGSI_TEXTURE_1D:
1079 dim = 1;
1080 break;
1081 case TGSI_TEXTURE_UNKNOWN:
1082 case TGSI_TEXTURE_2D:
1083 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */
1084 case TGSI_TEXTURE_RECT:
1085 dim = 2;
1086 break;
1087 case TGSI_TEXTURE_3D:
1088 case TGSI_TEXTURE_CUBE:
1089 case TGSI_TEXTURE_SHADOW2D:
1090 case TGSI_TEXTURE_SHADOWRECT: /* XXX */
1091 dim = 3;
1092 break;
1093 default:
1094 assert(0);
1095 break;
1096 }
1097
1098 /* some cards need t[0]'s hw index to be a multiple of 4 */
1099 alloc_temp4(pc, t, 0);
1100
1101 if (proj) {
1102 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1103 mode = pc->interp_mode[src[0]->index];
1104
1105 t[3]->rhw = src[3]->rhw;
1106 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1107 emit_flop(pc, 0, t[3], t[3]);
1108
1109 for (c = 0; c < dim; c++) {
1110 t[c]->rhw = src[c]->rhw;
1111 emit_interp(pc, t[c], t[3],
1112 (mode | INTERP_PERSPECTIVE));
1113 }
1114 } else {
1115 emit_flop(pc, 0, t[3], src[3]);
1116 for (c = 0; c < dim; c++)
1117 emit_mul(pc, t[c], src[c], t[3]);
1118
1119 /* XXX: for some reason the blob sometimes uses MAD:
1120 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1121 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1122 */
1123 }
1124 } else {
1125 if (type == TGSI_TEXTURE_CUBE) {
1126 temp = temp_temp(pc);
1127 emit_minmax(pc, 4, temp, src[0], src[1]);
1128 emit_minmax(pc, 4, temp, temp, src[2]);
1129 emit_flop(pc, 0, temp, temp);
1130 for (c = 0; c < 3; c++)
1131 emit_mul(pc, t[c], src[c], temp);
1132 } else {
1133 for (c = 0; c < dim; c++)
1134 emit_mov(pc, t[c], src[c]);
1135 }
1136 }
1137
1138 e = exec(pc);
1139 set_long(pc, e);
1140 e->inst[0] |= 0xf0000000;
1141 e->inst[1] |= 0x00000004;
1142 set_dst(pc, t[0], e);
1143 e->inst[0] |= (unit << 9);
1144
1145 if (dim == 2)
1146 e->inst[0] |= 0x00400000;
1147 else
1148 if (dim == 3)
1149 e->inst[0] |= 0x00800000;
1150
1151 e->inst[0] |= (mask & 0x3) << 25;
1152 e->inst[1] |= (mask & 0xc) << 12;
1153
1154 emit(pc, e);
1155
1156 #if 1
1157 c = 0;
1158 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1159 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1160 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1161 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1162
1163 free_temp4(pc, t);
1164 #else
1165 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1166 * the texture coordinates, not the fetched values: latency ? */
1167
1168 for (c = 0; c < 4; c++) {
1169 if (mask & (1 << c))
1170 assimilate_temp(pc, dst[c], t[c]);
1171 else
1172 free_temp(pc, t[c]);
1173 }
1174 #endif
1175 }
1176
1177 static void
1178 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1179 struct nv50_program_exec **join)
1180 {
1181 struct nv50_program_exec *e = exec(pc);
1182
1183 if (join) {
1184 set_long(pc, e);
1185 e->inst[0] |= 0xa0000002;
1186 emit(pc, e);
1187 *join = e;
1188 e = exec(pc);
1189 }
1190
1191 set_long(pc, e);
1192 e->inst[0] |= 0x10000002;
1193 if (pred >= 0)
1194 set_pred(pc, cc, pred, e);
1195 emit(pc, e);
1196 }
1197
1198 static void
1199 emit_nop(struct nv50_pc *pc)
1200 {
1201 struct nv50_program_exec *e = exec(pc);
1202
1203 e->inst[0] = 0xf0000000;
1204 set_long(pc, e);
1205 e->inst[1] = 0xe0000000;
1206 emit(pc, e);
1207 }
1208
1209 static void
1210 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1211 {
1212 struct nv50_program_exec *e = exec(pc);
1213
1214 assert(src->type == P_TEMP);
1215
1216 e->inst[0] = 0xc0140000;
1217 e->inst[1] = 0x89800000;
1218 set_long(pc, e);
1219 set_dst(pc, dst, e);
1220 set_src_0(pc, src, e);
1221 set_src_2(pc, src, e);
1222
1223 emit(pc, e);
1224 }
1225
1226 static void
1227 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1228 {
1229 struct nv50_program_exec *e = exec(pc);
1230
1231 assert(src->type == P_TEMP);
1232
1233 if (!src->neg) /* ! double negation */
1234 emit_neg(pc, src, src);
1235
1236 e->inst[0] = 0xc0150000;
1237 e->inst[1] = 0x8a400000;
1238 set_long(pc, e);
1239 set_dst(pc, dst, e);
1240 set_src_0(pc, src, e);
1241 set_src_2(pc, src, e);
1242
1243 emit(pc, e);
1244 }
1245
1246 static void
1247 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1248 {
1249 unsigned q = 0, m = ~0;
1250
1251 assert(!is_long(e));
1252
1253 switch (e->inst[0] >> 28) {
1254 case 0x1:
1255 /* MOV */
1256 q = 0x0403c000;
1257 m = 0xffff7fff;
1258 break;
1259 case 0x8:
1260 /* INTERP (move centroid, perspective and flat bits) */
1261 m = ~0x03000100;
1262 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1263 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1264 break;
1265 case 0x9:
1266 /* RCP */
1267 break;
1268 case 0xB:
1269 /* ADD */
1270 m = ~(127 << 16);
1271 q = ((e->inst[0] & (~m)) >> 2);
1272 break;
1273 case 0xC:
1274 /* MUL */
1275 m = ~0x00008000;
1276 q = ((e->inst[0] & (~m)) << 12);
1277 break;
1278 case 0xE:
1279 /* MAD (if src2 == dst) */
1280 q = ((e->inst[0] & 0x1fc) << 12);
1281 break;
1282 default:
1283 assert(0);
1284 break;
1285 }
1286
1287 set_long(pc, e);
1288 pc->p->exec_size++;
1289
1290 e->inst[0] &= m;
1291 e->inst[1] |= q;
1292 }
1293
1294 /* Some operations support an optional negation flag. */
1295 static boolean
1296 negate_supported(const struct tgsi_full_instruction *insn, int i)
1297 {
1298 int s;
1299
1300 switch (insn->Instruction.Opcode) {
1301 case TGSI_OPCODE_DDY:
1302 case TGSI_OPCODE_DP3:
1303 case TGSI_OPCODE_DP4:
1304 case TGSI_OPCODE_MUL:
1305 case TGSI_OPCODE_KIL:
1306 case TGSI_OPCODE_ADD:
1307 case TGSI_OPCODE_SUB:
1308 case TGSI_OPCODE_MAD:
1309 break;
1310 case TGSI_OPCODE_POW:
1311 if (i == 1)
1312 break;
1313 return FALSE;
1314 default:
1315 return FALSE;
1316 }
1317
1318 /* Watch out for possible multiple uses of an nv50_reg, we
1319 * can't use nv50_reg::neg in these cases.
1320 */
1321 for (s = 0; s < insn->Instruction.NumSrcRegs; ++s) {
1322 if (s == i)
1323 continue;
1324 if ((insn->FullSrcRegisters[s].SrcRegister.Index ==
1325 insn->FullSrcRegisters[i].SrcRegister.Index) &&
1326 (insn->FullSrcRegisters[s].SrcRegister.File ==
1327 insn->FullSrcRegisters[i].SrcRegister.File))
1328 return FALSE;
1329 }
1330
1331 return TRUE;
1332 }
1333
1334 /* Return a read mask for source registers deduced from opcode & write mask. */
1335 static unsigned
1336 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1337 {
1338 unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask;
1339
1340 switch (insn->Instruction.Opcode) {
1341 case TGSI_OPCODE_COS:
1342 case TGSI_OPCODE_SIN:
1343 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1344 case TGSI_OPCODE_DP3:
1345 return 0x7;
1346 case TGSI_OPCODE_DP4:
1347 case TGSI_OPCODE_DPH:
1348 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1349 return 0xf;
1350 case TGSI_OPCODE_DST:
1351 return mask & (c ? 0xa : 0x6);
1352 case TGSI_OPCODE_EX2:
1353 case TGSI_OPCODE_LG2:
1354 case TGSI_OPCODE_POW:
1355 case TGSI_OPCODE_RCP:
1356 case TGSI_OPCODE_RSQ:
1357 case TGSI_OPCODE_SCS:
1358 return 0x1;
1359 case TGSI_OPCODE_LIT:
1360 return 0xb;
1361 case TGSI_OPCODE_TEX:
1362 case TGSI_OPCODE_TXP:
1363 {
1364 const struct tgsi_instruction_ext_texture *tex;
1365
1366 assert(insn->Instruction.Extended);
1367 tex = &insn->InstructionExtTexture;
1368
1369 mask = 0x7;
1370 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
1371 mask |= 0x8;
1372
1373 switch (tex->Texture) {
1374 case TGSI_TEXTURE_1D:
1375 mask &= 0x9;
1376 break;
1377 case TGSI_TEXTURE_2D:
1378 mask &= 0xb;
1379 break;
1380 default:
1381 break;
1382 }
1383 }
1384 return mask;
1385 case TGSI_OPCODE_XPD:
1386 x = 0;
1387 if (mask & 1) x |= 0x6;
1388 if (mask & 2) x |= 0x5;
1389 if (mask & 4) x |= 0x3;
1390 return x;
1391 default:
1392 break;
1393 }
1394
1395 return mask;
1396 }
1397
1398 static struct nv50_reg *
1399 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1400 {
1401 switch (dst->DstRegister.File) {
1402 case TGSI_FILE_TEMPORARY:
1403 return &pc->temp[dst->DstRegister.Index * 4 + c];
1404 case TGSI_FILE_OUTPUT:
1405 return &pc->result[dst->DstRegister.Index * 4 + c];
1406 case TGSI_FILE_NULL:
1407 return NULL;
1408 default:
1409 break;
1410 }
1411
1412 return NULL;
1413 }
1414
1415 static struct nv50_reg *
1416 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1417 boolean neg)
1418 {
1419 struct nv50_reg *r = NULL;
1420 struct nv50_reg *temp;
1421 unsigned sgn, c;
1422
1423 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1424
1425 c = tgsi_util_get_full_src_register_extswizzle(src, chan);
1426 switch (c) {
1427 case TGSI_EXTSWIZZLE_X:
1428 case TGSI_EXTSWIZZLE_Y:
1429 case TGSI_EXTSWIZZLE_Z:
1430 case TGSI_EXTSWIZZLE_W:
1431 switch (src->SrcRegister.File) {
1432 case TGSI_FILE_INPUT:
1433 r = &pc->attr[src->SrcRegister.Index * 4 + c];
1434 break;
1435 case TGSI_FILE_TEMPORARY:
1436 r = &pc->temp[src->SrcRegister.Index * 4 + c];
1437 break;
1438 case TGSI_FILE_CONSTANT:
1439 r = &pc->param[src->SrcRegister.Index * 4 + c];
1440 break;
1441 case TGSI_FILE_IMMEDIATE:
1442 r = &pc->immd[src->SrcRegister.Index * 4 + c];
1443 break;
1444 case TGSI_FILE_SAMPLER:
1445 break;
1446 default:
1447 assert(0);
1448 break;
1449 }
1450 break;
1451 case TGSI_EXTSWIZZLE_ZERO:
1452 r = alloc_immd(pc, 0.0);
1453 return r;
1454 case TGSI_EXTSWIZZLE_ONE:
1455 if (sgn == TGSI_UTIL_SIGN_TOGGLE || sgn == TGSI_UTIL_SIGN_SET)
1456 return alloc_immd(pc, -1.0);
1457 return alloc_immd(pc, 1.0);
1458 default:
1459 assert(0);
1460 break;
1461 }
1462
1463 switch (sgn) {
1464 case TGSI_UTIL_SIGN_KEEP:
1465 break;
1466 case TGSI_UTIL_SIGN_CLEAR:
1467 temp = temp_temp(pc);
1468 emit_abs(pc, temp, r);
1469 r = temp;
1470 break;
1471 case TGSI_UTIL_SIGN_TOGGLE:
1472 if (neg)
1473 r->neg = 1;
1474 else {
1475 temp = temp_temp(pc);
1476 emit_neg(pc, temp, r);
1477 r = temp;
1478 }
1479 break;
1480 case TGSI_UTIL_SIGN_SET:
1481 temp = temp_temp(pc);
1482 emit_abs(pc, temp, r);
1483 if (neg)
1484 temp->neg = 1;
1485 else
1486 emit_neg(pc, temp, temp);
1487 r = temp;
1488 break;
1489 default:
1490 assert(0);
1491 break;
1492 }
1493
1494 return r;
1495 }
1496
1497 /* return TRUE for ops that produce only a single result */
1498 static boolean
1499 is_scalar_op(unsigned op)
1500 {
1501 switch (op) {
1502 case TGSI_OPCODE_COS:
1503 case TGSI_OPCODE_DP2:
1504 case TGSI_OPCODE_DP3:
1505 case TGSI_OPCODE_DP4:
1506 case TGSI_OPCODE_DPH:
1507 case TGSI_OPCODE_EX2:
1508 case TGSI_OPCODE_LG2:
1509 case TGSI_OPCODE_POW:
1510 case TGSI_OPCODE_RCP:
1511 case TGSI_OPCODE_RSQ:
1512 case TGSI_OPCODE_SIN:
1513 /*
1514 case TGSI_OPCODE_KIL:
1515 case TGSI_OPCODE_LIT:
1516 case TGSI_OPCODE_SCS:
1517 */
1518 return TRUE;
1519 default:
1520 return FALSE;
1521 }
1522 }
1523
1524 /* Returns a bitmask indicating which dst components depend
1525 * on source s, component c (reverse of nv50_tgsi_src_mask).
1526 */
1527 static unsigned
1528 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1529 {
1530 if (is_scalar_op(op))
1531 return 0x1;
1532
1533 switch (op) {
1534 case TGSI_OPCODE_DST:
1535 return (1 << c) & (s ? 0xa : 0x6);
1536 case TGSI_OPCODE_XPD:
1537 switch (c) {
1538 case 0: return 0x6;
1539 case 1: return 0x5;
1540 case 2: return 0x3;
1541 case 3: return 0x0;
1542 default:
1543 assert(0);
1544 return 0x0;
1545 }
1546 case TGSI_OPCODE_LIT:
1547 case TGSI_OPCODE_SCS:
1548 case TGSI_OPCODE_TEX:
1549 case TGSI_OPCODE_TXP:
1550 /* these take care of dangerous swizzles themselves */
1551 return 0x0;
1552 case TGSI_OPCODE_IF:
1553 case TGSI_OPCODE_KIL:
1554 /* don't call this function for these ops */
1555 assert(0);
1556 return 0;
1557 default:
1558 /* linear vector instruction */
1559 return (1 << c);
1560 }
1561 }
1562
1563 static INLINE boolean
1564 has_pred(struct nv50_program_exec *e, unsigned cc)
1565 {
1566 if (!is_long(e) || is_immd(e))
1567 return FALSE;
1568 return ((e->inst[1] & 0x780) == (cc << 7));
1569 }
1570
1571 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1572 * join_at ENDIF
1573 * @p0.eq bra ENDIF
1574 * single_op
1575 * ENDIF: nop.join
1576 */
1577 static boolean
1578 nv50_kill_branch(struct nv50_pc *pc)
1579 {
1580 int lvl = pc->if_lvl;
1581
1582 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
1583 return FALSE;
1584
1585 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1586 * reg may no longer be valid, since we currently always use $p0
1587 */
1588 if (has_pred(pc->if_insn[lvl], 0xf))
1589 return FALSE;
1590 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
1591
1592 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1593 * update prev's next); if exec_tail is BRK, update the pointer.
1594 */
1595 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
1596 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
1597
1598 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
1599
1600 *pc->br_join[lvl] = *pc->p->exec_tail;
1601
1602 FREE(pc->if_insn[lvl]);
1603 FREE(pc->p->exec_tail);
1604
1605 pc->p->exec_tail = pc->br_join[lvl];
1606 pc->p->exec_tail->next = NULL;
1607 set_pred(pc, 0xd, 0, pc->p->exec_tail);
1608
1609 return TRUE;
1610 }
1611
1612 static boolean
1613 nv50_program_tx_insn(struct nv50_pc *pc,
1614 const struct tgsi_full_instruction *inst)
1615 {
1616 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
1617 unsigned mask, sat, unit;
1618 int i, c;
1619
1620 mask = inst->FullDstRegisters[0].DstRegister.WriteMask;
1621 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
1622
1623 memset(src, 0, sizeof(src));
1624
1625 for (c = 0; c < 4; c++) {
1626 if ((mask & (1 << c)) && !pc->r_dst[c])
1627 dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]);
1628 else
1629 dst[c] = pc->r_dst[c];
1630 rdst[c] = dst[c];
1631 }
1632
1633 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1634 const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i];
1635 unsigned src_mask;
1636 boolean neg_supp;
1637
1638 src_mask = nv50_tgsi_src_mask(inst, i);
1639 neg_supp = negate_supported(inst, i);
1640
1641 if (fs->SrcRegister.File == TGSI_FILE_SAMPLER)
1642 unit = fs->SrcRegister.Index;
1643
1644 for (c = 0; c < 4; c++)
1645 if (src_mask & (1 << c))
1646 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
1647 }
1648
1649 brdc = temp = pc->r_brdc;
1650 if (brdc && brdc->type != P_TEMP) {
1651 temp = temp_temp(pc);
1652 if (sat)
1653 brdc = temp;
1654 } else
1655 if (sat) {
1656 for (c = 0; c < 4; c++) {
1657 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
1658 continue;
1659 rdst[c] = dst[c];
1660 dst[c] = temp_temp(pc);
1661 }
1662 }
1663
1664 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
1665
1666 switch (inst->Instruction.Opcode) {
1667 case TGSI_OPCODE_ABS:
1668 for (c = 0; c < 4; c++) {
1669 if (!(mask & (1 << c)))
1670 continue;
1671 emit_abs(pc, dst[c], src[0][c]);
1672 }
1673 break;
1674 case TGSI_OPCODE_ADD:
1675 for (c = 0; c < 4; c++) {
1676 if (!(mask & (1 << c)))
1677 continue;
1678 emit_add(pc, dst[c], src[0][c], src[1][c]);
1679 }
1680 break;
1681 case TGSI_OPCODE_BGNLOOP:
1682 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
1683 break;
1684 case TGSI_OPCODE_BRK:
1685 emit_branch(pc, -1, 0, NULL);
1686 assert(pc->loop_lvl > 0);
1687 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
1688 break;
1689 case TGSI_OPCODE_CEIL:
1690 for (c = 0; c < 4; c++) {
1691 if (!(mask & (1 << c)))
1692 continue;
1693 emit_cvt(pc, dst[c], src[0][c], -1,
1694 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
1695 }
1696 break;
1697 case TGSI_OPCODE_CMP:
1698 pc->allow32 = FALSE;
1699 for (c = 0; c < 4; c++) {
1700 if (!(mask & (1 << c)))
1701 continue;
1702 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
1703 emit_mov(pc, dst[c], src[1][c]);
1704 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
1705 emit_mov(pc, dst[c], src[2][c]);
1706 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
1707 }
1708 break;
1709 case TGSI_OPCODE_COS:
1710 if (mask & 8) {
1711 emit_precossin(pc, temp, src[0][3]);
1712 emit_flop(pc, 5, dst[3], temp);
1713 if (!(mask &= 7))
1714 break;
1715 if (temp == dst[3])
1716 temp = brdc = temp_temp(pc);
1717 }
1718 emit_precossin(pc, temp, src[0][0]);
1719 emit_flop(pc, 5, brdc, temp);
1720 break;
1721 case TGSI_OPCODE_DDX:
1722 for (c = 0; c < 4; c++) {
1723 if (!(mask & (1 << c)))
1724 continue;
1725 emit_ddx(pc, dst[c], src[0][c]);
1726 }
1727 break;
1728 case TGSI_OPCODE_DDY:
1729 for (c = 0; c < 4; c++) {
1730 if (!(mask & (1 << c)))
1731 continue;
1732 emit_ddy(pc, dst[c], src[0][c]);
1733 }
1734 break;
1735 case TGSI_OPCODE_DP3:
1736 emit_mul(pc, temp, src[0][0], src[1][0]);
1737 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1738 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
1739 break;
1740 case TGSI_OPCODE_DP4:
1741 emit_mul(pc, temp, src[0][0], src[1][0]);
1742 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1743 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1744 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
1745 break;
1746 case TGSI_OPCODE_DPH:
1747 emit_mul(pc, temp, src[0][0], src[1][0]);
1748 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1749 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1750 emit_add(pc, brdc, src[1][3], temp);
1751 break;
1752 case TGSI_OPCODE_DST:
1753 if (mask & (1 << 1))
1754 emit_mul(pc, dst[1], src[0][1], src[1][1]);
1755 if (mask & (1 << 2))
1756 emit_mov(pc, dst[2], src[0][2]);
1757 if (mask & (1 << 3))
1758 emit_mov(pc, dst[3], src[1][3]);
1759 if (mask & (1 << 0))
1760 emit_mov_immdval(pc, dst[0], 1.0f);
1761 break;
1762 case TGSI_OPCODE_ELSE:
1763 emit_branch(pc, -1, 0, NULL);
1764 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1765 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
1766 break;
1767 case TGSI_OPCODE_ENDIF:
1768 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1769
1770 /* try to replace branch over 1 insn with a predicated insn */
1771 if (nv50_kill_branch(pc) == TRUE)
1772 break;
1773
1774 if (pc->br_join[pc->if_lvl]) {
1775 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
1776 pc->br_join[pc->if_lvl] = NULL;
1777 }
1778 /* emit a NOP as join point, we could set it on the next
1779 * one, but would have to make sure it is long and !immd
1780 */
1781 emit_nop(pc);
1782 pc->p->exec_tail->inst[1] |= 2;
1783 break;
1784 case TGSI_OPCODE_ENDLOOP:
1785 emit_branch(pc, -1, 0, NULL);
1786 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
1787 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
1788 break;
1789 case TGSI_OPCODE_EX2:
1790 emit_preex2(pc, temp, src[0][0]);
1791 emit_flop(pc, 6, brdc, temp);
1792 break;
1793 case TGSI_OPCODE_FLR:
1794 for (c = 0; c < 4; c++) {
1795 if (!(mask & (1 << c)))
1796 continue;
1797 emit_flr(pc, dst[c], src[0][c]);
1798 }
1799 break;
1800 case TGSI_OPCODE_FRC:
1801 temp = temp_temp(pc);
1802 for (c = 0; c < 4; c++) {
1803 if (!(mask & (1 << c)))
1804 continue;
1805 emit_flr(pc, temp, src[0][c]);
1806 emit_sub(pc, dst[c], src[0][c], temp);
1807 }
1808 break;
1809 case TGSI_OPCODE_IF:
1810 /* emitting a join_at may not be necessary */
1811 assert(pc->if_lvl < MAX_IF_DEPTH);
1812 set_pred_wr(pc, 1, 0, pc->if_cond);
1813 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
1814 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
1815 break;
1816 case TGSI_OPCODE_KIL:
1817 emit_kil(pc, src[0][0]);
1818 emit_kil(pc, src[0][1]);
1819 emit_kil(pc, src[0][2]);
1820 emit_kil(pc, src[0][3]);
1821 break;
1822 case TGSI_OPCODE_LIT:
1823 emit_lit(pc, &dst[0], mask, &src[0][0]);
1824 break;
1825 case TGSI_OPCODE_LG2:
1826 emit_flop(pc, 3, brdc, src[0][0]);
1827 break;
1828 case TGSI_OPCODE_LRP:
1829 temp = temp_temp(pc);
1830 for (c = 0; c < 4; c++) {
1831 if (!(mask & (1 << c)))
1832 continue;
1833 emit_sub(pc, temp, src[1][c], src[2][c]);
1834 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
1835 }
1836 break;
1837 case TGSI_OPCODE_MAD:
1838 for (c = 0; c < 4; c++) {
1839 if (!(mask & (1 << c)))
1840 continue;
1841 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
1842 }
1843 break;
1844 case TGSI_OPCODE_MAX:
1845 for (c = 0; c < 4; c++) {
1846 if (!(mask & (1 << c)))
1847 continue;
1848 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
1849 }
1850 break;
1851 case TGSI_OPCODE_MIN:
1852 for (c = 0; c < 4; c++) {
1853 if (!(mask & (1 << c)))
1854 continue;
1855 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
1856 }
1857 break;
1858 case TGSI_OPCODE_MOV:
1859 case TGSI_OPCODE_SWZ:
1860 for (c = 0; c < 4; c++) {
1861 if (!(mask & (1 << c)))
1862 continue;
1863 emit_mov(pc, dst[c], src[0][c]);
1864 }
1865 break;
1866 case TGSI_OPCODE_MUL:
1867 for (c = 0; c < 4; c++) {
1868 if (!(mask & (1 << c)))
1869 continue;
1870 emit_mul(pc, dst[c], src[0][c], src[1][c]);
1871 }
1872 break;
1873 case TGSI_OPCODE_POW:
1874 emit_pow(pc, brdc, src[0][0], src[1][0]);
1875 break;
1876 case TGSI_OPCODE_RCP:
1877 emit_flop(pc, 0, brdc, src[0][0]);
1878 break;
1879 case TGSI_OPCODE_RSQ:
1880 emit_flop(pc, 2, brdc, src[0][0]);
1881 break;
1882 case TGSI_OPCODE_SCS:
1883 temp = temp_temp(pc);
1884 if (mask & 3)
1885 emit_precossin(pc, temp, src[0][0]);
1886 if (mask & (1 << 0))
1887 emit_flop(pc, 5, dst[0], temp);
1888 if (mask & (1 << 1))
1889 emit_flop(pc, 4, dst[1], temp);
1890 if (mask & (1 << 2))
1891 emit_mov_immdval(pc, dst[2], 0.0);
1892 if (mask & (1 << 3))
1893 emit_mov_immdval(pc, dst[3], 1.0);
1894 break;
1895 case TGSI_OPCODE_SIN:
1896 if (mask & 8) {
1897 emit_precossin(pc, temp, src[0][3]);
1898 emit_flop(pc, 4, dst[3], temp);
1899 if (!(mask &= 7))
1900 break;
1901 if (temp == dst[3])
1902 temp = brdc = temp_temp(pc);
1903 }
1904 emit_precossin(pc, temp, src[0][0]);
1905 emit_flop(pc, 4, brdc, temp);
1906 break;
1907 case TGSI_OPCODE_SLT:
1908 case TGSI_OPCODE_SGE:
1909 case TGSI_OPCODE_SEQ:
1910 case TGSI_OPCODE_SGT:
1911 case TGSI_OPCODE_SLE:
1912 case TGSI_OPCODE_SNE:
1913 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
1914 for (c = 0; c < 4; c++) {
1915 if (!(mask & (1 << c)))
1916 continue;
1917 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
1918 }
1919 break;
1920 case TGSI_OPCODE_SUB:
1921 for (c = 0; c < 4; c++) {
1922 if (!(mask & (1 << c)))
1923 continue;
1924 emit_sub(pc, dst[c], src[0][c], src[1][c]);
1925 }
1926 break;
1927 case TGSI_OPCODE_TEX:
1928 emit_tex(pc, dst, mask, src[0], unit,
1929 inst->InstructionExtTexture.Texture, FALSE);
1930 break;
1931 case TGSI_OPCODE_TXP:
1932 emit_tex(pc, dst, mask, src[0], unit,
1933 inst->InstructionExtTexture.Texture, TRUE);
1934 break;
1935 case TGSI_OPCODE_TRUNC:
1936 for (c = 0; c < 4; c++) {
1937 if (!(mask & (1 << c)))
1938 continue;
1939 emit_cvt(pc, dst[c], src[0][c], -1,
1940 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
1941 }
1942 break;
1943 case TGSI_OPCODE_XPD:
1944 temp = temp_temp(pc);
1945 if (mask & (1 << 0)) {
1946 emit_mul(pc, temp, src[0][2], src[1][1]);
1947 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
1948 }
1949 if (mask & (1 << 1)) {
1950 emit_mul(pc, temp, src[0][0], src[1][2]);
1951 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
1952 }
1953 if (mask & (1 << 2)) {
1954 emit_mul(pc, temp, src[0][1], src[1][0]);
1955 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
1956 }
1957 if (mask & (1 << 3))
1958 emit_mov_immdval(pc, dst[3], 1.0);
1959 break;
1960 case TGSI_OPCODE_END:
1961 break;
1962 default:
1963 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
1964 return FALSE;
1965 }
1966
1967 if (brdc) {
1968 if (sat)
1969 emit_sat(pc, brdc, brdc);
1970 for (c = 0; c < 4; c++)
1971 if ((mask & (1 << c)) && dst[c] != brdc)
1972 emit_mov(pc, dst[c], brdc);
1973 } else
1974 if (sat) {
1975 for (c = 0; c < 4; c++) {
1976 if (!(mask & (1 << c)))
1977 continue;
1978 /* in this case we saturate later */
1979 if (dst[c]->type == P_TEMP && dst[c]->index < 0)
1980 continue;
1981 emit_sat(pc, rdst[c], dst[c]);
1982 }
1983 }
1984
1985 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1986 for (c = 0; c < 4; c++) {
1987 if (!src[i][c])
1988 continue;
1989 src[i][c]->neg = 0;
1990 if (src[i][c]->index == -1 && src[i][c]->type == P_IMMD)
1991 FREE(src[i][c]);
1992 }
1993 }
1994
1995 kill_temp_temp(pc);
1996 return TRUE;
1997 }
1998
1999 static void
2000 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2001 {
2002 struct nv50_reg *reg = NULL;
2003 const struct tgsi_full_src_register *src;
2004 const struct tgsi_dst_register *dst;
2005 unsigned i, c, k, mask;
2006
2007 dst = &insn->FullDstRegisters[0].DstRegister;
2008 mask = dst->WriteMask;
2009
2010 if (dst->File == TGSI_FILE_TEMPORARY)
2011 reg = pc->temp;
2012 else
2013 if (dst->File == TGSI_FILE_OUTPUT)
2014 reg = pc->result;
2015
2016 if (reg) {
2017 for (c = 0; c < 4; c++) {
2018 if (!(mask & (1 << c)))
2019 continue;
2020 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2021 }
2022 }
2023
2024 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2025 src = &insn->FullSrcRegisters[i];
2026
2027 if (src->SrcRegister.File == TGSI_FILE_TEMPORARY)
2028 reg = pc->temp;
2029 else
2030 if (src->SrcRegister.File == TGSI_FILE_INPUT)
2031 reg = pc->attr;
2032 else
2033 continue;
2034
2035 mask = nv50_tgsi_src_mask(insn, i);
2036
2037 for (c = 0; c < 4; c++) {
2038 if (!(mask & (1 << c)))
2039 continue;
2040 k = tgsi_util_get_full_src_register_extswizzle(src, c);
2041
2042 if (k > TGSI_EXTSWIZZLE_W)
2043 continue;
2044
2045 reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr;
2046 }
2047 }
2048 }
2049
2050 /* Returns a bitmask indicating which dst components need to be
2051 * written to temporaries first to avoid 'corrupting' sources.
2052 *
2053 * m[i] (out) indicate component to write in the i-th position
2054 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2055 */
2056 static unsigned
2057 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2058 {
2059 unsigned i, c, x, unsafe;
2060
2061 for (c = 0; c < 4; c++)
2062 m[c] = c;
2063
2064 /* Swap as long as a dst component written earlier is depended on
2065 * by one written later, but the next one isn't depended on by it.
2066 */
2067 for (c = 0; c < 3; c++) {
2068 if (rdep[m[c + 1]] & (1 << m[c]))
2069 continue; /* if next one is depended on by us */
2070 for (i = c + 1; i < 4; i++)
2071 /* if we are depended on by a later one */
2072 if (rdep[m[c]] & (1 << m[i]))
2073 break;
2074 if (i == 4)
2075 continue;
2076 /* now, swap */
2077 x = m[c];
2078 m[c] = m[c + 1];
2079 m[c + 1] = x;
2080
2081 /* restart */
2082 c = 0;
2083 }
2084
2085 /* mark dependencies that could not be resolved by reordering */
2086 for (i = 0; i < 3; ++i)
2087 for (c = i + 1; c < 4; ++c)
2088 if (rdep[m[i]] & (1 << m[c]))
2089 unsafe |= (1 << i);
2090
2091 /* NOTE: $unsafe is with respect to order, not component */
2092 return unsafe;
2093 }
2094
2095 /* Select a suitable dst register for broadcasting scalar results,
2096 * or return NULL if we have to allocate an extra TEMP.
2097 *
2098 * If e.g. only 1 component is written, we may also emit the final
2099 * result to a write-only register.
2100 */
2101 static struct nv50_reg *
2102 tgsi_broadcast_dst(struct nv50_pc *pc,
2103 const struct tgsi_full_dst_register *fd, unsigned mask)
2104 {
2105 if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
2106 int c = ffs(~mask & fd->DstRegister.WriteMask);
2107 if (c)
2108 return tgsi_dst(pc, c - 1, fd);
2109 } else {
2110 int c = ffs(fd->DstRegister.WriteMask) - 1;
2111 if ((1 << c) == fd->DstRegister.WriteMask)
2112 return tgsi_dst(pc, c, fd);
2113 }
2114
2115 return NULL;
2116 }
2117
2118 /* Scan source swizzles and return a bitmask indicating dst regs that
2119 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2120 */
2121 static unsigned
2122 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2123 unsigned rdep[4])
2124 {
2125 const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0];
2126 const struct tgsi_full_src_register *fs;
2127 unsigned i, deqs = 0;
2128
2129 for (i = 0; i < 4; ++i)
2130 rdep[i] = 0;
2131
2132 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2133 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2134 boolean neg_supp = negate_supported(insn, i);
2135
2136 fs = &insn->FullSrcRegisters[i];
2137 if (fs->SrcRegister.File != fd->DstRegister.File ||
2138 fs->SrcRegister.Index != fd->DstRegister.Index)
2139 continue;
2140
2141 for (chn = 0; chn < 4; ++chn) {
2142 unsigned s, c;
2143
2144 if (!(mask & (1 << chn))) /* src is not read */
2145 continue;
2146 c = tgsi_util_get_full_src_register_extswizzle(fs, chn);
2147 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2148
2149 if (c > TGSI_EXTSWIZZLE_W ||
2150 !(fd->DstRegister.WriteMask & (1 << c)))
2151 continue;
2152
2153 /* no danger if src is copied to TEMP first */
2154 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2155 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2156 continue;
2157
2158 rdep[c] |= nv50_tgsi_dst_revdep(
2159 insn->Instruction.Opcode, i, chn);
2160 deqs |= (1 << c);
2161 }
2162 }
2163
2164 return deqs;
2165 }
2166
2167 static boolean
2168 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2169 {
2170 struct tgsi_full_instruction insn = tok->FullInstruction;
2171 const struct tgsi_full_dst_register *fd;
2172 unsigned i, deqs, rdep[4], m[4];
2173
2174 fd = &tok->FullInstruction.FullDstRegisters[0];
2175 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2176
2177 if (is_scalar_op(insn.Instruction.Opcode)) {
2178 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2179 if (!pc->r_brdc)
2180 pc->r_brdc = temp_temp(pc);
2181 return nv50_program_tx_insn(pc, &insn);
2182 }
2183 pc->r_brdc = NULL;
2184
2185 if (!deqs)
2186 return nv50_program_tx_insn(pc, &insn);
2187
2188 deqs = nv50_revdep_reorder(m, rdep);
2189
2190 for (i = 0; i < 4; ++i) {
2191 assert(pc->r_dst[m[i]] == NULL);
2192
2193 insn.FullDstRegisters[0].DstRegister.WriteMask =
2194 fd->DstRegister.WriteMask & (1 << m[i]);
2195
2196 if (!insn.FullDstRegisters[0].DstRegister.WriteMask)
2197 continue;
2198
2199 if (deqs & (1 << i))
2200 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2201
2202 if (!nv50_program_tx_insn(pc, &insn))
2203 return FALSE;
2204 }
2205
2206 for (i = 0; i < 4; i++) {
2207 struct nv50_reg *reg = pc->r_dst[i];
2208 if (!reg)
2209 continue;
2210 pc->r_dst[i] = NULL;
2211
2212 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2213 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2214 else
2215 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2216 free_temp(pc, reg);
2217 }
2218
2219 return TRUE;
2220 }
2221
2222 static void
2223 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2224 {
2225 struct nv50_reg *iv, **ppiv;
2226 unsigned mode = pc->interp_mode[reg->index];
2227
2228 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2229 iv = *ppiv;
2230
2231 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2232 iv = *ppiv = alloc_temp(pc, NULL);
2233 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2234
2235 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2236 emit_flop(pc, 0, iv, iv);
2237
2238 /* XXX: when loading interpolants dynamically, move these
2239 * to the program head, or make sure it can't be skipped.
2240 */
2241 }
2242
2243 emit_interp(pc, reg, iv, mode);
2244 }
2245
2246 static boolean
2247 nv50_program_tx_prep(struct nv50_pc *pc)
2248 {
2249 struct tgsi_parse_context tp;
2250 struct nv50_program *p = pc->p;
2251 boolean ret = FALSE;
2252 unsigned i, c, flat_nr = 0;
2253
2254 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2255 while (!tgsi_parse_end_of_tokens(&tp)) {
2256 const union tgsi_full_token *tok = &tp.FullToken;
2257
2258 tgsi_parse_token(&tp);
2259 switch (tok->Token.Type) {
2260 case TGSI_TOKEN_TYPE_IMMEDIATE:
2261 {
2262 const struct tgsi_full_immediate *imm =
2263 &tp.FullToken.FullImmediate;
2264
2265 ctor_immd(pc, imm->u[0].Float,
2266 imm->u[1].Float,
2267 imm->u[2].Float,
2268 imm->u[3].Float);
2269 }
2270 break;
2271 case TGSI_TOKEN_TYPE_DECLARATION:
2272 {
2273 const struct tgsi_full_declaration *d;
2274 unsigned si, last, first, mode;
2275
2276 d = &tp.FullToken.FullDeclaration;
2277 first = d->DeclarationRange.First;
2278 last = d->DeclarationRange.Last;
2279
2280 switch (d->Declaration.File) {
2281 case TGSI_FILE_TEMPORARY:
2282 break;
2283 case TGSI_FILE_OUTPUT:
2284 if (!d->Declaration.Semantic ||
2285 p->type == PIPE_SHADER_FRAGMENT)
2286 break;
2287
2288 si = d->Semantic.SemanticIndex;
2289 switch (d->Semantic.SemanticName) {
2290 case TGSI_SEMANTIC_BCOLOR:
2291 p->cfg.two_side[si].hw = first;
2292 if (p->cfg.io_nr > first)
2293 p->cfg.io_nr = first;
2294 break;
2295 case TGSI_SEMANTIC_PSIZE:
2296 p->cfg.psiz = first;
2297 if (p->cfg.io_nr > first)
2298 p->cfg.io_nr = first;
2299 break;
2300 /*
2301 case TGSI_SEMANTIC_CLIP_DISTANCE:
2302 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2303 break;
2304 */
2305 default:
2306 break;
2307 }
2308 break;
2309 case TGSI_FILE_INPUT:
2310 {
2311 if (p->type != PIPE_SHADER_FRAGMENT)
2312 break;
2313
2314 switch (d->Declaration.Interpolate) {
2315 case TGSI_INTERPOLATE_CONSTANT:
2316 mode = INTERP_FLAT;
2317 flat_nr++;
2318 break;
2319 case TGSI_INTERPOLATE_PERSPECTIVE:
2320 mode = INTERP_PERSPECTIVE;
2321 p->cfg.regs[1] |= 0x08 << 24;
2322 break;
2323 default:
2324 mode = INTERP_LINEAR;
2325 break;
2326 }
2327 if (d->Declaration.Centroid)
2328 mode |= INTERP_CENTROID;
2329
2330 assert(last < 32);
2331 for (i = first; i <= last; i++)
2332 pc->interp_mode[i] = mode;
2333 }
2334 break;
2335 case TGSI_FILE_CONSTANT:
2336 break;
2337 case TGSI_FILE_SAMPLER:
2338 break;
2339 default:
2340 NOUVEAU_ERR("bad decl file %d\n",
2341 d->Declaration.File);
2342 goto out_err;
2343 }
2344 }
2345 break;
2346 case TGSI_TOKEN_TYPE_INSTRUCTION:
2347 pc->insn_nr++;
2348 prep_inspect_insn(pc, &tok->FullInstruction);
2349 break;
2350 default:
2351 break;
2352 }
2353 }
2354
2355 if (p->type == PIPE_SHADER_VERTEX) {
2356 int rid = 0;
2357
2358 for (i = 0; i < pc->attr_nr * 4; ++i) {
2359 if (pc->attr[i].acc) {
2360 pc->attr[i].hw = rid++;
2361 p->cfg.attr[i / 32] |= 1 << (i % 32);
2362 }
2363 }
2364
2365 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2366 p->cfg.io[i].hw = rid;
2367 p->cfg.io[i].id_vp = i;
2368
2369 for (c = 0; c < 4; ++c) {
2370 int n = i * 4 + c;
2371 if (!pc->result[n].acc)
2372 continue;
2373 pc->result[n].hw = rid++;
2374 p->cfg.io[i].mask |= 1 << c;
2375 }
2376 }
2377
2378 for (c = 0; c < 2; ++c)
2379 if (p->cfg.two_side[c].hw < 0x40)
2380 p->cfg.two_side[c] = p->cfg.io[
2381 p->cfg.two_side[c].hw];
2382
2383 if (p->cfg.psiz < 0x40)
2384 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2385 } else
2386 if (p->type == PIPE_SHADER_FRAGMENT) {
2387 int rid, aid;
2388 unsigned n = 0, m = pc->attr_nr - flat_nr;
2389
2390 int base = (TGSI_SEMANTIC_POSITION ==
2391 p->info.input_semantic_name[0]) ? 0 : 1;
2392
2393 /* non-flat interpolants have to be mapped to
2394 * the lower hardware IDs, so sort them:
2395 */
2396 for (i = 0; i < pc->attr_nr; i++) {
2397 if (pc->interp_mode[i] == INTERP_FLAT) {
2398 p->cfg.io[m].id_vp = i + base;
2399 p->cfg.io[m++].id_fp = i;
2400 } else {
2401 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2402 p->cfg.io[n].linear = TRUE;
2403 p->cfg.io[n].id_vp = i + base;
2404 p->cfg.io[n++].id_fp = i;
2405 }
2406 }
2407
2408 if (!base) /* set w-coordinate mask from perspective interp */
2409 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2410
2411 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2412 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2413
2414 for (n = 0; n < pc->attr_nr; ++n) {
2415 p->cfg.io[n].hw = rid = aid;
2416 i = p->cfg.io[n].id_fp;
2417
2418 for (c = 0; c < 4; ++c) {
2419 if (!pc->attr[i * 4 + c].acc)
2420 continue;
2421 pc->attr[i * 4 + c].rhw = rid++;
2422 p->cfg.io[n].mask |= 1 << c;
2423
2424 load_interpolant(pc, &pc->attr[i * 4 + c]);
2425 }
2426 aid += popcnt4(p->cfg.io[n].mask);
2427 }
2428
2429 if (!base)
2430 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2431
2432 m = popcnt4(p->cfg.regs[1] >> 24);
2433
2434 /* set count of non-position inputs and of non-flat
2435 * non-position inputs for FP_INTERPOLANT_CTRL
2436 */
2437 p->cfg.regs[1] |= aid - m;
2438
2439 if (flat_nr) {
2440 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2441 p->cfg.regs[1] |= (i - m) << 16;
2442 } else
2443 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2444
2445 /* mark color semantic for light-twoside */
2446 n = 0x40;
2447 for (i = 0; i < pc->attr_nr; i++) {
2448 ubyte si, sn;
2449
2450 sn = p->info.input_semantic_name[p->cfg.io[i].id_fp];
2451 si = p->info.input_semantic_index[p->cfg.io[i].id_fp];
2452
2453 if (sn == TGSI_SEMANTIC_COLOR) {
2454 p->cfg.two_side[si] = p->cfg.io[i];
2455
2456 /* increase colour count */
2457 p->cfg.regs[0] += popcnt4(
2458 p->cfg.two_side[si].mask) << 16;
2459
2460 n = MIN2(n, p->cfg.io[i].hw - m);
2461 }
2462 }
2463 if (n < 0x40)
2464 p->cfg.regs[0] += n;
2465
2466 /* Initialize FP results:
2467 * FragDepth is always first TGSI and last hw output
2468 */
2469 i = p->info.writes_z ? 4 : 0;
2470 for (rid = 0; i < pc->result_nr * 4; i++)
2471 pc->result[i].rhw = rid++;
2472 if (p->info.writes_z)
2473 pc->result[2].rhw = rid;
2474
2475 p->cfg.high_result = rid;
2476 }
2477
2478 if (pc->immd_nr) {
2479 int rid = 0;
2480
2481 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2482 if (!pc->immd)
2483 goto out_err;
2484
2485 for (i = 0; i < pc->immd_nr; i++) {
2486 for (c = 0; c < 4; c++, rid++)
2487 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2488 }
2489 }
2490
2491 ret = TRUE;
2492 out_err:
2493 if (pc->iv_p)
2494 free_temp(pc, pc->iv_p);
2495 if (pc->iv_c)
2496 free_temp(pc, pc->iv_c);
2497
2498 tgsi_parse_free(&tp);
2499 return ret;
2500 }
2501
2502 static void
2503 free_nv50_pc(struct nv50_pc *pc)
2504 {
2505 if (pc->immd)
2506 FREE(pc->immd);
2507 if (pc->param)
2508 FREE(pc->param);
2509 if (pc->result)
2510 FREE(pc->result);
2511 if (pc->attr)
2512 FREE(pc->attr);
2513 if (pc->temp)
2514 FREE(pc->temp);
2515
2516 FREE(pc);
2517 }
2518
2519 static boolean
2520 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
2521 {
2522 int i, c;
2523 unsigned rtype[2] = { P_ATTR, P_RESULT };
2524
2525 pc->p = p;
2526 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
2527 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
2528 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
2529 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
2530
2531 p->cfg.high_temp = 4;
2532
2533 p->cfg.two_side[0].hw = 0x40;
2534 p->cfg.two_side[1].hw = 0x40;
2535
2536 switch (p->type) {
2537 case PIPE_SHADER_VERTEX:
2538 p->cfg.psiz = 0x40;
2539 p->cfg.clpd = 0x40;
2540 p->cfg.io_nr = pc->result_nr;
2541 break;
2542 case PIPE_SHADER_FRAGMENT:
2543 rtype[0] = rtype[1] = P_TEMP;
2544
2545 p->cfg.regs[0] = 0x01000004;
2546 p->cfg.io_nr = pc->attr_nr;
2547
2548 if (p->info.writes_z) {
2549 p->cfg.regs[2] |= 0x00000100;
2550 p->cfg.regs[3] |= 0x00000011;
2551 }
2552 if (p->info.uses_kill)
2553 p->cfg.regs[2] |= 0x00100000;
2554 break;
2555 }
2556
2557 if (pc->temp_nr) {
2558 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
2559 if (!pc->temp)
2560 return FALSE;
2561
2562 for (i = 0; i < pc->temp_nr * 4; ++i)
2563 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
2564 }
2565
2566 if (pc->attr_nr) {
2567 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
2568 if (!pc->attr)
2569 return FALSE;
2570
2571 for (i = 0; i < pc->attr_nr * 4; ++i)
2572 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
2573 }
2574
2575 if (pc->result_nr) {
2576 unsigned nr = pc->result_nr * 4;
2577
2578 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
2579 if (!pc->result)
2580 return FALSE;
2581
2582 for (i = 0; i < nr; ++i)
2583 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
2584 }
2585
2586 if (pc->param_nr) {
2587 int rid = 0;
2588
2589 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
2590 if (!pc->param)
2591 return FALSE;
2592
2593 for (i = 0; i < pc->param_nr; ++i)
2594 for (c = 0; c < 4; ++c, ++rid)
2595 ctor_reg(&pc->param[rid], P_CONST, i, rid);
2596 }
2597
2598 return TRUE;
2599 }
2600
2601 static void
2602 nv50_fp_move_results(struct nv50_pc *pc)
2603 {
2604 struct nv50_reg reg;
2605 unsigned i;
2606
2607 ctor_reg(&reg, P_TEMP, -1, -1);
2608
2609 for (i = 0; i < pc->result_nr * 4; ++i) {
2610 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2611 continue;
2612 if (pc->result[i].rhw != pc->result[i].hw) {
2613 reg.hw = pc->result[i].rhw;
2614 emit_mov(pc, &reg, &pc->result[i]);
2615 }
2616 }
2617 }
2618
2619 static void
2620 nv50_program_fixup_insns(struct nv50_pc *pc)
2621 {
2622 struct nv50_program_exec *e, *prev = NULL, **bra_list;
2623 unsigned i, n, pos;
2624
2625 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
2626
2627 /* Collect branch instructions, we need to adjust their offsets
2628 * when converting 32 bit instructions to 64 bit ones
2629 */
2630 for (n = 0, e = pc->p->exec_head; e; e = e->next)
2631 if (e->param.index >= 0 && !e->param.mask)
2632 bra_list[n++] = e;
2633
2634 /* Make sure we don't have any single 32 bit instructions. */
2635 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
2636 pos += is_long(e) ? 2 : 1;
2637
2638 if ((pos & 1) && (!e->next || is_long(e->next))) {
2639 for (i = 0; i < n; ++i)
2640 if (bra_list[i]->param.index >= pos)
2641 bra_list[i]->param.index += 1;
2642 convert_to_long(pc, e);
2643 ++pos;
2644 }
2645 if (e->next)
2646 prev = e;
2647 }
2648
2649 assert(!is_immd(pc->p->exec_head));
2650 assert(!is_immd(pc->p->exec_tail));
2651
2652 /* last instruction must be long so it can have the end bit set */
2653 if (!is_long(pc->p->exec_tail)) {
2654 convert_to_long(pc, pc->p->exec_tail);
2655 if (prev)
2656 convert_to_long(pc, prev);
2657 }
2658 assert(!(pc->p->exec_tail->inst[1] & 2));
2659 /* set the end-bit */
2660 pc->p->exec_tail->inst[1] |= 1;
2661
2662 FREE(bra_list);
2663 }
2664
2665 static boolean
2666 nv50_program_tx(struct nv50_program *p)
2667 {
2668 struct tgsi_parse_context parse;
2669 struct nv50_pc *pc;
2670 boolean ret;
2671
2672 pc = CALLOC_STRUCT(nv50_pc);
2673 if (!pc)
2674 return FALSE;
2675
2676 ret = ctor_nv50_pc(pc, p);
2677 if (ret == FALSE)
2678 goto out_cleanup;
2679
2680 ret = nv50_program_tx_prep(pc);
2681 if (ret == FALSE)
2682 goto out_cleanup;
2683
2684 tgsi_parse_init(&parse, pc->p->pipe.tokens);
2685 while (!tgsi_parse_end_of_tokens(&parse)) {
2686 const union tgsi_full_token *tok = &parse.FullToken;
2687
2688 /* don't allow half insn/immd on first and last instruction */
2689 pc->allow32 = TRUE;
2690 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
2691 pc->allow32 = FALSE;
2692
2693 tgsi_parse_token(&parse);
2694
2695 switch (tok->Token.Type) {
2696 case TGSI_TOKEN_TYPE_INSTRUCTION:
2697 ++pc->insn_cur;
2698 ret = nv50_tgsi_insn(pc, tok);
2699 if (ret == FALSE)
2700 goto out_err;
2701 break;
2702 default:
2703 break;
2704 }
2705 }
2706
2707 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2708 nv50_fp_move_results(pc);
2709
2710 nv50_program_fixup_insns(pc);
2711
2712 p->param_nr = pc->param_nr * 4;
2713 p->immd_nr = pc->immd_nr * 4;
2714 p->immd = pc->immd_buf;
2715
2716 out_err:
2717 tgsi_parse_free(&parse);
2718
2719 out_cleanup:
2720 free_nv50_pc(pc);
2721 return ret;
2722 }
2723
2724 static void
2725 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
2726 {
2727 if (nv50_program_tx(p) == FALSE)
2728 assert(0);
2729 p->translated = TRUE;
2730 }
2731
2732 static void
2733 nv50_program_upload_data(struct nv50_context *nv50, float *map,
2734 unsigned start, unsigned count, unsigned cbuf)
2735 {
2736 struct nouveau_channel *chan = nv50->screen->base.channel;
2737 struct nouveau_grobj *tesla = nv50->screen->tesla;
2738
2739 while (count) {
2740 unsigned nr = count > 2047 ? 2047 : count;
2741
2742 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
2743 OUT_RING (chan, (cbuf << 0) | (start << 8));
2744 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
2745 OUT_RINGp (chan, map, nr);
2746
2747 map += nr;
2748 start += nr;
2749 count -= nr;
2750 }
2751 }
2752
2753 static void
2754 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
2755 {
2756 struct pipe_screen *pscreen = nv50->pipe.screen;
2757
2758 if (!p->data[0] && p->immd_nr) {
2759 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
2760
2761 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
2762 while (heap->next && heap->size < p->immd_nr) {
2763 struct nv50_program *evict = heap->next->priv;
2764 nouveau_resource_free(&evict->data[0]);
2765 }
2766
2767 if (nouveau_resource_alloc(heap, p->immd_nr, p,
2768 &p->data[0]))
2769 assert(0);
2770 }
2771
2772 /* immediates only need to be uploaded again when freed */
2773 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
2774 p->immd_nr, NV50_CB_PMISC);
2775 }
2776
2777 assert(p->param_nr <= 128);
2778
2779 if (p->param_nr) {
2780 unsigned cb;
2781 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
2782 PIPE_BUFFER_USAGE_CPU_READ);
2783
2784 if (p->type == PIPE_SHADER_VERTEX)
2785 cb = NV50_CB_PVP;
2786 else
2787 cb = NV50_CB_PFP;
2788
2789 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
2790 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
2791 }
2792 }
2793
2794 static void
2795 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
2796 {
2797 struct nouveau_channel *chan = nv50->screen->base.channel;
2798 struct nouveau_grobj *tesla = nv50->screen->tesla;
2799 struct nv50_program_exec *e;
2800 struct nouveau_stateobj *so;
2801 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR;
2802 unsigned start, count, *up, *ptr;
2803 boolean upload = FALSE;
2804
2805 if (!p->bo) {
2806 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
2807 p->exec_size * 4, &p->bo);
2808 upload = TRUE;
2809 }
2810
2811 if (p->data[0] && p->data[0]->start != p->data_start[0])
2812 upload = TRUE;
2813
2814 if (!upload)
2815 return;
2816
2817 for (e = p->exec_head; e; e = e->next) {
2818 unsigned ei, ci, bs;
2819
2820 if (e->param.index < 0)
2821 continue;
2822
2823 if (e->param.mask == 0) {
2824 assert(!(e->param.index & 1));
2825 /* seem to be 8 byte steps */
2826 ei = (e->param.index >> 1) + 0 /* START_ID */;
2827
2828 e->inst[0] &= 0xf0000fff;
2829 e->inst[0] |= ei << 12;
2830 continue;
2831 }
2832
2833 bs = (e->inst[1] >> 22) & 0x07;
2834 assert(bs < 2);
2835 ei = e->param.shift >> 5;
2836 ci = e->param.index;
2837 if (bs == 0)
2838 ci += p->data[bs]->start;
2839
2840 e->inst[ei] &= ~e->param.mask;
2841 e->inst[ei] |= (ci << e->param.shift);
2842 }
2843
2844 if (p->data[0])
2845 p->data_start[0] = p->data[0]->start;
2846
2847 #ifdef NV50_PROGRAM_DUMP
2848 NOUVEAU_ERR("-------\n");
2849 for (e = p->exec_head; e; e = e->next) {
2850 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
2851 if (is_long(e))
2852 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
2853 }
2854 #endif
2855
2856 up = ptr = MALLOC(p->exec_size * 4);
2857 for (e = p->exec_head; e; e = e->next) {
2858 *(ptr++) = e->inst[0];
2859 if (is_long(e))
2860 *(ptr++) = e->inst[1];
2861 }
2862
2863 so = so_new(4,2);
2864 so_method(so, nv50->screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
2865 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_HIGH, 0, 0);
2866 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_LOW, 0, 0);
2867 so_data (so, (NV50_CB_PUPLOAD << 16) | 0x0800); //(p->exec_size * 4));
2868
2869 start = 0; count = p->exec_size;
2870 while (count) {
2871 struct nouveau_channel *chan = nv50->screen->base.channel;
2872 unsigned nr;
2873
2874 so_emit(chan, so);
2875
2876 nr = MIN2(count, 2047);
2877 nr = MIN2(chan->pushbuf->remaining, nr);
2878 if (chan->pushbuf->remaining < (nr + 3)) {
2879 FIRE_RING(chan);
2880 continue;
2881 }
2882
2883 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
2884 OUT_RING (chan, (start << 8) | NV50_CB_PUPLOAD);
2885 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
2886 OUT_RINGp (chan, up + start, nr);
2887
2888 start += nr;
2889 count -= nr;
2890 }
2891
2892 FREE(up);
2893 so_ref(NULL, &so);
2894 }
2895
2896 void
2897 nv50_vertprog_validate(struct nv50_context *nv50)
2898 {
2899 struct nouveau_grobj *tesla = nv50->screen->tesla;
2900 struct nv50_program *p = nv50->vertprog;
2901 struct nouveau_stateobj *so;
2902
2903 if (!p->translated) {
2904 nv50_program_validate(nv50, p);
2905 if (!p->translated)
2906 assert(0);
2907 }
2908
2909 nv50_program_validate_data(nv50, p);
2910 nv50_program_validate_code(nv50, p);
2911
2912 so = so_new(13, 2);
2913 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
2914 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2915 NOUVEAU_BO_HIGH, 0, 0);
2916 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2917 NOUVEAU_BO_LOW, 0, 0);
2918 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
2919 so_data (so, p->cfg.attr[0]);
2920 so_data (so, p->cfg.attr[1]);
2921 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
2922 so_data (so, p->cfg.high_result);
2923 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
2924 so_data (so, p->cfg.high_result); //8);
2925 so_data (so, p->cfg.high_temp);
2926 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
2927 so_data (so, 0); /* program start offset */
2928 so_ref(so, &nv50->state.vertprog);
2929 so_ref(NULL, &so);
2930 }
2931
2932 void
2933 nv50_fragprog_validate(struct nv50_context *nv50)
2934 {
2935 struct nouveau_grobj *tesla = nv50->screen->tesla;
2936 struct nv50_program *p = nv50->fragprog;
2937 struct nouveau_stateobj *so;
2938
2939 if (!p->translated) {
2940 nv50_program_validate(nv50, p);
2941 if (!p->translated)
2942 assert(0);
2943 }
2944
2945 nv50_program_validate_data(nv50, p);
2946 nv50_program_validate_code(nv50, p);
2947
2948 so = so_new(64, 2);
2949 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
2950 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2951 NOUVEAU_BO_HIGH, 0, 0);
2952 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2953 NOUVEAU_BO_LOW, 0, 0);
2954 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
2955 so_data (so, p->cfg.high_temp);
2956 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
2957 so_data (so, p->cfg.high_result);
2958 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
2959 so_data (so, p->cfg.regs[2]);
2960 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
2961 so_data (so, p->cfg.regs[3]);
2962 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
2963 so_data (so, 0); /* program start offset */
2964 so_ref(so, &nv50->state.fragprog);
2965 so_ref(NULL, &so);
2966 }
2967
2968 static void
2969 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
2970 {
2971 struct nv50_program *fp = nv50->fragprog;
2972 struct nv50_program *vp = nv50->vertprog;
2973 unsigned i, c, m = base;
2974
2975 /* XXX: This can't work correctly in all cases yet, we either
2976 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
2977 * to be per FP input instead of per VP output
2978 */
2979 memset(pntc, 0, 8 * sizeof(uint32_t));
2980
2981 for (i = 0; i < fp->cfg.io_nr; i++) {
2982 uint8_t sn, si;
2983 uint8_t j = fp->cfg.io[i].id_vp, k = fp->cfg.io[i].id_fp;
2984 unsigned n = popcnt4(fp->cfg.io[i].mask);
2985
2986 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
2987 m += n;
2988 continue;
2989 }
2990
2991 sn = vp->info.input_semantic_name[j];
2992 si = vp->info.input_semantic_index[j];
2993
2994 if (j < fp->cfg.io_nr && sn == TGSI_SEMANTIC_GENERIC) {
2995 ubyte mode =
2996 nv50->rasterizer->pipe.sprite_coord_mode[si];
2997
2998 if (mode == PIPE_SPRITE_COORD_NONE) {
2999 m += n;
3000 continue;
3001 }
3002 }
3003
3004 /* this is either PointCoord or replaced by sprite coords */
3005 for (c = 0; c < 4; c++) {
3006 if (!(fp->cfg.io[i].mask & (1 << c)))
3007 continue;
3008 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3009 ++m;
3010 }
3011 }
3012 }
3013
3014 static int
3015 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3016 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3017 {
3018 int c;
3019 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3020 uint8_t *map = (uint8_t *)p_map;
3021
3022 for (c = 0; c < 4; ++c) {
3023 if (mf & 1) {
3024 if (fpi->linear == TRUE)
3025 lin[mid / 32] |= 1 << (mid % 32);
3026 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3027 }
3028
3029 oid += mv & 1;
3030 mf >>= 1;
3031 mv >>= 1;
3032 }
3033
3034 return mid;
3035 }
3036
3037 void
3038 nv50_linkage_validate(struct nv50_context *nv50)
3039 {
3040 struct nouveau_grobj *tesla = nv50->screen->tesla;
3041 struct nv50_program *vp = nv50->vertprog;
3042 struct nv50_program *fp = nv50->fragprog;
3043 struct nouveau_stateobj *so;
3044 struct nv50_sreg4 dummy, *vpo;
3045 int i, n, c, m = 0;
3046 uint32_t map[16], lin[4], reg[5], pcrd[8];
3047
3048 memset(map, 0, sizeof(map));
3049 memset(lin, 0, sizeof(lin));
3050
3051 reg[1] = 0x00000004; /* low and high clip distance map ids */
3052 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3053 reg[3] = 0x00000000; /* point size map id & enable */
3054 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3055 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3056
3057 dummy.linear = FALSE;
3058 dummy.mask = 0xf; /* map all components of HPOS */
3059 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3060
3061 dummy.mask = 0x0;
3062
3063 if (vp->cfg.clpd < 0x40) {
3064 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3065 map[m++] = vp->cfg.clpd + c;
3066 reg[1] = (m << 8);
3067 }
3068
3069 reg[0] |= m << 8; /* adjust BFC0 id */
3070
3071 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3072 if (nv50->rasterizer->pipe.light_twoside) {
3073 vpo = &vp->cfg.two_side[0];
3074
3075 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3076 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3077 }
3078
3079 reg[0] += m - 4; /* adjust FFC0 id */
3080 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3081
3082 i = 0;
3083 if (fp->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION)
3084 i = 1;
3085 for (; i < fp->cfg.io_nr; i++) {
3086 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id_fp];
3087 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id_fp];
3088
3089 n = fp->cfg.io[i].id_vp;
3090 if (n >= vp->cfg.io_nr ||
3091 vp->info.output_semantic_name[n] != sn ||
3092 vp->info.output_semantic_index[n] != si)
3093 vpo = &dummy;
3094 else
3095 vpo = &vp->cfg.io[n];
3096
3097 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3098 }
3099
3100 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3101 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3102 reg[3] = (m++ << 4) | 1;
3103 }
3104
3105 /* now fill the stateobj */
3106 so = so_new(64, 0);
3107
3108 n = (m + 3) / 4;
3109 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3110 so_data (so, m);
3111 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3112 so_datap (so, map, n);
3113
3114 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3115 so_datap (so, reg, 4);
3116
3117 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3118 so_data (so, reg[4]);
3119
3120 so_method(so, tesla, 0x1540, 4);
3121 so_datap (so, lin, 4);
3122
3123 if (nv50->rasterizer->pipe.point_sprite) {
3124 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3125
3126 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3127 so_datap (so, pcrd, 8);
3128 }
3129
3130 so_ref(so, &nv50->state.programs);
3131 so_ref(NULL, &so);
3132 }
3133
3134 void
3135 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3136 {
3137 while (p->exec_head) {
3138 struct nv50_program_exec *e = p->exec_head;
3139
3140 p->exec_head = e->next;
3141 FREE(e);
3142 }
3143 p->exec_tail = NULL;
3144 p->exec_size = 0;
3145
3146 nouveau_bo_ref(NULL, &p->bo);
3147
3148 nouveau_resource_free(&p->data[0]);
3149
3150 p->translated = 0;
3151 }